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Verilog Record

The document outlines the assessment structure for the Logic Design using Verilog course at Dr TMA Pai Polytechnic Manipal, detailing various Continuous Internal Evaluation (CIE) components and their maximum marks. It includes written tests, skill tests, and portfolio evaluations, totaling 60 marks. Additionally, it lists experiments with associated marks and linked Course Outcomes (CO) for practical assessments.

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npavan.16.42
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119 views3 pages

Verilog Record

The document outlines the assessment structure for the Logic Design using Verilog course at Dr TMA Pai Polytechnic Manipal, detailing various Continuous Internal Evaluation (CIE) components and their maximum marks. It includes written tests, skill tests, and portfolio evaluations, totaling 60 marks. Additionally, it lists experiments with associated marks and linked Course Outcomes (CO) for practical assessments.

Uploaded by

npavan.16.42
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dr TMA Pai Polytechnic Manipal

Sl. No Assessment Maximum Obtained Conversion


Marks Marks
1 CIE-1 Written test 30 Average of
CIE1, CIE2 & CIE3
2 CIE-2 Written test 30

3 CIE-3 Written test 30

4 CIE-4 Skill Test- 100/20 Average of


CIE4&CIE5(20marks)
Practice
5 CIE-5 Skill Test- 100/20
Practice
6 CIE-6 Portfolio 10
continuous
evaluation of Tutorial
sessions through Rubrics
Total CIE (60 Marks)

Student Signature Course Coordinator Program coordinator

Department of E&C Engineering Logic Design using Verilog 20EC32P


Dr TMA Pai Polytechnic Manipal

EX
No. EXPERIMENT NAME LINKED MARKS
CO max obtained
1 C02 10
Clocked SR Flip-flop
2 C02 10
D&T Flip-flop
3 Ring counter C03 10

4 Johnson counter C03 10

5 2-bit counter C03 10

6 Shift register C02 10

7 Basic gates (basic 21-codes) C01 10

8 Half adder (basic 3-codes) C01 10

9 Full adder (basic 3-codes) C01 10

10 Half subtractor (basic 3-codes) C01 10

11 Full subtractor (basic 3-codes) C01 10

12 2:1 Multiplexer(3-codes) C03 10

13 2:1 Multiplexer using “if-else” C03 10

14 4:1 Multiplexer (basic 3-codes) C03 10

15 1:2 demux(basic 3-codes) C03 10

16 1:4 demux(basic 3-codes) C03 10

17 D-Flipflop using “if-else” C02 10

18 T-Flip-flop using “if-else” C02 10

19 2:1 mux using “case” statement C04 10

20 4:1 mux using “case” statement C04 10

21 ALU(2-bit) using “case” statement C04 10

22 Seven segment display using “case” C04 10


statement

Department of E&C Engineering Logic Design using Verilog 20EC32P


Dr TMA Pai Polytechnic Manipal

EX No. Marks Split Rubrics wise


Total Average Marks
A B C D
1

10

12
13

14

15

16

17

18

19

20

21

22

Student Signature Course Coordinator Program coordinator

Department of E&C Engineering Logic Design using Verilog 20EC32P

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