Data Hazards:

Forwarding versus Stalling

•
Consider this
sequence: SUB X2,
X1,X3 AND
X12,X2,X5 OR
X13,X6,X2
ADD X14,X2,X2
STUR X15,[X2,#100]

•
We can resolve hazards with forwarding
– How do we detect when to forward?
 Dependencies & Forwarding

FIGURE 4.51
 Detecting the Need to Forward
•
Pass register numbers along pipeline
–
e.g., ID/EX.RegisterRs = register number for Rs sitting
in ID/EX pipeline register
•
ALU operand register numbers in EX stage
are given by
–
ID/EX.RegisterRn1, ID/EX.RegisterRm2
•
Data hazards when
Fwd from
1a. EX/MEM.RegisterRd = ID/EX.RegisterRn1 EX/MEM
1b. EX/MEM.RegisterRd = ID/EX.RegisterRm2 pipeline reg

2a. MEM/WB.RegisterRd = ID/EX.RegisterRn1 Fwd from

2b. MEM/WB.RegisterRd = ID/EX.RegisterRm2 MEM/WB
pipeline reg
 Detecting the Need to Forward
•
But only if forwarding instruction will write
to a register!
– EX/MEM.RegWrite, MEM/WB.RegWrite

•
And only if Rd for that instruction is not XZR
– EX/MEM.RegisterRd ≠ 31,
MEM/WB.RegisterRd ≠ 31
FIGURE 4.52
 Forwarding Paths

FIGURE 4.53
 Forwarding Conditions
Mux control Source Explanation
ForwardA = 00 ID/EX The first ALU operand comes from the register file.
ForwardA = 10 EX/MEM The first ALU operand is forwarded from the prior ALU
result.
ForwardA = 01 MEM/WB The first ALU operand is forwarded from data memory or
an earlier
ALU result.
ForwardB = 00 ID/EX The second ALU operand comes from the register file.

ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior ALU
result.
ForwardB = 01 MEM/WB The second ALU operand is forwarded from data memory
or an
earlier ALU result.

FIGURE 4.54 The control values for the forwarding multiplexors in Figure 4.53.
 Double Data Hazard
• Consider the sequence:
add X1,X1,X2
add X1,X1,X3
add X1,X1,X4
• Both hazards occur
– Want to use the most recent
• Revise MEM hazard condition
– Only fwd if EX hazard condition isn’t true
 Revised Forwarding Condition

• MEM hazard
– if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 31)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 31)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRn1))
and (MEM/WB.RegisterRd = ID/EX.RegisterRn1)) ForwardA = 01
– if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 31)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 31)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRm2))
and (MEM/WB.RegisterRd = ID/EX.RegisterRm2)) ForwardB = 01
 Datapath with Forwarding

FIGURE 4.55 The datapath modified to resolve hazards via forwarding

FIGURE 4.56
Datapath with Forwarding

FIGURE 4.57 A
pipelined sequence of
instructions
 Load-Use Hazard Detection
• Check when using instruction is decoded in ID
stage
• ALU operand register numbers in ID stage
are given by
– IF/ID.RegisterRn1, IF/ID.RegisterRm2
• Load-use hazard when
– If (ID/EX.MemRead and
((ID/EX.RegisterRd = IF/ID.RegisterRn1) or
(ID/EX.RegisterRd = IF/ID.RegisterRm2))
• If detected, stall and insert bubble
 How to Stall the Pipeline
• Force control values in ID/EX register to 0
– EX, MEM and WB do nop (no-operation)
• Prevent update of PC and IF/ID register
– Using instruction is decoded again
– Following instruction is fetched again
– 1-cycle stall allows MEM to read data for LDUI
•
Can subsequently forward to EX stage
Load-Use Data Hazard

Stall inserted
here

FIGURE 4.58
 Datapath with Hazard Detection

FIGURE 4.59
 Stalls and Performance
The BIG Picture
•
Stalls reduce performance
–
But are required to get correct results
•
Compiler can arrange code to avoid
hazards and stalls
–
Requires knowledge of the pipeline structure
Control Hazards
 Branch Hazards
•
If branch outcome determined in MEM

Flush these
instructions
(Set control
values to 0)

PC

FIGURE 4.60 The impact of the pipeline on the branch instruction

 Reducing Branch Delay
• Move hardware to determine outcome to ID stage
– Target address adder
– Register comparator
• Example: branch taken
36: SUB X10, X4, X8
40: CBZ X1, X3, 8// PC-relative branch to
40+8 4=72
* AND X12, X2, X5
44:
48: ORR X13, X2, X6
52: ADD X14, X4, X2
56: SUB X15, X6, X7
...
72: LDUR X4, [X7,#50]
 Example: Branch Taken

FIGURE 4.61 a
 Example: Branch Taken

FIGURE 4.61 b
 Dynamic Branch Prediction
• In deeper and superscalar pipelines, branch
penalty is more significant
• Use dynamic prediction
– Branch prediction buffer (aka branch history table)
– Indexed by recent branch instruction addresses
– Stores outcome (taken/not taken)
– To execute a branch
•
Check table, expect the same outcome
•
Start fetching from fall-through or target
•
If wrong, flush pipeline and flip prediction
 1-Bit Predictor: Shortcoming
•
Inner loop branches mispredicted twice!
outer: …
…
inner: …
…
CBZ …, …, inner
…
CBZ …, …, outer


Mispredict as taken on last
iteration of inner loop

Then mispredict as not taken on
first iteration of inner loop next
time around
 2-Bit Predictor
•
Only change prediction on two
successive mispredictions

FIGURE 4.62 The states in a 2-bit prediction scheme

 Exceptions and Interrupts
• “Unexpected” events requiring
change in flow of control
– Different ISAs use the terms differently
• Exception
– Arises within the CPU
•
e.g., undefined opcode, overflow, syscall, …
• Interrupt
– From an external I/O controller
• Dealing with them without sacrificing performance
is hard
Here are examples showing whether the situation is
internally generated by the processor or externally
generated and the name that ARM uses:
 Handling Exceptions
• Save PC of offending (or interrupted) instruction
– In LEGv8: Exception Link Register (ELR)

• Save indication of the problem

– In LEGv8: Exception Syndrome Register (ESR)
– We’ll assume 1-bit
•
0 for undefined opcode, 1 for overflow
 An Alternate Mechanism
• Vectored Interrupts
– Handler address determined by the cause
• Exception vector address to be added to a vector
table base register:
– Unknown Reason: 00 0000two
– Overflow: 10 1100two
– …: 11 1111two
• Instructions either
– Deal with the interrupt, or
– Jump to real handler
 Exceptions in a Pipeline
• Another form of control hazard
• Consider overflow on add in EX stage
ADD X1, X2, X1
– Prevent X1 from being clobbered
– Complete previous instructions
– Flush add and subsequent instructions
– Set ESR and ELR register values
– Transfer control to handler
• Similar to mispredicted branch
– Use much of the same hardware
 Pipeline with Exceptions

FIGURE 4.64
 Exception Example
• Exception on ADD in
40 SUB X11, X2, X4
44 AND X12, X2, X5
48 ORR X13, X2, X6
4C ADD X1, X2, X1
50 SUB X15, X6, X7
54 LDUR X16, [X7,#100]
…
• Handler
80000180 STUR X26, [X0,#1000]
80000184 STUR X27, [X0,#1008]
…
 Exception Example

FIGURE 4.65 Clock 6

 Exception Example

FIGURE 4.65 Clock 7

Parallelism via Instructions
 Instruction-Level Parallelism (ILP)

• Pipelining: executing multiple instructions in parallel

• To increase ILP
– Deeper pipeline
•
Less work per stage  shorter clock cycle
– Multiple issue
•
Replicate pipeline stages  multiple pipelines
•
Start multiple instructions per clock cycle
•
CPI < 1, so use Instructions Per Cycle (IPC)
•
E.g., 4GHz 4-way multiple-issue
– 16 BIPS, peak CPI = 0.25, peak IPC = 4
•
But dependencies reduce this in practice
 Multiple Issue
• Static multiple issue
– Compiler groups instructions to be issued together
– Packages them into “issue slots”
– Compiler detects and avoids hazards
• Dynamic multiple issue
– CPU examines instruction stream and chooses
instructions to issue each cycle
– Compiler can help by reordering instructions
– CPU resolves hazards using advanced techniques
at runtime
 Speculation
• “Guess” what to do with an instruction
– Start operation as soon as possible
– Check whether guess was right
•
If so, complete the operation
•
If not, roll-back and do the right thing

• Common to static and dynamic multiple issue

• Examples
– Speculate on branch outcome
•
Roll back if path taken is different
– Speculate on load
•
Roll back if location is updated
 Compiler/Hardware Speculation
• Compiler can reorder instructions
– e.g., move load before branch
– Can include “fix-up” instructions to recover
from incorrect guess
• Hardware can look ahead for instructions
to execute
– Buffer results until it determines they are
actually needed
– Flush buffers on incorrect speculation
 Speculation and Exceptions
• What if exception occurs on a
speculatively executed instruction?
– e.g., speculative load before null-pointer check
• Static speculation
– Can add ISA support for deferring exceptions
• Dynamic speculation
– Can buffer exceptions until instruction
completion (which may not occur)
 Static Multiple Issue
• Compiler groups instructions into “issue
packets”
– Group of instructions that can be issued on a single
cycle
– Determined by pipeline resources required
• Think of an issue packet as a very long
instruction
– Specifies multiple concurrent operations
–  Very Long Instruction Word (VLIW)
 Scheduling Static Multiple Issue
• Compiler must remove some/all hazards
– Reorder instructions into issue packets
– No dependencies with a packet
– Possibly some dependencies between packets
•
Varies between ISAs; compiler must know!
– Pad with nop if necessary
 LEGv8 with Static Dual Issue
•
Two-issue packets
–
One ALU/branch instruction
–
One load/store instruction
–
64-bit aligned
•
ALU/branch, then load/store
•
Pad an unused instruction with nop

Address Instruction type Pipeline Stages

n ALU/branch IF ID EX MEM WB
n+4 Load/store IF ID EX MEM WB
n+8 ALU/branch IF ID EX MEM WB
n + 12 Load/store IF ID EX MEM WB
n + 16 ALU/branch IF ID EX MEM WB
n + 20 Load/store IF ID EX MEM WB

FIGURE 4.66
 LEGv8 with Static Dual Issue

FIGURE 4.67
use latency

Number of clock cycles between a

load instruction and an instruction
that can use the result of the load
without stalling the pipeline.
 Hazards in the Dual-Issue LEGv8

•
More instructions executing in parallel
•
EX data hazard
–
Forwarding avoided stalls with single-issue
–
Now can’t use ALU result in load/store in same packet
•
ADD X0, X0, X1
LDUR X2, [X0,#0]
•
Split into two packets, effectively a stall
•
Load-use hazard
–
Still one cycle use latency, but now two instructions
•
More aggressive scheduling required
 Scheduling Example
•
Schedule this for dual-issue LEGv8
Loop: LDUR X0, [X20,#0] //
X0=array element
ADD X0, X0,X21 //
add scalar in X21
STUR X0, [X20,#0] //
store result
SUBI X20, X20,#4 //
decrement pointer
CMP X20, X22 //
branch $s1!=0
BGT Loop

ALU/branch Load/store cycle

Loop: nop LDUR X0, [X20,#0] 1
SUBI X20, X20,#4 nop 2
ADD X0, X0,X21 nop 3
CMP X20, X22 nop 4
BGT Loop STUR X0, [X20,#0] 5

FIGURE 4.68
 Loop Unrolling
• Replicate loop body to expose
more parallelism
– Reduces loop-control overhead
• Use different registers per replication
– Called “register renaming”
– Avoid loop-carried “anti-dependencies”
• Store followed by a load of the same register
• Aka “name dependence”
– Reuse of a register name
 Loop Unrolling Example
ALU/branch Load/store cycle
Loop: SUBI X20, X20,#32 LDUR X0, [X20,#0] 1
nop LDUR X1, [X20,#24] 2
ADD X0, X0, X21 LDUR X2, [X20,#16] 3
ADD X1, X1, X21 LDUR X3, [X20,#8] 4
ADD X2, X2, X21 STUR X0, [X20,#32] 5
ADD X3, X3, X21 sw X1, [X20,#24] 6
CMP X20,X22 sw X2, [X20,#16] 7
BGT Loop sw X3, [X20,#8] 8

Figure 4.69

•
IPC = 15/8 = 1.875
– Closer to 2, but at cost of registers and code size
Dynamic Multiple-Issue Processors

• “Superscalar” processors
• CPU decides whether to issue 0, 1, 2, …
each cycle
– Avoiding structural and data hazards
• Avoids the need for compiler scheduling
– Though it may still help
– Code semantics ensured by the CPU
 Dynamic Pipeline Scheduling
• Allow the CPU to execute instructions out
of order to avoid stalls
– But commit result to registers in order
• Example
LDUR X0, [X21,#20]
ADD X1, X0, X2 SUB
X23,X23,X3 ANDI X5,
X23,#20
– Can start sub while ADD is waiting for LDUI
 Dynamically Scheduled CPU
Preserves
dependencies

Hold pending
operands

Reorders buffer for Results also sent to

register writes any waiting
reservation stations

Can supply operands

for issued
instructions
FIGURE 4.70
 Why Do Dynamic Scheduling?
• Why not just let the compiler schedule code?
• Not all stalls are predicable
– e.g., cache misses
• Can’t always schedule around branches
– Branch outcome is dynamically determined
• Different implementations of an ISA
have different latencies and hazards
 Does Multiple Issue Work?
The BIG Picture
•
Yes, but not as much as we’d like
•
Programs have real dependencies that limit ILP
•
Some dependencies are hard to eliminate
–
e.g., pointer aliasing
•
Some parallelism is hard to expose
–
Limited window size during instruction issue
•
Memory delays and limited bandwidth
–
Hard to keep pipelines full
•
Speculation can help if done well
 Power Efficiency
• Complexity of dynamic scheduling
and speculations requires power
• Multiple simpler cores may be better
Microprocessor Year Clock Rate Pipeline Issu Out-of- Cores Power
Stages e order/
widt Speculation
h
i486 1989 25MHz 5 1 No 1 5W
Pentium 1993 66MHz 5 2 No 1 10W
Pentium Pro 1997 200MHz 10 3 Yes 1 29W
P4 Willamette 2001 2000MHz 22 3 Yes 1 75W
P4 Prescott 2004 3600MHz 31 3 Yes 1 103W
Core 2006 2930MHz 14 4 Yes 2 75W
UltraSparc III 2003 1950MHz 14 4 No 1 90W
UltraSparc T1 2005 1200MHz 6 1 No 8 70W
FIGURE 4.71
Seach

Apple M1 vs Intel Core i9-10980HK

 Fallacies
• Pipelining is easy (!)
– The basic idea is easy
– The devil is in the details
• e.g., detecting data hazards
• Pipelining is independent of technology
– So why haven’t we always done pipelining?
– More transistors make more advanced techniques feasible
– Pipeline-related ISA design needs to take account
of technology trends
• e.g., predicated instructions
 Concluding Remarks
• ISA influences design of datapath and control
• Datapath and control influence design of ISA
• Pipelining improves instruction throughput
using parallelism
– More instructions completed per second
– Latency for each instruction not reduced
• Hazards: structural, data, control
• Multiple issue and dynamic scheduling (ILP)
– Dependencies limit achievable parallelism
– Complexity leads to the power wall