4018-06 Printed Pages: 8|
MCA(2 Years) (Sem. -1) Examination, 2021
(Session : 2020-22)
COMPUTER ORGANIZATION AND
ARCHITECTURE
[Subjectcode: PPU-MCA-CC-6]
IMaximum Marks : 70|
Time: Three Hours]
their own
Note: Candidates are required to givetheir answêrs in
words as far as practicable. Section-A is compulsory,
two marks
consisting of ten questions carrying
each.Section-B contains six questions
carrying five
students have to attempt any four
marks each and
contains five questions carrying ten
questions. Section-C
three ques-
have to attempt any
marks each and student
tions.
SECTION-A
[10x2=20]
Note Multiple choice questions
connects several devices
collection of lines that
A
1 )
iscalled:
[P.T.O.]
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(1)
(a Bus
the timee
is
The access time of memory
(iv)
(b) Peripheral connection single CPU
required for performing any
(c) Both (a) and (b) operation.
Shorter than
(d) Internal wires (a)
(i) Which memory unit has lowest access (b)
Negligible than
time?
(a) Cache Same as
(c)
(b Registers d Longer than
(c) Magnetic Disk can be
(v) The performance of Cache Memory
(d) Main Memory representedas
(ii) Which one of the of hits / total CPU references to
following is the address (a) number
generated by CPU ? the memory
(a) Physical address
(b number of hits/ (number of hits+number
(b) of misses
Absolute address
Logical address (c) numberofmiss/ (number of hits+number
of misses
(d) None of the above
(d) Both (a) and (b)
06/450
(2)
4018-06/450 (3) P.T.O.]
(vi) The processing required for a single instruction (c) 1 GB
iscalled
(d) 4 GB
(a) Instruction cycle
Which of the following affects processing
(ix)
(b) Processing cycle power?
(c) Execution cycle Data bus capacity
(a)
(d) Data cycle Addressing schemne
(b)
(vii) Control Units are designed using which of the (c) Clock speed
following approach?
d All of the above
(a) Hardwired approach
a means for
(x) The hardware device that provides
(b) Microprogramming approach information between central systen
transferring
and external 1/0 perripheral device.
(c Both (a) and (b)
(a /O Controller
(d) None of the above
(b) /O Driver
(Vii) A 32 bit address bus allows access to a
memory
of capacity. Both (a) and (b)
(c)
(a) 64 MB
(d) None of the above
1 6 16 MB SECTION-B
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4) (5) P.T.O]
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(ii) Bus system
[4x5=201
Note : Answer any four questions of the fallowing
(iv) Universal gate
combinational circuit ? Explain full
What do you m e a n by
adder in detail.
10
10 Solve the expression F(AB.C.D) m
using
(0.1.4,67.3.9
=
12)
K-map. Also draw the circuit
diagram
Write a short note on virtual memory and its significance.
Discuss hardwired and
What is Instruction Cycle ? Explain steps involved in microprogrammed control unit
instruction cycle 12 Discuss the concept of cache
memory Aiso discuss the
different mapping technique in cache
Discuss JK Flip Flop in detail. organisation
--- X ----
Differentiate between programmed 1/0 and Interrupt
initiated i/O.
What do you mean by micro-operations ? List its types.
SECTION - C
Note Anwer any three questions of the following: [3x10-30]
8 What is DMA ? Explain the technique behind DMA in
detail
Write short notes on any three
(0 Assembler
(i) Priority Interrupt
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4018-06/450 (6)
