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COMBINATIONAL LOGIC CIRCUITS

Dr. Naveen Saini

Assistant Professor,
Department of Information Technology
Indian Institute of Information Technology Allahabad
Uttar Pradesh, India

nsaini@iiita.ac.in https://sites.google.com/view/nsaini
 Introduction

Binary Binary
Digital Digital
. Gate Output
Input .
Signal . Signal

Types of Basic Logic Blocks

- Combinational Logic Block

Logic Blocks whose output logic value depends only on the input logic
values (clock independent)
E.g. -> Encoder, Decoder, Multiplexer, Demultiplexer, Half Adder, Full
Adder, Full Subtractor, etc.

- Sequential Logic Block

Those circuits which are dependent on clock cycles and depends on
present as well as past inputs to generate any output.
E.g. -> Flip-flops, Counters

Functions of Gates can be described by

- Truth Table
- Boolean Function
- Karnaugh Map
 Half Adder

• A combinational logic circuit that performs the arithmetic

addition of two bits A (augend) and B (addend).
• Associated with two outputs carry (C) and sum (S).

c = xy s = xy’ + x’y
=x  y
x y c s
0 0 0 0 y y
0 1 0 1 x x
0 0 0 1
1 0 0 1 1 0
1 1 1 0 0 1

x
y C

s
 Combinational Logic Circuits

Full Adder
• A combinational logic circuit that performs the arithmetic addition of three input bits and
give two output bits.
• Two of the input bits, x and y, , represents the two significant bits to be added. The third
input bit ‘z’ represents the carry from the previous lower significant position.
• Arithmetic sum ranges in the value 0 to 3, and binary of 2 and 3 needs 2 digits
• two outputs are denoted as carry (C) and sum (S).
x y cn-1 cn s
0 0 0 0 0 y y
0 0 1 0 1
0 0 0 1
0 1 0 0 1
0 1 1 1 0 0 1 c 1 0 c
n-1 n-1
1 0 0 0 1 x 1 1 x 0 1
1 0 1 1 0 0 1 1 0
1 1 0 1 0 cn s
1 1 1 1 1

x
y S cn = xy + xcn-1+ ycn-1
cn-1 = xy + (x  y)cn-1
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
cn
= x  y  cn-1 = (x  y)  cn-1
 Half Subtractor

• building block for subtracting two binary numbers. It has two in

puts and two outputs.
• This circuit is used to subtract two single bit binary numbers
A and B. The 'diff' and 'borrow' are two output states of the
half subtractor.

The SOP form of

the Diff and Borrow is as follows:
Diff=A'B+AB‘
Borrow = A'B
 Half Subtractor

The SOP form of the Diff and Borrow is as follows:

• Diff=A'B+AB‘
• Borrow = A'B
 Full Subtractor

• A full subtractor is a combinational circuit that performs subtraction of two bits,

one is minuend and other is subtrahend, taking into account borrow of the previous
adjacent lower minuend bit.
• This circuit has three inputs and two outputs.
• The three inputs A, B and Bin, denote the minuend, subtrahend, and previous
borrow, respectively. The two outputs, D and Bout represent the difference and out
put borrow, respectively.
 Full Subtractor

Bout= A’Bin + A’B + BBin

D = (A XOR B) XOR Bin

Logic Circuit for Full Subtractor

 Full Subtractor

D = (A XOR B) XOR Bin Bout= A’Bin + A’B + BBin

Logic Circuit for Full Subtractor using Half Subtractors

 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Other Combinational Circuits

Multiplexer
De-muliplexer
Encoder
Decoder
etc.
 Combinational Logic Circuits

MULTIPLEXER
• Receive binary information from one of the 2n input lines Function table of
and directs it to a single output line.
4-to-1 Multiplexer
• The selection of particular data line depends upon the
“n” selection inputs. Select Output
S1 S0 Y
• Let S1 S0 =10 => AND gate associated with input I2 has
two inputs as 1. For other AND gates, at least one input will 0 0 I0
be 0 with make their output as 0. Thus finally, the output of 0 1 I1
OR gate will be I2 1 0 I2
1 1 I3

I0

I1
Input data
lines Y
I2

I3

Selection S0
inputs S1
 Combinational Logic Circuits

DE-MULTIPLEXER
• a combinational circuit that has only 1 input line and 2N output lines. On the other h
and, the multiplexer is a single-input and multi-output combinational circuit.
• De-multiplexer is also treated as De-mux.
• 1×2 De-multiplexer:
– only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and single input, i.e., A
– On the basis of the selection value, the input will be connected to one of the o
utputs.
 Combinational Logic Circuits

DE-MULTIPLEXER
• 1×4 De-multiplexer:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
 Combinational Logic Circuits

DE-MULTIPLEXER
• 1×8 De-multiplexer:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A
 DE-MULTIPLEXER EXPANSION

Example: 1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

• To implement the 1×8 de-multiplexer, we need two 1×4 de-multiplexer
and one 1×2 de-multiplexer. The 1×4 multiplexer has 2 selection lines, 4
outputs, and 1 input. The 1×2 de-multiplexer has only 1 selection line.
• The 1×2 de-multiplexer produces two outputs. So, in order to get the final
output, we have to pass the outputs of 1×2 de-multiplexer as an input of
both the 1×4 de-multiplexer.
 Combinational Logic Circuits

DECODER
Decoder:
• Capable of representing n bit binary code to maximum 2n bit code
• n-to-m line decoder (or nxm decoder) and m <=2n (or fewer)
• Application: binary to octal conversion don’t care (0/1)
 Combinational Logic Circuits

DECODER

NAND gate Decoder

Decoders are constructed using NAND gate

2-to-4 line decoder enable input constructed with NAND gate shown below
Decoder will be enable with E=0

D0
E A1 A0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1 A0 D1
0 1 0 1 1 0 1
0 1 1 1 1 1 0 D2
1 d d 1 1 1 1
A1 D3
E
 Decoder Extension
• Some occasion when larger size decoder needed but only smaller sizes are available.
• Can we combine two or decoders with enable input??  Yes
• For example, for 6-to-64 line decoder, it is possible to construct using 4-to-16 line
decoders. In these cases, enable input is a variant feature to connect two or more
decoders.
• let us implement 3 to 8 decoder using 2 to 4 decoders

• Here, m2 and m1 are the number of outputs of higher and lower order decoder.

• The parallel inputs A1 & A0 are applied to each 2

to 4 decoder. The complement of input A2 is
connected to Enable, E of lower 2 to 4 decoder
in order to get the outputs, Y3 to Y0. These are
the lower four min terms. The input, A2 is
directly connected to Enable, E of upper 2 to 4
decoder in order to get the outputs, Y7 to Y4.
These are the higher four min terms.
 Decoder Extension
• let us implement 4 to 16 decoder using 3 to 8 decoders.
 Combinational Logic Circuits

ENCODER

Octal-to-Binary Encoder
• Capable to perform the inverse operation of a decoder.
• Consider the case of octal to binary conversion. It has eight inputs one for
every octal digit and three outputs that generate corresponding binary number

A0 =1 if the input
octal digit is 1 or 3
or 5 or 7
A0=

A1=

A2=
Email: nsaini@iiita.ac.in