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Cad 1

The document outlines the design and implementation of a 4-bit binary adder for unsigned integers using full-adders. It includes the truth table for a full-adder, mathematical expressions for sum and carry, and a C program to display the truth table. The results from both software simulation and programming confirm the correctness of the adder's logic for all input combinations.

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0% found this document useful (0 votes)
14 views5 pages

Cad 1

The document outlines the design and implementation of a 4-bit binary adder for unsigned integers using full-adders. It includes the truth table for a full-adder, mathematical expressions for sum and carry, and a C program to display the truth table. The results from both software simulation and programming confirm the correctness of the adder's logic for all input combinations.

Uploaded by

krishalasth34
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1

ADDITION OF TWO UNSIGNED INTEGER BINARY NUMBER


OBJECTIVE
To design n-bit (4-bit) adder for unsigned integer binary numbers.
THEORY
A full-adder is a combinational circuit that forms the arithmetic sum of the three inputs bit. It
consists of three inputs and two outputs. Two of the input a and b (say) represent, the bit c (say)
represents the carry from the previous lower significant bit position. The S (say) represents the
value of the least significant bit of the sum while C (say) gives the output carry. The truth table
for full-adder is given below which shows the value of the carry out and sum under difference
combinational values of the input bits. It is clear that when all input bits are 0, the output (S) is 0.
The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to
1. The C output has a carry 1 if two or three inputs are equal to 1.
Table 2.1: Truth table for full
adder
Inputs Outputs
a b c C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
Figure 2.1: Logical diagram of full adder
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Figure 2.2: Block diagram of
full adder
Mathematical expression for the full adder is:
S = (a + b + c) %2
C = (a + b + c)/2
The logical expression for the full adder is:
S=aʘbʘc
C = a b + (a ʘ b) c

790341 Shreya maharjan


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n-bit binary adder is constructed with n full-adder connected in cascade with the output carry
from one-full-adder connect to the input carry of the next full-adder. The figure below shows the
circuit for 4-bit binary adder.

Figure 2.3: 4-bit binary adder


To implement the add operation in software, we used the variables that holds the data and
mathematical expressions that perform the arithmetic addition.
1. Binary Adder:
#include<stdio.h>
int main()
{int i,j,k,S,C;
printf("Binary Full Adder\n");
printf("A | B | C | C | S\n");
printf("--------------------\n");
for (i=0;i<=1;i++)
{for (j=0;j<=1;j++)
{for (k=0;k<=1;k++)
{S=(i+j+k)%2;
C=(i+j+k)/2;
printf("%d | %d | %d | %d | %d\n",i,j,k,C,S);}}}}

Figure 2.4: Output for binary full adder

790341 Shreya maharjan


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DISCUSSION
In the above program, C is used for displaying the truth table of binary adder. The program
shows the output for addition of 3-bit binary number i.e., sum(S) and carry out(C) for all possible
combinations of the 3-bit binary inputs. The sum is calculated using S = (a + b + c) %2 and carry
out is calculated using C = (a + b + c)/2.
2. 4-bit Binary Full Adder

Figure 2.5: Logical diagram of 4-bit binary adder

790341 Shreya maharjan


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790341 Shreya maharjan


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DISCUSSION
The above figure is the logical diagram of a 4-bit binary adder made in Proteus simulator. The
simulator can be used to design circuits, and simulating the circuits which helps in verifying the
nature of the circuits. The above circuit works as a 4-bit binary adder and the truth table for the
binary adder is verified through the software.
CONCLUSION
In this lab, we simulated binary adder using Proteus simulating software and also implemented it
using C program to verify the truth table. The 4-bit binary adder was successfully designed and
implemented using both software and simulation tools. The results obtained verified the
correctness of the logic for all possible input combinations, demonstrating the effective operation
of the full adder circuit.

790341 Shreya maharjan

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