; i Digital Signal Processing 10-2 Eo Introduction to Progra introduce DSP processor architecture and their features, fy mented various DSP algorithms such 5 f C. There are few things common to all Dsp /* mmable DSPs ie é In this chapter we will briefly In the previous chapters we have imple convolution, FFT, filtering, correlation ete in algorithms such as, i) Processing on arrays is involved. rations are multiply and accumulate. ii) Majority of ope’ iii) Linear and circular shifting of arrays is required. These operations require large time when they are implemented on general purpose processors. This is because the hardware of general purpose processors is not optimized to perform such operations fast. Hence general purpose processors are not suitable for DSP operations. Particularly, real time DSP operations are very difficult on general ” purpose processors. Hence DSP processors having architecture suitable for DSP # operations are developed. [EDEEE Desirable Features of DSP Processors Now let us see what features DSP processors should have so that DSP operations will aM be performed fast. i) DSP processors should have multiple registers so that from register to register is fast. re multiple operands simultaneous! data (ie. arrays) exchange % ii) DSP operations requi ly. Hence DSP processor should have multiple operand fetch capacity. DSP processors should have circular buffers to support circular shift operations. The DSP processor should be able to perform multiply and accumulate operations iii) iv) very fast. ¥) DSP processors should have multiple pointers to support multiple operands jumps and shifts. \ ‘Since DSP processors can be used with general processors, ‘multi processing ability. vil) To support DSP operations fast, the DSP processors should have on chip memo? viii) For real time applications interrupts and timers are required. Hence? processors should have powerful interrupt structure and timers. ‘The architectures of DSP processors are designed to have these featuret, The sors from Analog Devices, Texas Instruments, Motorola etc are comm ee Scanned with CamScanner vi) they should hav? & proces: only usedProcessing 10-3 pita 902 Introduction to DSP Processors Multiplier and Accumulator (MAC) Unit 4 Most of the operations in DSP involve array multiplication. The operations such as convolution, correlation require multiply and accumulate oe In real time applications, the array multiplication and accumulation must be completed before next sample of input comes. This requires very fast implementation of multiplication and accumulation, «The dedicated hardware unit i called MAC is used. It is called multiplier-accumulator (MAC). It is one of the computational unit in processor. The complete MAC operation is executed in one clock cycle. In Texas Instruments DSP processor 320C5X, the output of multiplier is stored into the product register. This product register contents are added to accumulator register ACC in central ALU. The DSP processors have a special instruction called MACD. This means multiply accumulate with data shift. Modified Bus Structures and Memory Access Schemes in DSPs MACD instruction performs multiply, accumulate with accesses are required : i) Fetch MACD instruction from program memory " ii) Fetch one of the operands from program memory " ii) Fetch second operand from data memory iv) Data memory write If this instruction is executed with conventional architecture (Von-Neumann architecture), then it requires four clock cycles. But Harvard and Modified Harvard architecture require less number of clock cycles. ) Von-Neumann Architecture : General Purpose processors normally have this type of architecture. The architecture "es same memory for program and data. The processors perform instruction fetch, decode and execute operations sequentially. In such architecture, the speed can be lacreased by pipelining. This type of architecture contains common interval address and a bus, ALU, accumulator, 1/O devices and common memory for program and data, ‘Ype of architecture is not suitable for DSP processors. i Harvard Architecture : harvard architecture has separate memories for program and data. There are also separate, address and data buses for program and data, Because of these | — TECHNICAL PUBLICATIONS™- An up thrust for knowledge Scanned with CamScannera oe, Introduction to DSP Preceag 7 ors Digital Signal Processing: mS os, the speed of executi and internal buses, the spee: Ton IN harvarg separate on chip memories architecture is high. ee —— Program For storing programs Memory <}] 9} /8 z]/ 2] /8 __— = Digital Signal Processor cc Li swi|e}|4 gel|la] 2 ae lle lis 23| || a Data For storing data Memory Fig. 10.1.1 Harvard architecture showing separate program and data memories * In the above figure observe that there is Program Memory Address (PMA) bus and Program Memory Data (PMD) bus separate for program memory. Similarly there is separate Data Memory Data (DMD) bus and Data Memory Address (DMA) bus for data memory. This is all on chip. The digital signal processor includes various registers, address generators, ALUs etc. * The PMD bus is used to get instructions from the program memory and DMD bus is used to exchange operands and results from data memory. * The instruction code from program memory and operands from data memory &@ be fetched simultaneon’ This parallel operation increases the speed. . x Pw » etch next instruction when current instruction is executed. That ® ie fetch, decode and execute Operations are done parallely. Modified Harvard Architecture : * Fig. 10,1.2 shows the b jag, ifi be is teed tne ine block diagram for modified Harvard architecture. One ccess program as well ag data memories, * The DMD bus can be used to t memory and vice-versa, of tt ransfer the data from program memory 0 apigital Signal Processing ital Signal Processing ® Introduction to DSP Processors « This modified Harvard architecture is used in several P-DSPs such as DSP processors from Texas Instruments and Analog Devices, eee [= Progam = =] Memory gl al l2 — 5] | alls <|{a]|8 &]| a} |e Digital Signal Processor aio} |S Fla] |é Data Memory Fig. 10.1.2 Modified Harvard architecture data memory shared by programs Multiple Access Memory The multiple access memory-allows more than one memory access in a single clock » The dual access RAM (DA-RAM) allows two memory access in a single clock cycle. The DARAM is connected to the DSP processor with two address and two data buses independently. This gives four memory accesses in a single clock period. The Harvard architecture allows multiple access memories to be interfaced to DSP processes. EEE] Multiported Memory * The multiported memory has the facility of interfacing multiple address address Data and data buses. Fig. 10.1.3 shows the Bus 1 Bus 1 block diagram of a dual ported Address Data ‘ Bus 2 Bus 2 memory. This memory has two addres: buses and two data buses separately interfaced Fig. 10.1.3 Dual port memory The dual ported memory can allows two memory accesses period. in a single clock With the help of dual port memory, the program and data can be stored in a single memory chip and they can be accessed simultaneously. TECHNICAL PUBLICATIONS”. An up tust or browedge bee “4 Scanned with CamScannerDigital Signal Processing Introduction to DSP Processor, * The motorola DSPs use single memory. This allows one prog! per clock cycle. « The multiported memories increased number ported progra ram memory access @ mm memory and dual ported data ind two data memory access of pins and larger chip area which makes it more expensive and large in size- EQRES Vii Architecture and Multiple ALUs Some of the DSP processors use very long instruction — word (VLIW) architecture. Such architecture consists of multiple number of ALUs, MAC units, shifters etc. Fig. 10.1.4 shows the block diagram of VLIW architecture. * The above architecture consists of multiported register file. It is used for fetching the operands and storing the results. * The Read/Write cross bar provides parallel random access by functional units to the multiported register file. The functional units work Multiported register file Read/Write Crossbar Fig. 10.1.4 VLIW architecture concurrently with the load/store operation of data between a RAM and the register file. The program control unit provides the algorithm that executes independent Parallel operations. The performance of VLIW architecture depends upon degree of parallelism. * Normally 8 functional units are preferred. This ni cost of the multiported register file and crossbar Pipelining Any instruction cycle can be split i) Fetch : In this phase, an instruct ii) Decode : In this phase, data memory. umber is limited by hardware witch, in following micro instructions : tion is fetched from the memory. io an instruction is decoded, iti) Read : An operand required for the instruct ion is fetched from the iv) Execute : The operation is executed and re: sults are stored at appropriate place TECHNICAL PUBLICATION, "up thrust for knowledge Scanned with CamScanner oysignal Processing igi! 10-7 Introduction to DSP Py f the above opera *rocessors Bach of ions can be Fig: 40.1.5 shows how the instruction js e “parately executed j 'd in different functi it pa ¢ functional units, a a5 ‘cuted without Pipeline. ” aa etch Decode 1 11 Read Execute § 12 12 Fig. 10.1.5 Instruction execution without pi In the above figure observe that when instruction I 1 is in fetch phase, other units such as decode, read and execute are idle. Similarly when I 1 is in decode phase, other three units are idle. This means each functional unit is busy only for 25% of the total time. « Fig. 10.1.6 shows the instruction execution with pipeline. Here observe that when I 1 is in decode phase, next instruction I 2 is fetched. Similarly when I? goes to decode phase, next instruction I 3 is fetched. Thus observe that all the functional units are executing four successive instructions at any time. On comparing Fig. 10.1.5 and Fig. 10.1.6 we observe that five instructions are executed in the same time if pipelining is used. Value of T Fetch |. Decode Read Execute A 11 2 12 M1 ' 3 13 12 u Et 4 14 13 12 WW a 5 VIS 4 13 12 6 7 15 14 13 7 15 14 8 cae Fig, 10.1.6 Instruction ‘execution with pipeline TECHNICAL PUBLICATIONS™- An up int for Knowledge Scanned with CamScanneraj => i ON Introduction to DSP p, 100 8sorq Digital Signal Proce: EEA Barrel Shifter The barrel shiflet operations. The provides s SF ord in single 1 usually © Principle ple shifts are execu multiple shifts ar a perc) on instruction cycle. n-bits shifter mbit © Block diagram and Fig. 10.17) shows the outputs of a barrel shifter UR K_ Number oft © The barrel shifter has multiple inputs en Position for shit and multiple outputs. Hence all the coal bits of a register are shifted in single a instruction cycle. * The control inputs determine direction of shift and number of bits to be shifted. | If there are n-bits in the register, then control input requires K = log 7 control input lines to determine the shift. The line L / R indicates left (L) or right (R) shift When the bits are shifted to left, the new bit positions which are vacant are filled with zeros. In case of right shift, the new bit position are replicated with next significant bit to maintain sign of the shifted result. * In practical DSPs the shifting operation is combined with data transfer. Both of these operations are executed in a single clock cycle. > Write short notes on the following with respect to digital signal a) Barrel shifter b) MAC. . aan [II Special Addressing Modes : Conventional ‘microprocessors have addressing modes euch* as. direct; isdn immediate etc. The DSP processors have additi : € additional addressi Le execution is fast. These addressing modes are discussed next maces tect ssed next, the Fig. 10.1.7 Barrel shifter [OEE short immediate Addressing The operand Specified using a short constant, Thi of a single word instruction, In TMSI2005¢ sane aren eats s be specified as one of the ope A series of DSP processors 8-bit operand © Word instructions such as add, subl* Scanned with CamScanneral signal Processing var Introduction to DSP Processors Short Direct Addressing yer order addre stand i Ie OX DSP proce: ess of the operand is specified in the single word instruction. In saan Higher 9 bits of ape bits of the address are specified as the part of the 7 address are stored in the data page pointer. Each such instruction. Hig consists of 128 words. data Page pee Memory-Mapped Addressing The CPU and I/O registors are accessed as mem i is ; i : ory location. These registers are mapped in the starting page or final page of the memot In TM! corresponds to CPU and 1/0 registers. ry space. In TMS320C5X, page 0 [NE Indirect Addressing ‘The addresses of operands are stored in the indirect address registers. In ‘TMS320CXX vcasors such registers are called auxiliary registers (ARs). Any of these ARs can be fetched by these registers are being executed. The ARs are ‘d automatically by the value specified in offset register. For ter is called INDEX register. pro updated when operands incremented or decremente TMS320CXX processors the offset regis! Bit Reversed Addressing Mode For the computation of FFT, the input data is is no need to actually reshuffle the data in bit reversed sequence. The serially arranged data in the memory or buffer can be given to the processor in bit reversed mode with the help of bit reversed addressing mode. With this addressing mode an address is incremented /decremented by the number represented in bit reversed form. required in bit reversed format. There Circular Addressing With this mode, the data stored in the memory : t ay ion. This increases the utility of the memory. ‘The memory is organized as a circular ding addresses of the circular buffer are continuously t. The beginning and. en can itored. If the address exceeds ending address of the memory, then it is set at the inning address of the memory. This is ‘nothing but circular addressing. ERED on.chip Peripherals The DSPs hav i i ve many peripheral Peripherals reduce the DSP system aroun Pd ELEEH on-chip Timer The timer generate single pulse or periodic tr ee or frequency of the pulse train can be ProBt oes et oes ie Scanned with CamScanner can be read/written in circular s on the chip to support its operation. These on-chip ‘DSP. period of the single ain of pulses. The mer can be used ‘ammed. The on-chip ti| Peta . Introduction to Ds Digital Signal Processing 10-10 SP i) Generation of periodic interrupts to P-DSPs. Generation of sampling clocks for A/D converters. iii) Timing signals EEE Serial Port The serial ports have input and output buffers. These ports also have serial to paras and parallel to serial converters. The serial ports can operate in asynchronous Mode op in synchronous mode. The serial port allows following operations : i) Communication between P-DSP and external peripherals such as A/D converter, D/A converter or RS 232 device. ii) Parallel writes from P-DSP and serial transmission. Receives serially from extemg) peripherals and gives parallel data to P-DSPs. iii) Generate interupts when serial port output buffer is empty or when input buffer is full. iv) Allows synchronous and asynchronous transmission. EXE] To Serial Port The TDM serial port allows the P-DSP and peripherals to communicate using tine division multiplexing. Fig, 10.3.1 (a) shows how eight peripherals can be interfaced tp P-DSP. ‘TMS 320 CSX P-DSP (a) + ne TDM frame — (b) Fig. 10.3.1 a) Commutation through TDM serial port b) One TDM frame with eight slots TECHNICAL PUBLICATIONS”. An up thrust for ‘knowiedge Scanned with CamScannerpigitl Signal Processing 10-14 a Introduction to DSP Processors a), Q . he TDM setial port Uses follo wing four lines for serial Used for data transmissi used for data reception by yi, TOM channel by M Y authorized device TOLK: Bit clock used by transmitin, TERM: Frame syne signal is transmi : Address of tJ i i is TADD : ioe ee the serial device that is authorized to oul The TERM signal indicates the TDM channel to eight-devices as s BEES Parallel Port YY authorized device, and 8 and receiving devices, itted on this line put data in a particular begining of a TDM frame. The TDM frame allots the hown in Fig. 10.3.1. (), t data transmission com, dditccat ss10" compared to serial port. The parallel as additional lines for strobing and handshaking Some times data bus itself is used fo allel port is the = t parallel port. The parallel port is then addressed using I/O instructions. The parallel port is asigned a fred address space. 2 HIE! Bit 1/0 Ports These I/O ports have single bit lines. These bit I/O ports can be individually ated. These I/O ports do not have handshaking signals. Bit I/O ports are used for, i) Control purposes as well as data transfer. ii) Conditional branching or calls. EES Host Port The host port is a parallel port that is 8 or 16-bits wide. All P-DSPs normally have _ host port. It is used for following purposes : : i) P-DSPs communitate with host processors such as microprocessor or PC through host port. ii) The Host processor generates interrupts to P-DSP and load data on reset through host port. . . iti) Host port is also used for data communication with host processor. EEE comm Ports ts as well as Analog . ts, P-DSPs from Texas Instrument Devices bolt have, core hich vary from 6 to a] Normally each comm pert have 8 bi munication wee! | Ww : Sretng multiprocessor pe The 23 bit wide data can be split into four 8 bit Words, Then the data is exchanged amog P-DSPs over four different comm ports. FER wp and D/A Converter . for voice The on-chip A/D and D/A converters are useful for P-DSPs which are used for PPlications stich as mobiles and answering machines. TECHNICAL PUBLICATIONS”. An up thrust frArowledge Scanned with CamScanner10-12 Introduction 0 DSP Processors Digital Signal Processing - ae > Write short notes : | i) Dedicated MAC unit ii) VLIW architecture Ss i P processors. > Explain various addressing modes of DS! ? ture is used > What are the different types of architectures ? What type of architecture is used for Dgp ili) Pipelining Processors ? > What are the desirable features of DSP processors ? [EGET tms320c5x DsP Processors The TMS320Cxx series of DSP processors is manufactured by Texas Instruments, The TMS320C5x is one of the commonly used family of DSP processors. Let us study the architecture and features of this family of processors briefly in this section. SWEET Features of TMS320C5x Processors This family of processors have following features : 1) Powerful 16 bit CPU. 2) 20, 25, 35 and 50 ns single cycle instruction execution time for SV operation. 25, 49 and 50 ns single cycle instruction execution time for 3V operation, 3) 16 x 16 bit Multiply / Add operations can be performed in single cycle. 4) 224K x 16 bit maximum addressable external memory space. This space is divided into 64K program, 64K data, 64K I/O and 32K global memories, 5) Upto 32K x 16 bit single access on-chip program ROM. 6) Upto 9K x 16-bit single access on-chip program/data RAM (SARAM) 7) 1K x 16-bit dual access on chip program/data RAM (DARAM). 8) Full duplex synchronous serial port for coder/decoder interface. 9) Time Division Multiplexed (TDM) serial port. 10) It has hardware/software wait state generation capability. 11) On chip timer for control operations, 12) Repeat instructions for efficient use 13) It has buffered serial port, of program space. 14) It has host interface port, 15) It has multiple Phase Locked Loop (PLL) x5 and x9 16) Block move facility for data/pro ! gram mana, 12) On-chip scan based emulation logie, aan Clocking operations ive, x 1, x 2, x 3,%4 18) Boundary scan. DRA mrss with CamScannerIntroduction to OSP Processors a vhs family is manufactured into high performance static CMOS technology. low power dissipation and power down modes. * gandard Test Access Port (TAG). processors are available in five packaging options 22) The Pe ck. ' . she TMSG20C5X family of processors is manufactured with static CMOS technology. vanced harvard architecture. These processors can execute upto 50 million s per seconds (MIPS). Architecture of TMS320C5x Processors Fig. 104.1 shows the functional block diagram or architecture of TMS320C5x family 5 processors. Fig. 10.4.2 shows the simplified architecture. ‘The meanings of various symbols used in the block diagram of Fig, 10.4.1 are given jn Table 104.1. of we DESCRIPTION SyNBOT DESCRIPTION Se a erg uk a PL rezraltr ber THR [erupt Aecaruator igh NOX [rect adreseng:ndoregaer rd [rates m= Faia ie wk Yes ieceat aac Falan-regigeranate unk wox | water TraanyTeger poor bute PAER | Biocwopeotecarose oa omer Tsay TeTdar compare relat PAGR | Bloorpoat-aaios eat rege he —[ hoxary register poieer Program cour Ree | Raross receive regiter ABD [PFC Prefetch courer soART_| nonary rites eral ogc unk ARR ‘Address-transmit register (ABU) ‘Processor-mode-status register Bk | Receive butler-ize regier (ABU) Timer perodregier BK Transmit buffer-size register (ABU) Product register BWAR | lock move addres regider RPTC | Repost courer epee BAG | Stak repeat courter region ARAM | Singie-acoss RAM ear Buffered serial port Tet shitter ie Carry bt Right shitter jceeRt | Circular buffer 1 end address ‘SPC “Serial port intertace-control register Brats registers TCSR | TOM channel select register Greular butler 2 dant adaress: TCR’ Timer. control registor Dualaccoss RAM TOM Time-divsion-mutiploxed serial par Dynamic bk manipulation register || TOXR | TOM data transm& regstor Data memory page pointer Timer count rogiter ‘Seriapor data TOM recovedhaddross register “TDM data receive register “Temporary register for mutiplcation “Temporary register for dynamic afk count “Temporary register used as bit pointer in dyramiesbe test "TOM receive-Aransmt-address register “TOM serial port-control register {SEER2 | Circular butler 2end address Circular butler 1 dant address, sory allocation register Host pot interface register (high bytes) HPladdress register (ow bytes) HP corirol register (high byte HP l-contol register (low bytes) Table 10.4.1 Symbols used in functional block diagram a1 orien naTiONS”. An up thrust for knowiedge Scanned with CamScannerTam Bam om 6 [aro a Em Loe ST t erat c TA 1s vcr are ~ en Te oe Treo TREC, ae "aRONTE) ae Z won| Ce ay | Ae “ 8 . on oo REGO “ARTIS! sss LT = CesRIIE a “CHERICIS) = an || f= 2 geo a 2 2 Te be "i Saoer me eS om = > 2 veot fee =y oh ah SY pp ee E Al } i Fig. 10.4.1 Functional block dis “9fam oF architecture of TMS320C5x__—~ TECHNICAL PUBLICATIONS”. Anup knowiedge IS ist for Scanned with CamScannerIntroduction to DSP Processors Arouveny 1601 uonesauab ss@xpp¥ ypuyS BIEMPICH vod eves peseune pod eves 10-15 cs WoL z vod eves: sioysi601 poddew “ROWE, Sasa yonucoysmers yequnco wes601d FByeHIS weIBOI i Fusscoordinnin — Tonuoe Kowen | vod jeues stesoudued Fig. 10.4.2 Simplified functional block diagram ‘of TMS320C5x "An uo thrust for knowledge TECHNICAL PUBLICATIONS’ Scanned with CamScanner= 7 Di Pr 0-16 Introduction to Dsp at digital Signal Processing 1 Proce: i EQEESY Bus structure Observe that there are separate program and data buses. ate a address bus (PAB) addresses to the program memory. The data read address bus A ; ) addresses ig the program as well as data memory. The program bus (PB) carries the instructions from, program memory. These instructions are given further to CPU for oxetution, The daty read bus (DB) carries the data required for execution. It gets the data from the 1, 0 ports, CPU or data memory. Because of the four types of buses for Program and data, } high degree of parallelism is obtained. Therefore multiple operations are performed in | single instruction cycle. | Central Processing Unit (CPU) The CPU consists of Central Arithmetic Logic Unit (CALU) * Parallel Logic Unit (PLU) * Auxiliary Register Arithmetic Unit (ARAU) * Memory mapped registers + Program controller Central Arithmetic Logic Unit (CALU) The CALU is used to perform 2's complement arithmetic. The CALU consists of * 32-bit arithmetic logic unit (ALU) * 32-bit accumulator (ACC) * Scaling shifters * 16 x 16 parallel multiplier * 32-bit accumulator buffer (ACCB) One of the operands for ALU comes from CALU and its results are stored in ACC. Th by ACC for temporary storage. 32-bit ALU/accumulator The 32-bit ALU and accumulator performs arithmetic and logical functions. Alm" all these functions are executed in si . ingle cycle. ALU ‘a fc ‘poolea* operations. The ALU takes its operands from ae Tele ns Scaling shifter . ACC. The operations are performed * accumulator buffer (ACCB) register is used shifter and muitiplier. The scaling shifter has a 16-bit in connected to the ALU. The scaling input data. The other shifters it Put connected to the data bus and 32-bit oulP! hifler produces a left shift of 0 to 16 bits perform cays p numerical scaling, ‘bit extraction, ext precision arithmetic and overflow prevention aan Scanned with CamScannerDigital Signal Processing 10-17 to DSP Processors 16x 16 bit parallel m This is 16 x 16 bit p, 32-bit Product in a sing 2s complement num ultiplier ‘ardware multiplier is cap. le machine cycle. The ber and the able of multiplying si {wo number being multiplied are treated as result is also a 32-bit 2's complement number. The din product register (PREG), igned or unsigned cight auxiliary regi : i femporary data storage, ‘Thy 8 *iliary registers. These registers are used for i Suxiliary register file (ARO-AR7) is connected to the hii ter ari ic uni uxiliary Tegister arithmetic unit (ARAU). The contents of the auxiliary registers can be tored in data memory or used as inputs to central arithmetic logic unit (CALU). The RAU helps to speed up the operation of CALU. PPA Parallel Logic unit (PLuy EEE Summary of Registers Index Register (INDX) The index register (INDX) is 16-bit tegister. The ARAU add or subtract the value ored in INDX with contents of auxiliary registers (AR) to get new address. This mode called indirect addressing. Bit reversal addressing is also done with the help of INDX. Auxiliary Registers (ARO - AR7) The Auxiliary Registers (AR) are basically a set of eight registers. Each of them is a bit register. The ARs are used to provide 16-bit address for indirect addressing. In Mitition to this, ARs can be used as general purpose registers or counters by CALU, ARAU or PLU, Auxiliary Register Compare Register (ARCR) tt arison. The ARCR is a 16-bit register. It is used for address boundary comp: tT varison is instruction compares the ARCR to selected AR. The result of comp **1in test / control flag (TC) bit of status register 1 (ST1). Block Move Address Register (BMAR) jn block move and multiply / BMAR is a 16-bit register. The address required in : is used as an indirect iA operations is stored in BMAR. This 16-bit addres 4 operand, ee Scanned with CamScanner