LD7412

12/18/2009

2A Step-Down Switching Regulator

REV. 00

General Description Features

The LD7412 is a high efficiency asynchronous buck z High Efficiency: Up to 90%
converter with a constant-frequency, and voltage-mode z Wide Operating Input Voltage Range: 4.3V to 18V

architecture. It achieves 2A continuous output current over z Adjustable Output Voltage Range: 0.8V to Vin.

a wide input voltage ranging from 4.3V to 18V. The IC z Duty Ratio: 0% to 100% PWM control
z Oscillation Frequency: 400kHz typ.
provides a feed forward voltage mode operation to
z Cycle-by-Cycle Current Limiting
achieve the fast line-transient response. The LD7412 also
z Thermal Shutdown
provides soft-start function to prevent overshoot during
z Stable with Low ESR Output Ceramic Capacitors
startup.
z Built-in internal SW P-channel MOS
Fault condition protections include cycle-by-cycle current
z Internal Soft-start function
limiting and hiccup overload protection, which can reduce
z Under Voltage Lockout
the operation frequency from 400kHz to 50kHz.
The LD7412 minimizes the number of external Applications
components to complete a 2A step-down DC-DC z Distributed Power Systems

converter solution. z DVD-Video Player

z Per-Regulator for Linear Regulator
z Telecom Equipment
z Microprocessor core supply
z LCD monitor and TV

Typical Application Circuit

VOUT= VFB x (1+R1/R2)

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 LD7412
Pin Configuration
SOP-8 (TOP VIEW)

GND

GND
SW

SW
8 7 6 5

YY: Year code

TOP MARK WW: Week code
YYWWPP PP: Production code

1 2 3 4
EN
FB

VIN
IOSET

Ordering Information
Part number Package Top Mark Shipping

LD7412 GS SOP-8 LD7412GS 2500 /tape & reel

Note: The LD7412 is Green packaged.

Pin Descriptions
PIN NAME FUNCTION
Feedback Input. FB senses the output voltage for voltage regulation.
1 FB
Output voltage is regulated to keep the voltage of FB pin 0.8V typically.
Enable Input, an input for digital signal. Keeping the voltage of EN pin
2 EN higher than 2V enables the regulator, and keeping the voltage lower than
0.8V disables it. Do not leave EN pin floating.

3 IOSET Output Current Setting Pin. Add a resistor to set maximum output current.

Power Input. VIN supplies the power to the IC. Bypass VIN to GND
4 VIN with an appropriately-large capacitor to eliminate noise introduced from
this input into the IC.
Power Switching Output. SW is the switching node that alternatively
5,6 SW supplies power to the output. Connect the output LC filter from SW to the
output load.
Ground. These pins should be soldered to a large pad on a PCB and
7,8 GND
connected to GND in consideration of heat dissipation.

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 LD7412
Block Diagram
SW

Oscillation Reference Voltage

Source with
Circuit Soft Start
VIN
PWM-Switched +
Control Circuit
- FB
Thermal
Shutdown
90uA
VEN GND

EN IOSET

Absolute Maximum Ratings

Input Supply Voltage VIN -0.3V to 20V
EN Pin Voltage, VEN -0.3V to VIN
FB Voltage, VFB -0.3V to VIN
SW Pin Voltage, VSW -0.3V to VIN
Power dissipation, PD, @Ta=85°C 400mW
Package Thermal Resistance (θJA) 160°C/W
Junction Temperature 125°C
Storage Temperature Range -40°C to 150°C
Lead temperature (Soldering, 10sec) 260°C
ESD Level (Human Body Model) 2KV
ESD Level (Machine Model) 200V

Recommended Operating Conditions

Input Supply Voltage, VIN 4.3V to 18V
Enable Voltage, VEN 0V to 18V
Operating Ambient Temperature Range -20°C to 85°C
Output Current 0A to 2A

Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

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 LD7412
Electrical Characteristics
(VIN=12V,TA=25°C, unless otherwise noted.)

Parameter Symbol Conditions Min. Typ. Max. Unit

Input

Input Voltage VIN 4.3 18 V

Shutdown Current ISHDN VEN=0V 1 10 μA

Under Voltage Lockout Threshold

VUN 4.1 4.2 4.3 V
Rising
Under Voltage Lockout Threshold
VUN_HYS 200 mV
Rising Hysteresis

Reference Voltage

Feedback Reference Voltage VFB 4.3V ≤ VIN ≤ 18V 0.784 0.8 0.816 V

Line Regulation ∆VOUT/VIN VIN=5V to 18V 1 2 %

Load Regulation ∆VOUT/IOUT IOUT=0.1A to 2A 0.2 0.5 %

Power MOSFET

VIN=5V,VFB=0V 80 110 mΩ
High-Side Switch-on Resistance RDS(ON)1
VIN=12V,VFB=0V 70 100 mΩ

Switch Current ISW 2.5 A

Switch Leakage ISW_L VEN=0V,VSW=0V 1 10 μA

Oscillator

Oscillator Frequency fSW 350 400 450 kHz

Current limit or Short Circuit

fSW1 50 kHz
Oscillation Frequency

Enable

EN Input High Voltage VIH_EN 2 V

EN Input Low Voltage VIL_EN 0.8 V

EN pin for Resistance to ground RPULLUP=200kΩ 60 μA

Protection

IOSET Pin Bias Current IOSET 75 90 105 μA

Thermal Shutdown TSD 150 °C

Efficiency VIN=12V, VOUT=5V, IOUT=2A 92 %

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 LD7412
Typical Performance Characteristics
100 3.35
VOUT =8V

90
5V
3.3V 3.34

Output Voltage (V)

80
VIN=12V
Efficiency (%)

1.8V
3.33
70

60 1.2V
3.32

50
VIN =12V
3.31
40
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.1 0.2 0.6 1 1.4 1.8 2.2 2.6 3

Load Current (mA) Output Current (mA)

Fig. 1 Efficiency vs. Load current Fig. 2 Load Regulation

3.35 0.83

3.34

IOUT=200mA
Feedback Voltage (V)

IOUT=2A
Output Voltage (V)

0.82
3.33

IOUT =2A
3.32
0.81 IO UT= 200mA

3.31

3.30 0.80
5 8 11 14 17 20 5 8 11 14 17 20

Input Voltage (V) Input Voltage (V)

Fig. 3 Line Regulation Fig. 4 Feedback Voltage vs. Input voltage

400
420

IOUT=2A 410
390
Frequency (KHz)
Frequency (KHz)

400

380
IOUT= 200mA 390

380
370

370

360
360
5 8 11 14 17 20 -50 -30 -10 10 30 50 70 90 110 130

Input Voltage (V) Ambient Temperature (°C)

Fig. 5 Frequenc y vs. Input Voltage Fig. 6 Frequency vs. Ambient Temperature

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 LD7412

0.83 110

100
0.82
Feedback Voltage (V)

90

R DS(ON) (mΩ)
0.81 80

70
0.80
60

0.79 50
- 50 - 30 - 10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130

Ambient Tempertature (°C) Ambient Tempertatur e (°C)

Fig. 7 Feedback Voltage vs. Ambient Temperature Fig. 8 RDS(ON) vs. Ambient Temperature

SW SW

VOUT (AC) VOUT (AC)

IL IL

VIN=12V, VOUT =3.3V, IOUT =2A VIN=12V, VOU T=3.3V,IO UT=0.03A

Fig. 9 Output voltage ripple-CCM Fig. 10 Output voltage ripple-DCM

SW SW

VOUT (AC) VOUT (AC)

IL
IL

V IN=5V, VOUT=3.3V,IOUT=2A VIN=5V, VOUT=3.3V, IOUT=0.03A

Fig. 11 Output voltage ripple-CCM Fig. 12 Output voltage ripple-DCM

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 LD7412

V SW V SW

VIN VIN

V OUT V OUT

IIN IIN

V IN=5V, VOUT=3.3 V, IOUT=2A VIN=12V, VOUT=3.3V, IOUT=2A

Fig. 13 Start up from power supply Fig. 14 Start up from power supply

VSW
VSW

Enable Enable

V OUT V OUT

IIN IIN

VIN=12V, VOUT=3.3V, IOUT=2A V IN=5V, VOUT=3.3V, IOUT=2A

Fig. 15 Start up from Enable Fig. 16 Start up from Enable

V OUT(AC) V OUT(AC)

IOUT IOUT

VIN=5V,VOUT=3.3V,IOUT=0.2A to 2A VIN=12V, V OUT=3.3V, IOUT=0.2A to 2A

Fig. 17 Load Trans ient Fig. 18 Load Trans ient

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 LD7412
Application Information
LD7412 is a voltage-mode step-down converter. It is able Current Limit Protection
to accept an input voltage ranging from 4.3V to 18V, and The current limit threshold is set by an external resistor

to down convert to an output voltage that could be as low RIOSET connected from VIN supply to IOSET pin. An

as 0.8V and have output load current up to 2A. internal sink current IIOSET, typically 90μA, flows through
RIOSET and sets the voltage at IOSET pin. When, during a
The LD7412 uses voltage-mode control scheme to
charging period, the voltage drop across the high-side
regulate the output voltage and switches at a constant
switch is larger than that across the external resistor
frequency 400kHz to transfer power to the load cycle by
RIOSET, an over-current condition is triggered.
cycle.
The current limit threshold can be determined by the

Output Voltage Setting following equation:

The voltage divider allows the FB pin to sense the output

voltage as shown in Fig.1.
VOUT

R1
Fig. 2
FB

R2
IPEAK × RDS( ON) = IIOSET × RIOSET
( ΔI)
If the condition that IPEAK > IOUT(MAX ) + , OCP will
2
be activated.
GND
Where,
VIN − VOUT VOUT
ΔI = × ,
Fig. 1 Output Voltage Setting Fs × L VIN

The output voltage is set by an external voltage divider IPEAK is the output peak current; RDS(ON) the ON resistance

according to the following equation: of the high-side P-MOSFET switch; Fs the switching
R1 frequency 400kHz. Please note that the inductor value will
VOUT = VFB (1 + )
R2 affect the ripple current ∆I. The above equation is
Where VFB is regulated to approach 0.8V typically.
recommended for the input voltage between 4.3V and 18V.

Short Circuit Protection RIOSET values are recommended and summarized as

The LD7412 includes short circuit protection. When the follows:

VIN(V) VOUT(V) RIOSET(Ω)
output is shorted to ground, the protection circuit will be
4 1 6.8k
triggered, forcibly shifting the oscillation frequency down
5 3.3 5.6k
to around 50kHz. The oscillation frequency will increase 12 5 3.9k
once the output voltage or the feedback voltage rises 18 12 4.7k
above 0V.

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 LD7412
Delay Start-up to dampen the ringing. The following circuit introduces a
Depending on the application condition of input voltage, simple RC snubber:
the startup of the regulator and the power delivery to L
VOUT
output voltage can be delayed, as illustrated in Fig. 3. SW

LD7412 will be enabled soon after the capacitor voltage RSNUB

rises above the threshold voltage of EN pin, 2V in typical. GND
CSNUB

Fig. 4

Below are exemplified steps to select the component

values in the RC snubber.

Fig. 3 (1) Measure the voltage ringing frequency (fR) at SW pin.

(2) Connect an additional capacitor between the SW pin

For example, by setting VIN =12V, RDELAY= 100kΩ,
and GND pin to decrease the voltage ringing
CDELAY=0.1μF, the start-up delay time can be obtained as
frequency by half.
below formula:
T
− (3) The parasitic capacitance (CPAR) at the SW pin is 1/3
VC=Vin x (1- e τ )>VEN
the value. The parasitical inductance ( LPAR) at the
T>1.823ms
SW pin can be derived as:
Where: 1
LPAR = .
VC is capacitor voltage (2πfR )2 xCPAR
VEN=2V(Typ); EN Pin Threshold voltage
(4) CSNUB should be 2~4 times the value of CPAR but
T=Delay time
τ=(RDELAY//200k) x CDELAY small enough to suppress the power dissipation of
RSNUB. The power rating of RSNUB can be calculated
This feature is useful in situations where the input power
by following formula:
source is limited in its delivery current, and allows the 2
P_(snub)= CSNUB x VIN x fS.
input voltage to rise higher before the regulator starts
(5) Calculate the value of RSNUB by the following formula
operation.
and adjust the value to meet the expectative peak
voltage.
Snubber Circuit
RSNUB=2π × fR × LPAR
A simple RC snubber is useful for ringing suppression
during voltage switching. The high-frequency ringing Thermal Considerations
and voltage overshooting at SW pin occurs due to fast Thermal protection limits the total power dissipation in

transient switching and the resonance from the parasitic LD7412. As the junction temperature in LD7412 reaches

inductors and capacitors in the power circuit. It may approximately 150°C, the thermal sensor signals to turn

generate EMI, adversely affecting circuit performance. off the regulator. It will not resume until the IC’s junction

It’s preferred to reserve a snubber circuit in the PC board temperature drops to about 25°C.

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 LD7412
The maximum power dissipation depends on the thermal
VIN
resistance of IC package, PCB layout, the rate of IQ1 VIN

surrounding airflow and the temperature difference CIN

between the junction and the external ambience.

Maximum power dissipation can be calculated by Q1
following formula: L IL IOUT

PD(MAX) = (TJ(MAX) − TA ) / θJA SW

VOUT
Where TJ(MAX) is the maximum operation junction ESR
ICOUT
D1
temperature, TA the ambient temperature and θJA the COUT
junction-to-ambience thermal resistance.

Component Selection Fig. 5

T= 1/FOSC
1. Input Capacitor Selection
Refer to Fig5, During ON-time of the high-side
P-MOSFET (Q1), a small ceramic capacitor and a bulk VSW
DT
I
input capacitor for high frequency decoupling are IOUT

suggested to supply the surge current. Place them

between VIN and the anode of the Schottky diode (D1). IL

The bulk input capacitor should be determined in view of

IQ1 IOUT
the voltage rating and the RMS current rating. For reliable
operation, select the capacitor voltage of the bulk input
I
capacitor rating at least 1.25, or preferably 1.5, times
greater than the maximum input voltage. The RMS ICOUT

current (IRMS) of the bulk input capacitor is calculated as VOUT

the following equation.

IRMS = IOUT ⋅ D ⋅ (1 − D) ………(A) VOUT

where D is the ON-time duty cycle of the high-side Fig. 6

P-MOSFET. 2. Output Capacitor Selection

For a thorough whole design, if an aluminum electrolytic The function of the output capacitor COUT in Fig. 5 is to
or tantalum capacitor is used as the bulk input capacitor, store and maintain the output voltage. A Low ESR
connect a 0.1μF ceramic capacitor, and position it as (Equivalent Series Resistance) capacitor is preferred for
close as possible, to VIN pin of the regulator. Alternatively, reducing the output ripple voltage ( ΔVOUT ) and
if a ceramic capacitor is used, make sure its capacitance conduction loss. The output ripple voltage can be
is large enough to prevent the excessive input ripple calculated as below:
current. 1
ΔVOUT = ΔIL ⋅ (ESR COUT + )
8 ⋅ fS ⋅ COUT

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 LD7412
(1): When a low ESR ceramic capacitor is used as the shorten the life times due to the excessive internal
output capacitor, the output ripple voltage due to the ESR temperature. Choosing a smaller inductor causes higher
can be ignored because it is majorly caused by the ripple current which may result in overstress to the output
capacitance of the output capacitor. The tolerable value capacitor. The RMS ripple current flowing through the
of output ripple voltage must be first defined for choosing output capacitor and power dissipation can be calculated
a suitable output capacitor. using the following equation:
The minimum capacitance can be determined, basing on ΔIL
IRMS _ COUT = = 0.289 ΔIL
the switching frequency, the output ripple current, and the
12

tolerable output ripple voltage, according to the simplified

equation below: Layout consideration
ΔIL In a high power switching regulator, layout on PCB is
COUT(MIN) ≥
8 ⋅ fS ⋅ ΔVOUT essential to ensure proper operation of the regulator. In
Besides, some compensation components, such as a 1nF general, interconnecting impedance can be minimized
ceramic capacitor connected in parallel with the high side using short and wide printed circuit traces. Signal and
resistor of the output voltage divider, may be used to power grounds should be initially separated and finally
stabilize the control loop in some applications. combined using ground plane construction or single-point
grounding. Fig.7 illustrates the layout with bold lines
(2): While the ESR of an aluminum electrolytic or tantalum
indicating high current paths. Components along the bold
output capacitor is an important parameter to determine
lines should be placed close to one another. Below is a
the tolerable output ripple voltage, the manufactures
checklist for your layout.
usually do not specify ESR in the specifications.
1. The power charge path consisting of VIN trace, SW
Assuming the contribution to the tolerable output ripple
trace, external inductor and GND trace should be as
voltage from the capacitance of the output capacitor is
both wide and short as possible.
relatively small and can be ignored, the maximum ESR
2. The power discharge path consisting of SW trace,
could be calculated as below:
ΔVOUT external inductor, external diode and GND trace
ESR COUT ≤
ΔIL should be as both wide and short as possible.
3. The feedback path of the voltage divider should be
Choose the output capacitance according to the average
close to FB pin and away from any noisy traces,
value of RC product as below:
which may be isolated by a grounded copper.
50 ~ 80 ⋅ 10 −6
COUT ≈ 4. The (+) plates of input capacitors should be close to
ESR COUT
the IC.
(3): The ESR and the ripple current contribute in power 5. Keep the (-) plates of input and output capacitors as
dissipation in the capacitor that probably increases the close as possible.
capacitor’s internal temperature. Usually, the capacitors
manufactures specify ripple current ratings in order not to

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 LD7412
4 L1
VIN
+ 5,6
VIN SW
C3
- 2 EN +
C5
D1 C1 Load VOUT
C4 R4 LD7412
-
3
IOSET C2
FB 1
R3
GND R2
R1
7 8

Fig. 7

LD7412

Fig. 8

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 LD7412
Package Information
SOP-8

Dimensions in Millimeters Dimensions in Inch

Symbols
MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.229 0.007 0.009
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
θ 0° 8° 0° 8°

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice.
Customers should verify the datasheets are current and complete before placing order.

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 LD7412
IR Profile for SMD Devices
Temp.
(ºc)

Peak Temp.
300
260 -5/+0ºC, 30 seconds
(max.)

260
Ramp up
250
Ramp down
3ºC/second
6ºC/second max.
max.

217

200 217ºC
60 ~ 150 seconds

150

Preheat
60 ~ 120 seconds

100

50

0
Time (sec.)

Average Pre-heat Time Maintained Ramp-down

Item Peak Temp.
Ramp-up Rate (150 ~ 200°C) Above 217°C Rate

3°C(max) 260 +0/-5°C 6°C (max)

Required 60~120 sec 60~150 seconds
/sec 30 seconds /sec

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 LD7412
Revision History

Rev. Date Change Notice

00 12/1/2009 Original Specification.

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