8-Bit Microcontroller with UART and One Multi-Function Timer

COP688CS/COP684CS/COP888CS/COP884CS/COP988CS/COP984CS
August 1996

COP688CS/COP684CS/COP888CS/COP884CS/
COP988CS/COP984CS 8-Bit Microcontroller with UART
and One Multi-Function Timer
General Description Y Packages:
Ð 44 PLCC with 40 I/O pins
The COP888 family of microcontrollers uses an 8-bit single
Ð 40 DIP with 36 I/O pins
chip core architecture fabricated with National Semiconduc-
Ð 28 DIP with 24 I/O pins
tor’s M2CMOSTM process technology. The COP888CS is a
Ð 28 SO with 24 I/O pins
member of this expandable 8-bit core processor family of
microcontrollers. (Continued) CPU/Instruction Set Feature
Y 1 ms instruction cycle time
Key Features Y Ten multi-source vectored interrupts servicing
Y Full duplex UART Ð External interrupt with selectable edge
Y One 16-bit timer, with two 16-bit registers supporting: Ð Idle Timer T0
Ð Processor Independent PWM mode Ð Timer (2 interrupts)
Ð External Event counter mode Ð MICROWIRE/PLUS
Ð Input Capture mode Ð Multi-Input Wake Up
Y 4 kbytes of on-chip ROM Ð Software Trap
Y 192 bytes on-board RAM Ð UART (2)
Ð Default VIS (default interrupt)
Additional Peripheral Features Y Versatile instruction set
Y Idle Timer Y 8-bit Stack Pointer (SP)Ðstack in RAM
Y Multi-Input Wakeup (MIWU) with optional interrupts (8) Y Two 8-bit Register Indirect Data Memory Pointers
Y One analog comparator (B, X)
Y WATCHDOGTM and Clock Monitor logic
Y MICROWIRE/PLUSTM serial I/O Fully Static CMOS
Y Low current drain (typically k 1 mA)
I/O Features Y Single supply operation: 2.5V – 6.0V
Y Memory mapped I/O Y Temperature ranges: 0§ C to a 70§ C, b40§ C to a 85§ C,
Y Software selectable I/O options (TRI-STATEÉ Output, b 55§ C to a 125§ C
Push-Pull Output, Weak Pull Up Input, High Impedance
Input)
Development Support
Y Emulation and OTP devices
Y High current outputs
Y Real time emulation and full program debug offered by
Y Schmitt trigger inputs on Port G
MetaLink Development System

Block Diagram

TL/DD/10830 – 1
FIGURE 1. Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUSTM , M2CMOSTM , COP8TM Microcontrollers, MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.

C1996 National Semiconductor Corporation TL/DD10830 RRD-B30M106/Printed in U. S. A. http://www.national.com

 General Description (Continued)
It is a fully static part, fabricated using double-metal silicon IDLE), both with a multi-sourced wakeup/interrupt capabili-
gate microCMOS technology. Features include an 8-bit ty. This multi-sourced interrupt capability may also be used
memory mapped architecture, MICROWIRE/PLUS serial independent of the HALT or IDLE modes. Each I/O pin has
I/O, one 16-bit timer/counter supporting three modes (Proc- software selectable configurations. The device operates
essor Independent PWM generation, External Event coun- over a voltage range of 2.5V to 6V. High throughput is
ter, and Input Capture mode capabilities), full duplex UART, achieved with an efficient, regular instruction set operating
one comparator, and two power savings modes (HALT and at a maximum of 1 ms per instruction rate.

Connection Diagrams
Plastic Chip Carrier

TL/DD/10830 – 2
Top View
Order Number COP888CS-XXX/V,
COP988CS-XXX/V or COP988CSH-XXX/V
See NS Package Number V44A

Dual-In-Line Package Dual-In-Line Package

TL/DD/10830 – 5
Top View
Order Number COP884CS-XXX/N,
COP984CS-XXX/N or COP984CSH-XXX/N
See NS Package Number N28B

TL/DD/10830–3 Order Number COP884CS-XXX/WM,

Top View COP984CS-XXX/WM or COP984CSH-XXX/WM
See NS Package Number M28B
Order Number COP888CS-XXX/N,
COP988CS-XXX/N or COP988CSH-XXX/N
See NS Package Number N40A

FIGURE 2. Connection Diagrams

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Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages

28-Pin 40-Pin 44-Pin

Port Type Alt. Fun Alt. Fun
Pack. Pack. Pack.
L0 I/O MIWU 11 17 17
L1 I/O MIWU CKX 12 18 18
L2 I/O MIWU TDX 13 19 19
L3 I/O MIWU RDX 14 20 20
L4 I/O MIWU 15 21 25
L5 I/O MIWU 16 22 26
L6 I/O MIWU 17 23 27
L7 I/O MIWU 18 24 28
G0 I/O INT 25 35 39
G1 WDOUT 26 36 40
G2 I/O T1B 27 37 41
G3 I/O T1A 28 38 42
G4 I/O SO 1 3 3
G5 I/O SK 2 4 4
G6 I SI 3 5 5
G7 I/CKO HALT Restart 4 6 6
D0 O 19 25 29
D1 O 20 26 30
D2 O 21 27 31
D3 O 22 28 32
I0 I 7 9 9
I1 I COMP1INb 8 10 10
I2 I COMP1IN a 9 11 11
I3 I COMP1OUT 10 12 12
I4 I 13 13
I5 I 14 14
I6 I 15 15
I7 I 16 16
D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36
C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
VCC 6 8 8
GND 23 33 37
CKI 5 7 7
RESET 24 34 38

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 Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 110 mA
please contact the National Semiconductor Sales Storage Temperature Range b 65§ C to a 140§ C
Office/Distributors for availability and specifications.
Note: Absolute maximum ratings indicate limits beyond
Supply Voltage (VCC) 7V which damage to the device may occur. DC and AC electri-
Voltage at Any Pin b 0.3V to VCC a 0.3V cal specifications are not ensured when operating the de-
Total Current into VCC Pin (Source) 100 mA vice at absolute maximum ratings.
DC Electrical Characteristics 98XCS: 0§ C s TA s a 70§ C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage COP98XCS 2.5 4.0 V
COP98XCSH 4.0 6.0 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 VCC V
Supply Current (Note 2)
CKI e 10 MHz VCC e 6V, tc e 1 ms 12.5 mA
CKI e 4 MHz VCC e 6V, tc e 2.5 ms 5.5 mA
CKI e 4 MHz VCC e 4V, tc e 2.5 ms 2.5 mA
CKI e 1 MHz VCC e 4V, tc e 10 ms 1.4 mA
HALT Current (Note 3) VCC e 6V, CKI e 0 MHz k 0.7 8 mA
VCC e 4V, CKI e 0 MHz k 0.3 4 mA
IDLE Current
CKI e 10 MHz VCC e 6V, tc e 1 ms 3.5 mA
CKI e 4 MHz VCC e 6V, tc e 2.5 ms 2.5 mA
CKI e 1 MHz VCC e 4V, tc e 10 ms 0.7 mA
Input Levels
RESET
Logic High 0.8 VCC V
Logic Low 0.2 VCC V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
All Other Inputs
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
Hi-Z Input Leakage VCC e 6V b1 a1 mA
Input Pullup Current VCC e 6V, VIN e 0V b 40 b 250 mA
G and L Port Input Hysteresis 0.35 VCC V
Output Current Levels
D Outputs
Source VCC e 4V, VOH e 3.3V b 0.4 mA
VCC e 2.5V, VOH e 1.8V b 0.2 mA
Sink VCC e 4V, VOL e 1V 10 mA
VCC e 2.5V, VOL e 0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) VCC e 4V, VOH e 2.7V b 10 b 100 mA
VCC e 2.5V, VOH e 1.8V b 2.5 b 33 mA
Source (Push-Pull Mode) VCC e 4V, VOH e 3.3V b 0.4 mA
VCC e 2.5V, VOH e 1.8V b 0.2 mA
Sink (Push-Pull Mode) VCC e 4V, VOL e 0.4V 1.6 mA
VCC e 2.5V, VOL e 0.4V 0.7 mA
TRI-STATE Leakage VCC e 6.0V b1 a1 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.

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DC Electrical Characteristics 98XCS: 0§ C s TA s a 70§ C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3 mA
Maximum Input Current TA e 25§ C
g 100 mA
without Latchup (Note 5)
RAM Retention Voltage, Vr 500 ns Rise
2 V
and Fall Time (Min)
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF

AC Electrical Characteristics 98XCS: 0§ C s TA s a 70§ C unless otherwise specified

Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc) 4V s VCC s 6V 1 DC ms
Crystal, Resonator, 2.5V s VCC k 4V 2.5 DC ms
R/C Oscillator 4V s VCC s 6V 3 DC ms
2.5V s VCC k 4V 7.5 DC ms
Inputs
tSETUP 4V s VCC s 6V 200 ns
2.5V s VCC k 4V 500 ns
tHOLD 4V s VCC s 6V 60 ns
2.5V s VCC k 4V 150 ns
Output Propagation Delay (Note 6) RL e 2.2k, CL e 100 pF
tPD1, tPD0
SO, SK 4V s VCC s 6V 0.7 ms
2.5V s VCC k 4V 1.75 ms
All Others 4V s VCC s 6V 1 ms
2.5V s VCC k 4V 2.5 ms
MICROWIRETM Setup Time (tUWS) 20 ns
MICROWIRE Hold Time (tUWH) 56 ns
MICROWIRE Output Propagation Delay (tUPD) 220 ns
Input Pulse Width
Interrupt Input High Time 1 tc
Interrupt Input Low Time 1 tc
Timer Input High Time 1 tc
Timer Input Low Time 1 tc
Reset Pulse Width 1 ms
Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Notye 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

5 http://www.national.com
 Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 110 mA
please contact the National Semiconductor Sales Storage Temperature Range b 65§ C to a 140§ C
Office/Distributors for availability and specifications.
Note: Absolute maximum ratings indicate limits beyond
Supply Voltage (VCC) 7V which damage to the device may occur. DC and AC electri-
Voltage at Any Pin b 0.3V to VCC a 0.3V cal specifications are not ensured when operating the de-
Total Current into VCC Pin (Source) 100 mA vice at absolute maximum ratings.

DC Electrical Characteristics 88XCS: b40§ C s TA s a 85§ C unless otherwise specified

Parameter Conditions Min Typ Max Units
Operating Voltage 2.5 6 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 VCC V
Supply Current (Note 2)
CKI e 10 MHz VCC e 6V, tc e 1 ms 12.5 mA
CKI e 4 MHz VCC e 6V, tc e 2.5 ms 5.5 mA
HALT Current (Note 3) VCC e 6V, CKI e 0 MHz k1 10 mA
IDLE Current
CKI e 10 MHz VCC e 6V, tc e 1 ms 3.5 mA
CKI e 4 MHz VCC e 6V, tc e 2.5 ms 2.5 mA
Input Levels
RESET
Logic High 0.8 VCC V
Logic Low 0.2 VCC V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
All Other Inputs
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
Hi-Z Input Leakage VCC e 6V b2 a2 mA
Input Pullup Current VCC e 6V, VIN e 0V b 40 b 250 mA
G and L Port Input Hysteresis 0.35 VCC V
Output Current Levels
D Outputs
Source VCC e 4V, VOH e 3.3V b 0.4 mA
VCC e 2.5V, VOH e 1.8V b 0.2 mA
Sink VCC e 4V, VOL e 1V 10 mA
VCC e 2.5V, VOL e 0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) VCC e 4V, VOH e 2.7V b 10 b 100 mA
VCC e 2.5V, VOH e 1.8V b 2.5 b 33 mA
Source (Push-Pull Mode) VCC e 4V, VOH e 3.3V b 0.4 mA
VCC e 2.5V, VOH e 1.8V b 0.2 mA
Sink (Push-Pull Mode) VCC e 4V, VOL e 0.4V 1.6 mA
VCC e 2.5V, VOL e 0.4V 0.7 mA
TRI-STATE Leakage b2 a2 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.

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DC Electrical Characteristics 88XCS: b40§ C s TA s a 85§ C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3 mA
Maximum Input Current TA e 25§ C
g 100 mA
without Latchup (Note 5)
RAM Retention Voltage, Vr 500 ns Rise
2 V
and Fall Time (Min)
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF

AC Electrical Characteristics 88XCS: b40§ C s TA s a 85§ C unless otherwise specified

Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc) 4V s VCC s 6V 1 DC ms
Crystal, Resonator, 2.5V s VCC k 4V 2.5 DC ms
R/C Oscillator 4V s VCC s 6V 3 DC ms
2.5V s VCC k 4V 7.5 DC ms
Inputs
tSETUP 4V s VCC s 6V 200 ns
2.5V s VCC k 4V 500 ns
tHOLD 4V s VCC s 6V 60 ns
2.5V s VCC k 4V 150 ns
Output Propagation Delay (Note 6) RL e 2.2k, CL e 100 pF
tPD1, tPD0
SO, SK 4V s VCC s 6V 0.7 ms
2.5V s VCC k 4V 1.75 ms
All Others 4V s VCC s 6V 1 ms
2.5V s VCC k 4V 2.5 ms
MICROWIRE Setup Time (tUWS) 20 ns
MICROWIRE Hold Time (tUWH) 56 ns
MICROWIRE Output Propagation Delay (tUPD) 220 ns
Input Pulse Width
Interrupt Input High Time 1 tc
Interrupt Input Low Time 1 tc
Timer Input High Time 1 tc
Timer Input Low Time 1 tc
Reset Pulse Width 1 ms
Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

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 Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 110 mA
please contact the National Semiconductor Sales Storage Temperature Range b 65§ C to a 140§ C
Office/Distributors for availability and specifications.
Note: Absolute maximum ratings indicate limits beyond
Supply Voltage (VCC) 7V which damage to the device may occur. DC and AC electri-
Voltage at Any Pin b 0.3V to VCC a 0.3V cal specifications are not ensured when operating the de-
Total Current into VCC Pin (Source) 100 mA vice at absolute maximum ratings.

DC Electrical Characteristics 68XCS: b55§ C s TA s a 125§ C unless otherwise specified

Parameter Conditions Min Typ Max Units
Operating Voltage 4.5 5.5 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 VCC V
Supply Current (Note 2)
CKI e 10 MHz VCC e 5.5V, tc e 1 ms 12.5 mA
CKI e 4 MHz VCC e 5.5V, tc e 2.5 ms 5.5 mA
HALT Current (Note 3) VCC e 5.5V, CKI e 0 MHz k 10 30 mA
IDLE Current
CKI e 10 MHz VCC e 5.5V, tc e 1 ms 3.5 mA
CKI e 4 MHz VCC e 5.5V, tc e 2.5 ms 2.5 mA
Input Levels
RESET
Logic High 0.8 VCC V
Logic Low 0.2 VCC V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
All Other Inputs
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
Hi-Z Input Leakage VCC e 5.5V, VIN e 0V b5 a5 mA
Input Pullup Current VCC e 5.5V, VIN e 0V b 35 b 400 mA
G and L Port Input Hysteresis 0.35 VCC V
Output Current Levels
D Outputs
Source VCC e 4.5V, VOH e 3.8V b 0.4 mA
Sink VCC e 4.5V, VOL e 1V 9 mA
All Others
Source (Weak Pull-Up Mode) VCC e 4.5V, VOH e 3.2V b9 140 mA
Source (Push-Pull Mode) VCC e 4.5V, VOH e 3.8V b 0.4 mA
Sink (Push-Pull Mode) VCC e 4.5V, VOL e 0.4V 1.4 mA
TRI-STATE Leakage VCC e 5.5V b5 a5 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.

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DC Electrical Characteristics 68XCS: b55§ C s TA s a 125§ C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 12 mA
All others 2.5 mA
Maximum Input Current TA e 25§ C
g 100 mA
without Latchup (Note 5)
RAM Retention Voltage, Vr 500 ns Rise
2 V
and Fall Time (Min)
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF

AC Electrical Characteristics 68XCS: b55§ C s TA s a 125§ C unless otherwise specified

Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc) 4.5V s VCC s 5.5V 1 DC ms
Crystal, Resonator, 4.5V s VCC s 5.5V 3 DC ms
R/C Oscillator
Inputs
tSETUP 4.5V s VCC s 5.5V 200 ns
tHOLD 4.5V s VCC s 5.5V 60 ns
Output Propagation Delay (Note 6) RL e 2.2k, CL e 100 pF
tPD1, tPD0
SO, SK 4.5V s VCC s 5.5V 0.7 ms
All Others 4.5V s VCC s 5.5V 1 ms
MICROWIRE Setup Time (tUWS) 20 ns
MICROWIRE Hold Time (tUWH) 56 ns
MICROWIRE Output Propagation Delay (tUPD) 220 ns
Input Pulse Width
Interrupt Input High Time 1 tc
Interrupt Input Low Time 1 tc
Timer Input High Time 1 tc
Timer Input Low Time 1 tc
Reset Pulse Width 1 ms
Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

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 Comparator AC and DC Characteristics VCC e 5V, TA e 25§ C
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4V s VIN s VCC b 1.5V g 10 g 25 mV
Input Common Mode Voltage Range 0.4 VCC b 1.5 V
Low Level Output Current VOL e 0.4V 1.6 mA
High Level Output Current VOH e 4.6V 1.6 mA
DC Supply Current
250 mA
(When Enabled)
Response Time TBD mV Step, TBD mV
1 ms
Overdrive, 100 pF Load

TL/DD/10830 – 6
FIGURE 3. MICROWIRE/PLUS Timing

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Typical Performance Characteristics (b40§ C to a 85§ C)
HaltÐIDD IdleÐIDD (Crystal Clock Option)

TL/DD/10830 – 24 TL/DD/10830 – 25

Port L/C/G Weak Pull-Up

DynamicÐIDD (Crystal Clock Option) Source Current

TL/DD/10830 – 26 TL/DD/10830 – 27

Port L/C/G Push-Pull Source Current Port L/C/G/ Push-Pull Sink Current

TL/DD/10830 – 28 TL/DD/10830 – 29

Port D Source Current Port D Sink Current

TL/DD/10830 – 30 TL/DD/10830 – 31

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 Pin Descriptions
VCC and GND are the power supply pins. L4 MIWU
CKI is the clock input. This can come from an R/C generat- L5 MIWU
ed oscillator, or a crystal oscillator (in conjunction with L6 MIWU
CKO). See Oscillator Description section.
L7 MIWU
RESET is the master reset input. See Reset Description
Port G is an 8-bit port with 5 I/O pins (G0, G2 – G5), an input
section.
pin (G6), and two dedicated output pins (G1 and G7). Pins
The device contains three bidirectional 8-bit I/O ports (C, G G0 and G2 – G6 all have Schmitt Triggers on their inputs. Pin
and L), where each individual bit may be independently con- G1 serves as the dedicated WDOUT WATCHDOG output,
figured as an input (Schmitt trigger inputs on ports L and G), while pin G7 is either input or output depending on the oscil-
output or TRI-STATE under program control. Three data lator mask option selected. With the crystal oscillator option
memory address locations are allocated for each of these I/ selected, G7 serves as the dedicated output pin for the CKO
O ports. Each I/O port has two associated 8-bit memory clock output. With the single-pin R/C oscillator mask option
mapped registers, the CONFIGURATION register and the selected, G7 serves as a general purpose input pin but is
output DATA register. A memory mapped address is also also used to bring the device out of HALT mode with a low
reserved for the input pins of each I/O port. (See the memo- to high transition on G7. There are two registers associated
ry map for the various addresses associated with the I/O with the G Port, a data register and a configuration register.
ports.) Figure 4 shows the I/O port configurations. The Therefore, each of the 5 I/O bits (G0, G2 – G5) can be indi-
DATA and CONFIGURATION registers allow for each port vidually configured under software control.
bit to be individually configured under software control as
Since G6 is an input only pin and G7 is the dedicated CKO
shown below:
clock output pin (crystal clock option) or general purpose
input (R/C clock option), the associated bits in the data and
CONFIGURATION DATA configuration registers for G6 and G7 are used for special
Port Set-Up
Register Register purpose functions as outlined below. Reading the G6 and
G7 data bits will return zeros.
0 0 Hi-Z Input
(TRI-STATE Output) Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
0 1 Input with Weak Pull-Up
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
1 0 Push-Pull Zero Output
of the Port G Data Register.
1 1 Push-Pull One Output
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.

Config Reg. Data Reg.

G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
TL/DD/10830–7
FIGURE 4. I/O Port Configurations G6 SI (MICROWIRE Serial Data Input)
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on Port G has the following dedicated functions:
the inputs. G1 WDOUT WATCHDOG and/or Clock Monitor dedi-
The Port L supports Multi-Input Wake Up on all eight pins. cated output
L1 is used for the UART external clock. L2 and L3 are used G7 CKO Oscillator dedicated output or general pur-
for the UART transmit and receive. pose input
The Port L has the following alternate features: Port C is an 8-bit I/O port. The 40-pin device does not have
L0 MIWU a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
L1 MIWU or CKX pins will return unpredictable values.
L2 MIWU or TDX Port I is an eight-bit Hi-Z input port. The 28-pin device does
L3 MIWU or RDX not have a full complement of Port I pins. The unavailable

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 and Pin), the control registers, the MICROWIRE/PLUS SIO
Pin Descriptions (Continued) shift register, and the various registers, and counters asso-
pins are not terminated i.e., they are floating. A read opera- ciated with the timers (with the exception of the IDLE timer).
tion for these unterminated pins will return unpredictable Data memory is addressed directly by the instruction or indi-
values. The user must ensure that the software takes this rectly by the B, X, SP pointers and S register.
into account by either masking or restricting the accesses to
The device has 192 bytes of RAM. Sixteen bytes of RAM
bit operations. The unterminated Port I pins will draw power
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
only when addressed.
These registers can be loaded immediately, and also decre-
Ports I1 – I3 are used for Comparator 1. mented and tested with the DRSZ (decrement register and
Ports I1 – I3 have the following alternate features. skip if zero) instruction. The memory pointer registers X, SP,
I1 COMP1bIN (Comparator 1 Negative Input) B and S are memory mapped into this space at address
locations 0FC to 0FF Hex respectively, with the other regis-
I2 COMP1 a IN (Comparator 1 Positive Input)
ters being available for general usage.
I3 COMP1OUT (Comparator 1 Output)
The instruction set permits any bit in memory to be set,
Port D is an 8-bit output port that is preset high when reset or tested. All I/O and registers (except A and PC) are
RESET goes low. The user can tie two or more D port out- memory mapped; therefore, I/O bits and register bits can be
puts (except D2) together in order to get a higher drive. directly and individually set, reset and tested. The accumu-
Note: Care must be exercised with the D2 pin operation. At RESET, the lator (A) bits can also be directly and individually tested.
external loads on this pin must ensure that the output voltages stay
above 0.8 VCC to prevent the chip from entering special modes. Also Note: RAM contents are undefined upon power-up.
keep the external loading on D2 to less than 1000 pF.
Data Memory Segment
Functional Description RAM Extension
The architecture of the device is modified Harvard architec- Data memory address 0FF is used as a memory mapped
ture. With the Harvard architecture, the control store pro- location for the Data Segment Address Register (S).
gram memory (ROM) is separated from the data store mem-
ory (RAM). Both ROM and RAM have their own separate The data store memory is either addressed directly by a
addressing space with separate address buses. The archi- single byte address within the instruction, or indirectly rela-
tecture, though based on Harvard architecture, permits tive to the reference of the B, X, or SP pointers (each con-
transfer of data from ROM to RAM. tains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
CPU REGISTERS The upper bit of this single-byte address divides the data
The CPU can do an 8-bit addition, subtraction, logical or store memory into two separate sections as outlined previ-
shift operation in one instruction (tc) cycle time. ously. With the exception of the RAM register memory from
address locations 00F0 to 00FF, all RAM memory is memo-
There are six CPU registers:
ry mapped with the upper bit of the single-byte address be-
A is the 8-bit Accumulator Register ing equal to zero. This allows the upper bit of the single-byte
PC is the 15-bit Program Counter Register address to determine whether or not the base address
PU is the upper 7 bits of the program counter (PC) range (from 0000 to 00FF) is extended. If this upper bit
PL is the lower 8 bits of the program counter (PC) equals one (representing address range 0080 to 00FF),
B is an 8-bit RAM address pointer, which can be optionally then address extension does not take place. Alternatively, if
post auto incremented or decremented. this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
X is an 8-bit alternate RAM address pointer, which can be 0000 to 007F) from XX00 to XX7F, where XX represents the
optionally post auto incremented or decremented. 8 bits from the S register. Thus the 128-byte data segment
SP is the 8-bit stack pointer, which points to the subroutine/ extensions are located from addresses 0100 to 017F for
interrupt stack (in RAM). The SP is initialized to RAM ad- data segment 1, 0200 to 027F for data segment 2, etc., up
dress 06F with reset. to FF00 to FF7F for data segment 255. The base address
S is the 8-bit Data Segment Address Register used to ex- range from 0000 to 007F represents data segment 0.
tend the lower half of the address range (00 to 7F) into 256 Figure 5 illustrates how the S register data memory exten-
data segments of 128 bytes each. sion is used in extending the lower half of the base address
All the CPU registers are memory mapped with the excep- range (00 to 7F hex) into 256 data segments of 128 bytes
tion of the Accumulator (A) and the Program Counter (PC). each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg-
PROGRAM MEMORY
ments of 128 bytes each with an additional upper base seg-
Program memory consists of 4096 bytes of ROM. These ment of 128 bytes. Furthermore, all addressing modes are
bytes may hold program instructions or constant data (data available for all data segments. The S register must be
tables for the LAID instruction, jump vectors for the JID in- changed under program control to move from one data seg-
struction, and interrupt vectors for the VIS instruction). The ment (128 bytes) to another. However, the upper base seg-
program memory is addressed by the 15-bit program coun- ment (containing the 16 memory registers, I/O registers,
ter (PC). All interrupts vector to program memory location control registers, etc.) is always available regardless of the
0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data

13 http://www.national.com
 pulled low. Upon initialization, the data and configuration
Data Memory Segment registers for ports L, G and C are cleared, resulting in these
RAM Extension (Continued) Ports being initialized to the TRI-STATE mode. Pin G1 of the
contents of the S register, since the upper base segment G Port is an exception (as noted below) since pin G1 is
(address range 0080 to 00FF) is independent of data seg- dedicated as the WATCHDOG and/or Clock Monitor error
ment extension. output pin. Port D is set high. The PC, PSW, ICNTRL,
CNTRL, are cleared. The UART registers PSR, ENU (except
The instructions that utilize the stack pointer (SP) always
that TBMT bit is set), ENUR and ENUI are cleared. The
reference the stack as part of the base segment (Segment
Comparator Select Register is cleared. The S register is ini-
0), regardless of the contents of the S register. The S regis-
tialized to zero. The Multi-Input Wakeup registers WKEN,
ter is not changed by these instructions. Consequently, the
WKEDG and WKPND are cleared. The stack pointer, SP, is
stack (used with subroutine linkage and interrupts) is always
initialized to 6F Hex.
located in the base segment. The stack pointer will be inti-
tialized to point at data memory location 006F as a result of The device comes out of reset with both the WATCHDOG
reset. logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
The 128 bytes of RAM contained in the base segment are
bit set. The WATCHDOG and Clock Monitor circuits are in-
split between the lower and upper base segments. The first
hibited during reset. The WATCHDOG service window bits
112 bytes of RAM are resident from address 0000 to 006F
being initialized high default to the maximum WATCHDOG
in the lower base segment, while the remaining 16 bytes of
service window of 64k tC clock cycles. The Clock Monitor bit
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM being initialized high will cause a Clock Monitor error follow-
is located at the upper sixteen addresses (0070 to 007F) of ing reset if the clock has not reached the minimum specified
the lower base segment. frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
Additional RAM beyond these initial 128 bytes, however, will output will continue until 16 tC –32 tC clock cycles following
always be memory mapped in groups of 128 bytes (or less) the clock frequency reaching the minimum specified value,
at the data segment address extensions (XX00 to XX7F) of at which time the G1 output will enter the TRI-STATE mode.
the lower base segment. The additional 64 bytes of RAM
(beyond the initial 128 bytes) are memory mapped at ad- The external RC network shown in Figure 6 should be used
dress locations 0100 to 013F hex. to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

TL/DD/10830 – 9
RC l 5 c Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit

Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1/tc).
TL/DD/10830–8 Figure 7 shows the Crystal and R/C diagrams.
*Reads as all ones.
CRYSTAL OSCILLATOR
FIGURE 5. RAM Organization
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Reset
Table A shows the component values required for various
The RESET input when pulled low initializes the microcon-
standard crystal values.
troller. Initialization will occur whenever the RESET input is

http://www.national.com 14
Oscillator Circuits (Continued) Control Registers
R/C OSCILLATOR CNTRL Register (Address XÊ 00EE)
By selecting CKI as a single pin oscillator input, a single pin The Timer1 (T1) and MICROWIRE/PLUS control register
R/C oscillator circuit can be connected to it. CKO is avail- contains the following bits:
able as a general purpose input, and/or HALT restart input. SL1 & SL0 Select the MICROWIRE/PLUS clock divide
Table B shows the variation in the oscillator frequencies as by (00 e 2, 01 e 4, 1x e 8)
functions of the component (R and C) values. IEDG External interrupt edge polarity select
(0 e Rising edge, 1 e Falling edge)
MSEL Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
TL/DD/10830 – 11
T1C1 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C3 Timer T1 mode control bit
TL/DD/10830–10
FIGURE 7. Crystal and R/C Oscillator Diagrams
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
TABLE A. Crystal Oscillator Configuration, TA e 25§ C Bit 7 Bit 0
R1 R2 C1 C2 CKI Freq PSW Register (Address XÊ 00EF)
Conditions
(kX) (MX) (pF) (pF) (MHz) The PSW register contains the following select bits:
0 1 30 30–36 10 VCC e 5V GIE Global interrupt enable (enables interrupts)
0 1 30 30–36 4 VCC e 5.0V EXEN Enable external interrupt
0 1 200 100–150 0.455 VCC e 2.5V BUSY MICROWIRE/PLUS busy shifting flag
EXPND External interrupt pending
TABLE B. RC Oscillator Configuration, TA e 25§ C T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
R C CKI Freq Instr. Cycle
Conditions T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
(kX) (pF) (MHz) (ms) in mode 1, T1 Underflow in Mode 2, T1A cap-
3.3 82 2.2 to 2.7 3.7 to 4.6 VCC e 5V ture edge in mode 3)
5.6 100 1.1 to 1.3 7.4 to 9.0 VCC e 5V C Carry Flag
6.8 100 0.9 to 1.1 8.8 to 10.8 VCC e 5V HC Half Carry Flag
Note: 3k s R s 200k
50 pF s C s 200 pF
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the car-
ry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

15 http://www.national.com
 interrupt from the thirteenth bit of Timer T0 to be enabled or
Control Registers (Continued) disabled. Setting T0EN will enable the interrupt, while reset-
ICNTRL Register (Address XÊ 00E8) ting it will disable the interrupt.
The ICNTRL register contains the following bits: TIMER T1
T1ENB Timer T1 Interrupt Enable for T1B Input capture The device has a powerful timer/counter block.
edge
The timer block consists of a 16-bit timer, T1, and two sup-
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap- porting 16-bit autoreload/capture registers, R1A and R1B. It
ture edge has two pins associated with it, T1A and T1B. The pin T1A
mWEN Enable MICROWIRE/PLUS interrupt supports I/O required by the timer block, while the pin T1B
mWPND MICROWIRE/PLUS interrupt pending is an input to the timer block. The powerful and flexible timer
block allows the device to easily perform all timer functions
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
with minimal software overhead. The timer block has three
T0PND Timer T0 Interrupt pending operating modes: Processor Independent PWM mode, Ex-
LPEN L Port Interrupt Enable (Multi-Input Wakeup/In- ternal Event Counter mode, and Input Capture mode.
terrupt) The control bits T1C3, T1C2, and T1C1 allow selection of
Bit 7 could be used as a flag the different modes of operation.
Mode 1. Processor Independent PWM Mode
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB As the name suggests, this mode allows the device to gen-
Bit 7 Bit 0 erate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
Timers signal (ON time and OFF time). Once begun, the timer block
The device contains a very versatile set of timers (T0, T1). will continuously generate the PWM signal completely inde-
All timers and associated autoreload/capture registers pow- pendent of the microcontroller. The user software services
er up containing random data. the timer block only when the PWM parameters require up-
dating.
TIMER T0 (IDLE TIMER) In this mode the timer T1 counts down at a fixed rate of tc.
The device supports applications that require maintaining Upon every underflow the timer is alternately reloaded with
real time and low power with the IDLE mode. This IDLE the contents of supporting registers, R1A and R1B. The
mode support is furnished by the IDLE timer T0, which is a very first underflow of the timer causes the timer to reload
16-bit timer. The Timer T0 runs continuously at the fixed from the register R1A. Subsequent underflows cause the
rate of the instruction cycle clock, tc. The user cannot read timer to be reloaded from the registers alternately beginning
or write to the IDLE Timer T0, which is a count down timer. with the register R1B.
The Timer T0 supports the following functions: The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
Exit out of the Idle Mode (See Idle Mode description) timer for PWM mode operation.
WATCHDOG logic (See WATCHDOG description) Figure 8 shows a block diagram of the timer in PWM mode.
Start up delay out of the HALT mode The underflows can be programmed to toggle the T1A out-
The IDLE Timer T0 can generate an interrupt when the thir- put pin. The underflows can also be programmed to gener-
teenth bit toggles. This toggle is latched into the T0PND ate interrupts.
pending flag, and will occur every 4 ms at the maximum
clock frequency (tc e 1 ms). A control flag T0EN allows the

TL/DD/10830 – 12
FIGURE 8. Timer in PWM Mode

http://www.national.com 16
Timers (Continued)
Underflows from the timer are alternately latched into two The timer value gets copied over into the register when a
pending flags, T1PNDA and T1PNDB. The user must reset trigger event occurs on its corresponding pin. Control bits,
these pending flags under software control. Two control en- T1C3, T1C2 and T1C1, allow the trigger events to be speci-
able flags, T1ENA and T1ENB, allow the interrupts from the fied either as a positive or a negative edge. The trigger con-
timer underflow to be enabled or disabled. Setting the timer dition for each input pin can be specified independently.
enable flag T1ENA will cause an interrupt when a timer un- The trigger conditions can also be programmed to generate
derflow causes the R1A register to be reloaded into the interrupts. The occurrence of the specified trigger condition
timer. Setting the timer enable flag T1ENB will cause an on the T1A and T1B pins will be respectively latched into
interrupt when a timer underflow causes the R1B register to the pending flags, T1PNDA and T1PNDB. The control flag
be reloaded into the timer. Resetting the timer enable flags T1ENA allows the interrupt on T1A to be either enabled or
will disable the associated interrupts. disabled. Setting the T1ENA flag enables interrupts to be
Either or both of the timer underflow interrupts may be en- generated when the selected trigger condition occurs on the
abled. This gives the user the flexibility of interrupting once T1A pin. Similarly, the flag T1ENB controls the interrupts
per PWM period on either the rising or falling edge of the from the T1B pin.
PWM output. Alternatively, the user may choose to interrupt Underflows from the timer can also be programmed to gen-
on both edges of the PWM output. erate interrupts. Underflows are latched into the timer T1C0
Mode 2. External Event Counter Mode pending flag (the T1C0 control bit serves as the timer under-
This mode is quite similar to the processor independent flow interrupt pending flag in the Input Capture mode). Con-
PWM mode described above. The main difference is that sequently, the T1C0 control bit should be reset when enter-
the timer, T1, is clocked by the input signal from the T1A ing the Input Capture mode. The timer underflow interrupt is
pin. The Tx timer control bits, T1C3, T1C2 and T1C1 allow enabled with the T1ENA control flag. When a T1A interrupt
the timer to be clocked either on a positive or negative edge occurs in the Input Capture mode, the user must check both
from the T1A pin. Underflows from the timer are latched into the T1PNDA and T1C0 pending flags in order to determine
the T1PNDA pending flag. Setting the T1ENA control flag whether a T1A input capture or a timer underflow (or both)
will cause an interrupt when the timer underflows. caused the interrupt.
In this mode the input pin T1B can be used as an indepen- Figure 10 shows a block diagram of the timer in Input Cap-
dent positive edge sensitive interrupt input if the T1ENB ture mode.
control flag is set. The occurrence of a positive edge on the TIMER CONTROL FLAGS
T1B input pin is latched into the T1PNDB flag.
The control bits and their functions are summarized below.
Figure 9 shows a block diagram of the timer in External
T1C0 Timer Start/Stop control in Modes 1 and 2
Event Counter mode.
(Processor Independent PWM and External
Note: The PWM output is not available in this mode since the T1A pin is
Event Counter), where 1 e Start, 0 e Stop
being used as the counter input clock.
Timer Underflow Interrupt Pending Flag in
Mode 3. Input Capture Mode Mode 3 (Input Capture)
The device can precisely measure external frequencies or T1PNDA Timer Interrupt Pending Flag
time external events by placing the timer block, T1, in the T1PNDB Timer Interrupt Pending Flag
input capture mode. T1ENA Timer Interrupt Enable Flag
In this mode, the timer T1 is constantly running at the fixed T1ENB Timer Interrupt Enable Flag
tc rate. The two registers, R1A and R1B, act as capture 1 e Timer Interrupt Enabled
registers. Each register acts in conjunction with a pin. The 0 e Timer Interrupt Disabled
register R1A acts in conjunction with the T1A pin and the T1C3 Timer mode control
register R1B acts in conjunction with the T1B pin. T1C2 Timer mode control
T1C1 Timer mode control

TL/DD/10830 – 13 TL/DD/10830 – 14
FIGURE 9. Timer in External Event Counter Mode FIGURE 10. Timer in Input Capture Mode

17 http://www.national.com
 Timers (Continued)
The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:

Interrupt A Interrupt B Timer

T1C3 T1C2 T1C1 Timer Mode
Source Source Counts On
0 0 0 MODE 2 (External Timer Pos. T1B T1A
Event Counter) Underflow Edge Pos. Edge
0 0 1 MODE 2 (External Timer Pos. T1B T1A
Event Counter) Underflow Edge Neg. Edge
1 0 1 MODE 1 (PWM) Autoreload Autoreload
tc
T1A Toggle RA RB
1 0 0 MODE 1 (PWM) Autoreload Autoreload
tc
No T1A Toggle RA RB
0 1 0 MODE 3 (Capture) Pos. T1A Pos. T1B tc
Captures: Edge or Edge
T1A Pos. Edge Timer
T1B Pos. Edge Underflow
1 1 0 MODE 3 (Capture) Pos. T1A Neg. T1B tc
Captures: Edge or Edge
T1A Pos. Edge Timer
T1B Neg. Edge Underflow
0 1 1 MODE 3 (Capture) Neg. T1B Pos. T1B tc
Captures: Edge or Edge
T1A Neg. Edge Timer
T1B Pos. Edge Underflow
1 1 1 MODE 3 (Capture) Neg. T1A Neg. T1B tc
Captures: Edge or Edge
T1A Neg. Edge Timer
T1B Neg. Edge Underflow

Power Save Modes

The device offers the user two power save modes of opera- with the Multi-Input Wakeup feature on the L port. The sec-
tion: HALT and IDLE. In the HALT mode, all microcontroller ond method is with a low to high transition on the CKO (G7)
activities are stopped. In the IDLE mode, the on-board oscil- pin. This method precludes the use of the crystal clock con-
lator circuitry the WATCHDOG logic, the Clock Monitor and figuration (since CKO becomes a dedicated output), and so
timer T0 are active but all other microcontroller activities are may be used with an RC clock configuration. The third
stopped. In either mode, all on-board RAM, registers, I/O method of exiting the HALT mode is by pulling the RESET
states, and timers (with the exception of T0) are unaltered. pin low.
HALT MODE Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
The device is placed in the HALT mode by writing a ‘‘1’’ to
running immediately since crystal oscillators and ceramic
the HALT flag (G7 data bit). All microcontroller activities,
resonators have a delayed start up time to reach full ampli-
including the clock and timers, are stopped. The WATCH-
tude and frequency stability. The IDLE timer is used to gen-
DOG logic is disabled during the HALT mode. However, the
erate a fixed delay to ensure that the oscillator has indeed
clock monitor circuitry if enabled remains active and will
stabilized before allowing instruction execution. In this case,
cause the WATCHDOG output pin (WDOUT) to go low. If
upon detecting a valid Wakeup signal, only the oscillator
the HALT mode is used and the user does not want to acti-
circuitry is enabled. The IDLE timer is loaded with a value of
vate the WDOUT pin, the Clock Monitor should be disabled
256 and is clocked with the tc instruction cycle clock. The tc
after the device comes out of reset (resetting the Clock
clock is derived by dividing the oscillator clock down by a
Monitor control bit with the first write to the WDSVR regis-
factor of 10. The Schmitt trigger following the CKI inverter
ter). In the HALT mode, the power requirements of the de-
on the chip ensures that the IDLE timer is clocked only
vice are minimal and the applied voltage (VCC) may be de-
when the oscillator has a sufficiently large amplitude to
creased to Vr (Vr e 2.0V) without altering the state of the
meet the Schmitt trigger specifications. This Schmitt trigger
machine.
is not part of the oscillator closed loop. The startup timeout
The device supports three different ways of exiting the from the IDLE timer enables the clock signals to be routed
HALT mode. The first method of exiting the HALT mode is to the rest of the chip.

http://www.national.com 18
Power Save Modes (Continued)
If an RC clock option is being used, the fixed delay is intro- normal operation from the IDLE mode when the thirteenth
duced optionally. A control bit, CLKDLY, mapped as config- bit (representing 4.096 ms at internal clock frequency of
uration bit G7, controls whether the delay is to be intro- 1 MHz, tc e 1 ms) of the IDLE Timer toggles.
duced or not. The delay is included if CLKDLY is set, and This toggle condition of the thirteenth bit of the IDLE Timer
excluded if CLKDLY is reset. The CLKDLY bit is cleared on T0 is latched into the T0PND pending flag.
reset.
The user has the option of being interrupted with a transition
The device has two mask options associated with the HALT on the thirteenth bit of the IDLE Timer T0. The interrupt can
mode. The first mask option enables the HALT mode fea- be enabled or disabled via the T0EN control bit. Setting the
ture, while the second mask option disables the HALT T0EN flag enables the interrupt and vice versa.
mode. With the HALT mode enable mask option, the device
The user can enter the IDLE mode with the Timer T0 inter-
will enter and exit the HALT mode as described above. With
rupt enabled. In this case, when the T0PND bit gets set, the
the HALT disable mask option, the device cannot be placed
device will first execute the Timer T0 interrupt service rou-
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
tine and then return to the instruction following the ‘‘Enter
no effect).
Idle Mode’’ instruction.
The WATCHDOG detector circuit is inhibited during the
Alternatively, the user can enter the IDLE mode with the
HALT mode. However, the clock monitor circuit if enabled
IDLE Timer T0 interrupt disabled. In this case, the device
remains active during HALT mode in order to ensure a clock
will resume normal operation with the instruction immediate-
monitor error if the device inadvertently enters the HALT
ly following the ‘‘Enter IDLE Mode’’ instruction.
mode as a result of a runaway program or power glitch.
Note: It is necessary to program two NOP instructions following both the set
IDLE MODE HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
The device is placed in the IDLE mode by writing a ‘‘1’’ to IDLE modes.
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, the WATCH-
DOG logic, the clock monitor and the IDLE Timer T0, are
Multi-Input Wakeup
stopped. The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
As with the HALT mode, the device can be returned to nor-
Multi-Input Wakeup/Interrupt feature may also be used to
mal operation with a reset, or with a Multi-Input Wakeup
generate up to 8 edge selectable external interrupts.
from the L Port. Alternately, the microcontroller resumes
Figure 11 shows the Multi-Input Wakeup logic.

TL/DD/10830 – 15
FIGURE 11. Multi-Input Wake Up Logic

19 http://www.national.com
 Multi-Input Wakeup (Continued)
The Multi-Input Wakeup feature utilizes the L Port. The user PORT L INTERRUPTS
selects which particular L port bit (or combination of L Port Port L provides the user with an additional eight fully select-
bits) will cause the device to exit the HALT or IDLE modes. able, edge sensitive interrupts which are all vectored into
The selection is done through the Reg: WKEN. The Reg: the same service subroutine.
WKEN is an 8-bit read/write register, which contains a con-
The interrupt from Port L shares logic with the wake up cir-
trol bit for every L port bit. Setting a particular WKEN bit
cuitry. The register WKEN allows interrupts from Port L to
enables a Wakeup from the associated L port pin.
be individually enabled or disabled. The register WKEDG
The user can select whether the trigger condition on the specifies the trigger condition to be either a positive or a
selected L Port pin is going to be either a positive edge (low negative edge. Finally, the register WKPND latches in the
to high transition) or a negative edge (high to low transition). pending trigger conditions.
This selection is made via the Reg: WKEDG, which is an 8-
The GIE (Global Interrupt Enable) bit enables the interrupt
bit control register with a bit assigned to each L Port pin.
function.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit A control flag, LPEN, functions as a global interrupt enable
selects the trigger condition to be a positive edge. Changing for Port L interrupts. Setting the LPEN flag will enable inter-
an edge select entails several steps in order to avoid a rupts and vice versa. A separate global pending flag is not
pseudo Wakeup condition as a result of the edge change. needed since the register WKPND is adequate.
First, the associated WKEN bit should be reset, followed by Since Port L is also used for waking the device out of the
the edge select change in WKEDG. Next, the associated HALT or IDLE modes, the user can elect to exit the HALT or
WKPND bit should be cleared, followed by the associated IDLE modes either with or without the interrupt enabled. If
WKEN bit being re-enabled. he elects to disable the interrupt, then the device will restart
An example may serve to clarify this procedure. Suppose execution from the instruction immediately following the in-
we wish to change the edge select from positive (low going struction that placed the microcontroller in the HALT or
high) to negative (high going low) for L Port bit 5, where bit 5 IDLE modes. In the other case, the device will first execute
has previously been enabled for an input interrupt. The pro- the interrupt service routine and then revert to normal oper-
gram would be as follows: ation.
RBIT 5, WKEN The Wakeup signal will not start the chip running immediate-
SBIT 5, WKEDG ly since crystal oscillators or ceramic resonators have a fi-
RBIT 5, WKPND nite start up time. The IDLE Timer (T0) generates a fixed
SBIT 5, WKEN delay to ensure that the oscillator has indeed stabilized be-
fore allowing the device to execute instructions. In this case,
If the L port bits have been used as outputs and then
upon detecting a valid Wakeup signal, only the oscillator
changed to inputs with Multi-Input Wakeup/Interrupt, a safe-
circuitry and the IDLE Timer T0 are enabled. The IDLE Tim-
ty procedure should also be followed to avoid inherited
er is loaded with a value of 256 and is clocked from the tc
pseudo wakeup conditions. After the selected L port bits
instruction cycle clock. The tc clock is derived by dividing
have been changed from output to input but before the as-
down the oscillator clock by a factor of 10. A Schmitt trigger
sociated WKEN bits are enabled, the associated edge se-
following the CKI on-chip inverter ensures that the IDLE tim-
lect bits in WKEDG should be set or reset for the desired
er is clocked only when the oscillator has a sufficiently large
edge selects, followed by the associated WKPND bits being
amplitude to meet the Schmitt trigger specifications. This
cleared.
Schmitt trigger is not part of the oscillator closed loop. The
This same procedure should be used following reset, since startup timeout from the IDLE timer enables the clock sig-
the L port inputs are left floating as a result of reset. nals to be routed to the rest of the chip.
The occurrence of the selected trigger condition for Multi-In- If the RC clock option is used, the fixed delay is under soft-
put Wakeup is latched into a pending register called ware control. A control flag, CLKDLY, in the G7 configura-
WKPND. The respective bits of the WKPND register will be tion bit allows the clock start up delay to be optionally insert-
set on the occurrence of the selected trigger edge on the ed. Setting CLKDLY flag high will cause clock start up delay
corresponding Port L pin. The user has the responsibility of to be inserted and resetting it will exclude the clock start up
clearing these pending flags. Since WKPND is a pending delay. The CLKDLY flag is cleared during reset, so the clock
register for the occurrence of selected wakeup conditions, start up delay is not present following reset with the RC
the device will not enter the HALT mode if any Wakeup bit is clock options.
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempt-
ing to enter the HALT mode.
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.

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 UART CONTROL AND STATUS REGISTERS
UART
The operation of the UART is programmed through three
The device contains a full-duplex software programmable
registers: ENU, ENUR and ENUI. The function of the individ-
UART. The UART (Figure 12) consists of a transmit shift
ual bits in these registers is as follows:
register, a receiver shift register and seven addressable reg-
isters, as follows: a transmit buffer register (TBUF), a receiv- ENU-UART Control and Status Register (Address at 0BA)
er buffer register (RBUF), a UART control and status regis-
PEN PSEL1 XBIT9/ CHL1 CHL0 ERR RBFL TBMT
ter (ENU), a UART receive control and status register
(ENUR), a UART interrupt and clock source register (ENUI), PSEL0
a prescaler select register (PSR) and baud (BAUD) register. 0RW 0RW 0RW 0RW 0RW 0R 0R 1R
The ENU register contains flags for transmit and receive Bit 7 Bit 0
functions; this register also determines the length of the
ENUR-UART Receive Control and Status Register
data frame (7, 8 or 9 bits), the value of the ninth bit in trans-
(Address at 0BB)
mission, and parity selection bits. The ENUR register flags
framming, data overrun and parity errors while the UART is DOE FE PE SPARE RBIT9 ATTN XMTG RCVG
receiving. 0RD 0RD 0RD 0RW* 0R 0RW 0R 0R
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the Bit7 Bit0
UART’s attention mode of operation and providing addition- ENUI-UART Interrupt and Clock Source Register
al receiver/transmitter status information via RCVG and (Address at 0BC)
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as select- STP2 STP78 ETDX SSEL XRCLK XTCLK ERI ETI
ing the number of stop bits and enabling or disabling trans- 0RW 0RW 0RW 0RW 0RW 0RW 0RW 0RW
mit and receive interrupts. A control flag in this register can Bit7 Bit0
also select the UART mode of operation: asynchronous or *Bit is not used.
synchronous. 0 Bit is cleared on reset.
1 Bit is set to one on reset.
R Bit is read-only; it cannot be written by software.
RW Bit is read/write.
D Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.

TL/DD/10830 – 16
FIGURE 12. UART Block Diagram

21 http://www.national.com
 UART (Continued)
DESCRIPTION OF UART REGISTER BITS SPARE: Reserved for future use.
ENUÐUART CONTROL AND STATUS REGISTER PE: Flags a Parity Error.
PE e 0 Indicates no Parity Error has been detected since
TBMT: This bit is set when the UART transfers a byte of
the last time the ENUR register was read.
data from the TBUF register into the TSFT register for trans-
PE e 1 Indicates the occurence of a Parity Error.
mission. It is automatically reset when software writes into
the TBUF register. FE: Flags a Framing Error.
FE e 0 Indicates no Framing Error has been detected
RBFL: This bit is set when the UART has received a com-
since the last time the ENUR register was read.
plete character and has copied it into the RBUF register. It
FE e 1 Indicates the occurence of a Framing Error.
is automatically reset when software reads the character
from RBUF. DOE: Flags a Data Overrun Error.
DOE e 0 Indicates no Data Overrun Error has been de-
ERR: This bit is a global UART error flag which gets set if
tected since the last time the ENUR register
any or a combination of the errors (DOE, FE, PE) occur.
was read.
CHL1, CHL0: These bits select the character frame format. DOE e 1 Indicates the occurence of a Data Overrun Er-
Parity is not included and is generated/verified by hardware. ror.
CHL1 e 0, CHL0 e 0 The frame contains eight data bits.
CHL1 e 0, CHL0 e 1 The frame contains seven data ENUIÐUART INTERRUPT AND
bits. CLOCK SOURCE REGISTER
CHL1 e 1, CHL0 e 0 The frame contains nine data bits. ETI: This bit enables/disables interrupt from the transmitter
CHL1 e 1, CHL0 e 1 Loopback Mode selected. Trans- section.
mitter output internally looped ETI e 0 Interrupt from the transmitter is disabled.
back to receiver input. Nine bit ETI e 1 Interrupt from the transmitter is enabled.
framing format is used. ERI: This bit enables/disables interrupt from the receiver
XBIT9/PSEL0: Programs the ninth bit for transmission section.
when the UART is operating with nine data bits per frame. ERI e 0 Interrupt from the receiver is disabled.
For seven or eight data bits per frame, this bit in conjunction ERI e 1 Interrupt from the receiver is enabled.
with PSEL1 selects parity. XTCLK: This bit selects the clock source for the transmitter-
PSEL1, PSEL0: Parity select bits. section.
PSEL1 e 0, PSEL0 e 0 Odd Parity (if Parity enabled) XTCLK e 0 The clock source is selected through the
PSEL1 e 0, PSEL0 e 1 Even Parity (if Parity enabled) PSR and BAUD registers.
PSEL1 e 1, PSEL0 e 0 Mark(1) (if Parity enabled) XTCLK e 1 Signal on CKX (L1) pin is used as the clock.
PSEL1 e 1, PSEL0 e 1 Space(0) (if Parity enabled) XRCLK: This bit selects the clock source for the receiver
PEN: This bit enables/disables Parity (7- and 8-bit modes section.
only). XRCLK e 0 The clock source is selected through the
PEN e 0 Parity disabled. PSR and BAUD registers.
PEN e 1 Parity enabled. XRCLK e 1 Signal on CKX (L1) pin is used as the clock.
ENURÐUART RECEIVE CONTROL AND SSEL: UART mode select.
STATUS REGISTER SSEL e 0 Asynchronous Mode.
SSEL e 1 Synchronous Mode.
RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high. ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
XMTG: This bit is set to indicate that the UART is transmit-
To simulate line break generation, software should reset
ting. It gets reset at the end of the last frame (end of last
ETDX bit and output logic zero to TDX pin through Port L
Stop bit).
data and configuration registers.
ATTN: ATTENTION Mode is enabled while this bit is set.
STP78: This bit is set to program the last Stop bit to be
This bit is cleared automatically on receiving a character
7/8th of a bit in length.
with data bit nine set.
STP2: This bit programs the number of Stop bits to be trans-
RBIT9: Contains the ninth data bit received when the UART
mitted.
is operating with nine data bits per frame.
STP2 e 0 One Stop bit transmitted.
STP2 e 1 Two Stop bits transmitted.

http://www.national.com 22
 This mode is selected by setting SSEL bit in the ENUI regis-
Associated I/O Pins ter. The input frequency to the UART is the same as the
Data is transmitted on the TDX pin and received on the RDX baud rate.
pin. TDX is the alternate function assigned to Port L pin L2;
When an external clock input is selected at the CKX pin,
it is selected by setting ETDX (in the ENUI register) to one.
data transmit and receive are performed synchronously with
RDX is an inherent function of Port L pin L3, requiring no
this clock through TDX/RDX pins.
setup.
If data transmit and receive are selected with the CKX pin
The baud rate clock for the UART can be generated on-
as clock output, the mC generates the synchronous clock
chip, or can be taken from an external source. Port L pin L1
output at the CKX pin. The internal baud rate generator is
(CKX) is the external clock I/O pin. The CKX pin can be
used to produce the synchronous clock. Data transmit and
either an input or an output, as determined by Port L Config-
receive are performed synchronously with this clock.
uration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter FRAMING FORMATS
and/or receiver. As an output, it presents the internal Baud The UART supports several serial framing formats (Figure
Rate Generator output. 13). The format is selected using control bits in the ENU,
ENUR and ENUI registers.
UART Operation The first format (1, 1a, 1b, 1c) for data transmission (CHL0
The UART has two modes of operation: asynchronous e 1, CHL1 e 0) consists of Start bit, seven Data bits (ex-
mode and synchronous mode. cluding parity) and 7/8, one or two Stop bits. In applications
using parity, the parity bit is generated and verified by hard-
ASYNCHRONOUS MODE
ware.
This mode is selected by resetting the SSEL (in the ENUI
The second format (CHL0 e 0, CHL1 e 0) consists of one
register) bit to zero. The input frequency to the UART is 16
times the baud rate. Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hard-
The TSFT and TBUF registers double-buffer data for trans- ware.
mission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software The third format for transmission (CHL0 e 0, CHL1 e 1)
with the next byte to be transmitted. When TSFT finishes consists of one Start bit, nine Data bits and 7/8, one or two
transmitting the current character the contents of TBUF are Stop bits. This format also supports the UART ‘‘ATTEN-
transferred to the TSFT register and the Transmit Buffer TION’’ feature. When operating in this format, all eight bits
Empty Flag (TBMT in the ENU register) is set. The TBMT of TBUF and RBUF are used for data. The ninth data bit is
flag is automatically reset by the UART when software loads transmitted and received using two bits in the ENU and
a new character into the TBUF register. There is also the ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
XMTG bit which is set to indicate that the UART is transmit- only bit. Parity is not generated or verified in this mode.
ting. This bit gets reset at the end of the last frame (end of For any of the above framing formats, the last Stop bit can
last Stop bit). TBUF is a read/write register. be programmed to be 7/8th of a bit in length. If two Stop
The RSFT and RBUF registers double-buffer data being re- bits are selected and the 7/8th bit is set (selected), the
ceived. The UART receiver continually monitors the signal second Stop bit will be 7/8th of a bit in length.
on the RDX pin for a low level to detect the beginning of a The parity is enabled/disabled by PEN bit located in the
Start bit. Upon sensing this low level, it waits for half a bit ENU register. Parity is selected for 7- and 8-bit modes only.
time and samples again. If the RDX pin is still low, the re- If parity is enabled (PEN e 1), the parity selection is then
ceiver considers this to be a valid Start bit, and the remain- performed by PSEL0 and PSEL1 bits located in the ENU
ing bits in the character frame are each sampled a single register.
time, at the mid-bit position. Serial data input on the RDX pin Note that the XBIT9/PSEL0 bit located in the ENU register
is shifted into the RSFT register. Upon receiving the com- serves two mutually exclusive functions. This bit programs
plete character, the contents of the RSFT register are cop- the ninth bit for transmission when the UART is operating
ied into the RBUF register and the Received Buffer Full Flag with nine data bits per frame. There is no parity selection in
(RBFL) is set. RBFL is automatically reset when software this framing format. For other framing formats XBIT9 is not
reads the character from the RBUF register. RBUF is a read needed and the bit is PSEL0 used in conjunction with
only register. There is also the RCVG bit which is set high PSEL1 to select parity.
when a framing error occurs and goes low once RDX goes The frame formats for the receiver differ from the transmit-
high. TBMT, XMTG, RBFL and RCVG are read only bits. ter in the number of Stop bits required. The receiver only
SYNCHRONOUS MODE requires one Stop bit in a frame, regardless of the setting of
the Stop bit selection bits in the control register. Note that
In this mode data is transferred synchronously with the
an implicit assumption is made for full duplex UART opera-
clock. Data is transmitted on the rising edge and received
tion that the framing formats are the same for the transmit-
on the falling edge of the synchronous clock.
ter and receiver.

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 UART Operation (Continued)

TL/DD/10830 – 17
FIGURE 13. Framing Formats

UART INTERRUPTS source selected in the PSR and BAUD registers. Internally,
The UART is capable of generating interrupts. Interrupts are the basic baud clock is created from the oscillator frequency
generated on Receive Buffer Full and Transmit Buffer Emp- through a two-stage divider chain consisting of a 1 – 16 (in-
ty. Both interrupts have individual interrupt vectors. Two crements of 0.5) prescaler and an 11-bit binary counter.
bytes of program memory space are reserved for each inter- (Figure 14) The divide factors are specified through two
rupt vector. The two vectors are located at addresses 0xEC read/write registers shown in Figure 15 . Note that the 11-bit
to 0xEF Hex in the program memory space. The interrupts Baud Rate Divisor spills over into the Prescaler Select Reg-
can be individually enabled or disabled using Enable Trans- ister (PSR). PSR is cleared upon reset.
mit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in As shown in Table I, a Prescaler Factor of 0 corresponds to
the ENUI register. NO CLOCK. NO CLOCK condition is the UART power down
The interrupt from the Transmitter is set pending, and re- mode where the UART clock is turned off for power saving
mains pending, as long as both the TBMT and ETI bits are purpose. The user must also turn the UART clock off when
set. To remove this interrupt, software must either clear the a different baud rate is chosen.
ETI bit or write to the TBUF register (thus clearing the TBMT The correspondences between the 5-bit Prescaler Select
bit). and Prescaler factors are shown in Table I. Therer are many
The interrupt from the receiver is set pending, and remains ways to calculate the two divisor factors, but one particularly
pending, as long as both the RBFL and ERI bits are set. To effective method would be to achieve a 1.8432 MHz fre-
remove this interrupt, software must either clear the ERI bit quency coming out of the first stage. The 1.8432 MHz pre-
or read from the RBUF register (thus clearing the RBFL bit). scaler output is then used to drive the software programma-
ble baud rate counter to create a x16 clock for the following
baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
Baud Clock Generation 3600, 4800, 7200, 9600, 19200 and 38400 (Table II). Other
The clock inputs to the transmitter and receiver sections of baud rates may be created by using appropriate divisors.
the UART can be individually selected to come either from The x16 clock is then divided by 16 to provide the rate for
an external source at the CKX pin (port L, pin L1) or from a the serial shift registers of the transmitter and receiver.

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Baud Clock Generation (Continued)

TL/DD/10830 – 18
FIGURE 14. UART BAUD Clock Generation

TL/DD/10830 – 19
FIGURE 15. UART BAUD Clock Divisor Registers

TABLE I. Prescaler Factors TABLE II. Baud Rate Divisors

(1.8432 MHz Prescaler Output)
Prescaler Prescaler
Select Factor Baud Baud Rate
Rate Divisor b 1 (N-1)
00000 NO CLOCK
00001 1 110 (110.03) 1046
00010 1.5 134.5 (134.58) 855
00011 2 150 767
00100 2.5 300 383
00101 3 600 191
00110 3.5 1200 95
00111 4 1800 63
01000 4.5 2400 47
01001 5 3600 31
01010 5.5 4800 23
01011 6 7200 15
01100 6.5 9600 11
01101 7 19200 5
01110 7.5 38400 2
01111 8 The entries in Table II assume a prescaler output
10000 8.5 of 1.8432 MHz. In the asynchronous mode the
baud rate could be as high as 625k.
10001 9
10010 9.5 As an example, considering the Asynchronous Mode and a
10011 10 CKI clock of 4.608 MHz, the prescaler factor selected is:
10100 10.5 4.608/1.8432 e 2.5
10101 11 The 2.5 entry is available in Table I. The 1.8432 MHz pre-
10110 11.5 scaler output is then used with proper Baud Rate Divisor
10111 12 (Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
11000 12.5
11001 13 N b 1 e 5 (N b 1 is the value from Table II)
11010 13.5 N e 6 (N is the Baud Rate Divisor)
11011 14 Baud Rate e 1.8432 MHz/(16 c 6) e 19200
11100 14.5 The divide by 16 is performed because in the asynchronous
11101 15 mode, the input frequency to the UART is 16 times the baud
11110 15.5 rate. The equation to calculate baud rates is given below.
11111 16 The actual Baud Rate may be found from:
BR e Fc/(16 c N c P)

25 http://www.national.com
 ter is ‘‘looped back’’ into the Receive Shift Register input. In
Baud Clock Generation (Continued) this mode, data that is transmitted is immediately received.
Where: This feature allows the processor to verify the transmit and
BR is the Baud Rate receive data paths of the UART.
Fc is the CKI frequency Note that the framing format for this mode is the nine bit
N is the Baud Rate Divisor (Table II). format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)
Note: In the Synchronous Mode, the divisor 16 is replaced by two if internal Attention Mode
Baud Rate generator is used. Replaced by one if external clock is The UART Receiver section supports an alternate mode of
used. operation, referred to as ATTENTION Mode. This mode of
Example: operation is selected by the ATTN bit in the ENUR register.
Asynchronous Mode: The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
Crystal Frequency e 5 MHz
The ATTENTION mode of operation is intended for use in
Desired baud rate e 9600
networking the COP888CS with other processors. Typically
Using the above equation N c P can be calculated first. in such environments the messages consists of device ad-
N c P e (5 c 106)/(16 c 9600) e 32.552 dresses, indicating which of several destinations should re-
Now 32.552 is divided by each Prescaler Factor (Table II) to ceive them, and the actual data. This Mode supports a
obtain a value closest to an integer. This factor happens to scheme in which addresses are flagged by having the ninth
be 6.5 (P e 6.5). bit of the data field set to a 1. If the ninth bit is reset to a
N e 32.552/6.5 e 5.008 (N e 5) zero the byte is a Data byte.
The programmed value (from Table II) should be 4 (N b 1). While in ATTENTION mode, the UART monitors the com-
munication flow, but ignores all characters until an address
Using the above values calculated for N and P: character is received. Upon receiving an address character,
BR e (5 c 106)/(16 c 5 c 6.5) e 9615.384 the UART signals that the character is ready by setting the
% error e (9615.385 b 9600)/9600 e 0.16 RBFL flag, which in turn interrupts the processor if UART
Receiver interrupts are enabled. The ATTN bit is also
Effect of HALT/IDLE cleared automatically at this point, so that data characters
as well as address characters are recognized. Software ex-
The UART logic is reinitialized when either the HALT or
amines the contents of the RBUF and responds by deciding
IDLE modes are entered. This reinitialization sets the TBMT
either to accept the subsequent data stream (by leaving the
flag and resets all read only bits in the UART control and
ATTN bit reset) or to wait until the next address character is
status registers. Read/Write bits remain unchanged. The
seen (by setting the ATTN bit again).
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver regis- Operation of the UART Transmitter is not affected by selec-
ters RBUF and RSFT are not affected. tion of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
The mC will exit from the HALT/IDLE modes when the Start
the ninth bit received is obtained by reading RBIT9. Since
bit of a character is detected at the RDX (L3) pin. This fea-
this bit is located in ENUR register where the error flags
ture is obtained by using the Multi-Input Wakeup scheme
reside, a bit operation on it will reset the error flags.
provided on the mC.
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
Comparator
selection is done by setting bit 3 of WKEN (Wakeup Enable) The device contains one differential comparator, with a pair
register. The Wakeup trigger condition is then selected to of inputs (positive and negative) and an output. Ports I1 – I3
be high to low transition. This is done via the WKEDG regis- are used for the comparator. The following is the Port I as-
ter (Bit 3 is zero.) signment:
If the microcontroller is halted and crystal oscillator is used, I1 Comparator1 negative input
the Wakeup signal will not start the chip running immediate- I2 Comparator1 positive input
ly because of the finite start up time requirement of the crys- I3 Comparator1 output
tal oscillator. The idle timer (T0) generates a fixed delay to A Comparator Select Register (CMPSL) is used to enable
ensure that the oscillator has indeed stabilized before allow- the comparators, read the outputs of the comparator inter-
ing the mC to execute code. The user has to consider this nally, and enable the output of the comparator to the pins.
delay when data transfer is expected immediately after exit- Two control bits (enable and output enable) and one result
ing the HALT mode. bit are associated with the comparator. The comparator re-
sult bit (CMP1RD) is read only bit which will read as zero if
Diagnostic the comparator is not enabled. The Comparator Select Reg-
ister is cleared with reset, resulting in the comparator being
Bits CHARL0 and CHARL1 in the ENU register provide a
disabled. The comparator should also be disabled before
loopback feature for diagnostic testing of the UART. When
entering either the HALT or IDLE modes in order to save
these bits are set to one, the following occur: The receiver
power. The configuration of the CMPSL register is as fol-
input pin (RDX) is internally connected to the transmitter
lows:
output pin (TDX); the output of the Transmitter Shift Regis-

http://www.national.com 26
 The interruption process is accomplished with the INTR in-
Comparator (Continued) struction (opcode 00), which is jammed inside the Instruc-
CMPSL REGISTER (ADDRESS X’00B7) tion Register and replaces the opcode about to be execut-
The CMPSL register contains the following bits: ed. The following steps are performed for every interrupt:
CMP1EN Enable comparator 1 1. The GIE (Global Interrupt Enable) bit is reset.
CMP1RD Comparator 1 result (this is a read only bit, 2. The address of the instruction about to be executed is
which will read as 0 if the comparator is not pushed into the stack.
enabled) 3. The PC (Program Counter) branches to address 00FF.
CMP10E Selects pin I3 as comparator 1 output provided This procedure takes 7 tc cycles to execute.
that CMPIEN is set to enable the comparator At this time, since GIE e 0, other maskable interrupts are
disabled. The user is now free to do whatever context
Unused Unused Unused Unused CMP10E CMP1RD CMP1EN Unused switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then pro-
Bit 7 Bit 0
gram a VIS (Vector Interrupt Select) instruction in order to
Comparator outputs have the same spec as Ports L and G branch to the interrupt service routine of the highest priority
except that the rise and fall times are symmetrical. interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
Interrupts branch to address location 00FF Hex prior to the context
The device supports a vectored interrupt scheme. It sup- switching.
ports a total of fourteen interrupt sources. The following ta- Thus, if an interrupt with a higher rank than the one which
ble lists all the possible interrupt sources, their arbitration caused the interruption becomes active before the decision
ranking and the memory locations reserved for the interrupt of which interrupt to service is made by the VIS, then the
vector for each source. interrupt with the higher rank will override any lower ones
Two bytes of program memory space are reserved for each and will be acknowledged. The lower priority interrupt(s) are
interrupt source. All interrupt sources except the software still pending, however, and will cause another interrupt im-
interrupt are maskable. Each of the maskable interrupts mediately following the completion of the interrupt service
have an Enable bit and a Pending bit. A maskable interrupt routine associated with the higher priority interrupt just serv-
is active if its associated enable and pending bits are set. If iced. This lower priority interrupt will occur immediately fol-
GIE e 1 and an interrupt is active, then the processor will lowing the RETI (Return from Interrupt) instruction at the
be interrupted as soon as it is ready to start executing an end of the interrupt service routine just completed.
instruction except if the above conditions happen during the Inside the interrupt service routine, the associated pending
Software Trap service routine. This exception is described bit has to be cleared by software. The RETI (Return from
in the Software Trap sub-section. Interrupt) instruction at the end of the interrupt service rou-

Vector
Arbitration
Source Description Address
Ranking
Hi-Low Byte
(1) Highest Software INTR Instruction 0yFE – 0yFF
Reserved for Future Use 0yFC – 0yFD
(2) External Pin G0 Edge 0yFA – 0yFB
(3) Timer T0 Underflow 0yF8 – 0yF9
(4) Timer T1 T1A/Underflow 0yF6 – 0yF7
(5) Timer T1 T1B 0yF4 – 0yF5
(6) MICROWIRE/PLUS BUSY Goes Low 0yF2 – 0yF3
Reserved for Future Use 0yF0 – 0yF1
(7) UART Receive 0yEE – 0yEF
(8) UART Transmit 0yEC – 0yED
(9) Reserved 0yEA – 0yEB
(10) Reserved 0yE8 – 0yE9
(11) Reserved 0yE6 – 0yE7
(12) Reserved 0yE4 – 0yE5
(13) Port L/Wakeup Port L Edge 0yE2 – 0yE3
(14) Lowest Default VIS Instr. Execution 0yE0 – 0yE1
without Any Interrupts
y is VIS page, y i 0.

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 Interrupts (Continued)
tine will set the GIE (Global Interrupt Enable) bit, allowing If, by accident, a VIS gets executed and no interrupt is ac-
the processor to be interrupted again if another interrupt is tive, then the PC (Program Counter) will branch to a vector
active and pending. located at 0yE0 – 0yE1.
The VIS instruction looks at all the active interrupts at the WARNING
time it is executed and performs an indirect jump to the A Default VIS interrupt handler routine must be present. As
beginning of the service routine of the one with the highest a minimum, this handler should confirm that the GIE bit is
rank. cleared (this indicates that the interrupt sequence has been
The addresses of the different interrupt service routines, taken), take care of any required housekeeping, restore
called vectors, are chosen by the user and stored in ROM in context and return. Some sort of Warm Restart procedure
a table starting at 01E0 (assuming that VIS is located be- should be implemented. These events can occur without
tween 00FF and 01DF). The vectors are 15-bit wide and any error on the part of the system designer or programmer.
therefore occupy 2 ROM locations. Note: There is always the possibility of an interrupt occurring during an
instruction which is attempting to reset the GIE bit or any other inter-
VIS and the vector table must be located in the same 256-
rupt enable bit. If this occurs when a single cycle instruction is being
byte block (0y00 to 0yFF) except if VIS is located at the last used to reset the interrupt enable bit, the interrupt enable bit will be
address of a block. In this case, the table must be in the reset but an interrupt may still occur. This is because interrupt pro-
next block. The vector table cannot be inserted in the first cessing is started at the same time as the interrupt bit is being reset.
256-byte block (y i 0). To avoid this scenario, the user should always use a two, three, or
four cycle instruction to reset interrupt enable bits.
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte) Figure 16 shows the Interrupt block diagram.
and so forth in increasing rank number. The vector of the SOFTWARE TRAP
maskable interrupt with the highest rank is located at 0yFA The Software Trap (ST) is a special kind of non-maskable
(Hi-Order byte) and 0yFB (Lo-Order byte). interrupt which occurs when the INTR instruction (used to
The Software Trap has the highest rank and its vector is acknowledge interrupts) is fetched from ROM and placed
located at 0yFE and 0yFF. inside the instruction register. This may happen when the
If, by accident, a VIS gets executed and no interrupt is ac- PC is pointing beyond the available ROM address space or
tive, then the PC (Program Counter) will branch to a vector when the stack is over-popped.
located at 0yE0 – 0yE1. This vector can point to the Soft-
ware Trap (ST) interrupt service routine, or to another spe-
cial service routine as desired.

TL/DD/10830 – 20

FIGURE 16. Interrupt Block Diagram

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Interrupts (Continued)
When an ST occurs, the user can re-initialize the stack The lower limit of the service window is fixed at 2048 in-
pointer and do a recovery procedure (similar to reset, but struction cycles. Bits 7 and 6 of the WDSVR register allow
not necessarily containing all of the same initialization pro- the user to pick an upper limit of the service window.
cedures) before restarting. Table IV shows the four possible combinations of lower and
The occurrence of an ST is latched into the ST pending bit. upper limits for the WATCHDOG service window. This flexi-
The GIE bit is not affected and the ST pending bit (not bility in choosing the WATCHDOG service window prevents
accessible by the user) is used to inhibit other interrupts any undue burden on the user software.
and to direct the program to the ST service routine with the Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-
VIS instruction. The RPND instruction is used to clear the bit Key Data field. The key data is fixed at 01100. Bit 0 of the
software interrupt pending bit. This pending bit is also WDSVR Register is the Clock Monitor Select bit.
cleared on reset.
The ST has the highest rank among all interrupts. TABLE III. WATCHDOG Service Register (WDSVR)
Nothing (except another ST) can interrupt an ST being Window Clock
serviced. Key Data
Select Monitor

WATCHDOG X X 0 1 1 0 0 Y
The device contains a WATCHDOG and clock monitor. The 7 6 5 4 3 2 1 0
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or TABLE IV. WATCHDOG Service Window Select
‘‘runaway’’ programs. The Clock Monitor is used to detect
WDSVR WDSVR Service Window
the absence of a clock or a very slow clock below a speci-
Bit 7 Bit 6 (Lower-Upper Limits)
fied rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks: 0 0 2k –8k tc Cycles
WD UPPER and WD LOWER. WD UPPER establishes the 0 1 2k – 16k tc Cycles
upper limit on the service window and WD LOWER defines 1 0 2k – 32k tc Cycles
the lower limit of the service window. 1 1 2k – 64k tc Cycles
Servicing the WATCHDOG consists of writing a specific val-
ue to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
Clock Monitor
posed of three fields, consisting of a 2-bit Window Select, a The Clock Monitor aboard the device can be selected or
5-bit Key Data field, and the 1-bit Clock Monitor Select field. deselected under program control. The Clock Monitor is
Table III shows the WDSVR register. guaranteed not to reject the clock if the instruction cycle
clock (1/tc) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.

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 WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during until the clock frequency has reached the minimum speci-
reset. The device comes out of reset with the WATCHDOG fied value, after which the G1 output will enter the high im-
armed, the WATCHDOG Window Select bits (bits 6, 7 of the pedance TRI-STATE mode following 16 tc –32 tc clock cy-
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the cles. The Clock Monitor generates a continual Clock Moni-
WDSVR Register) enabled. Thus, a Clock Monitor error will tor error if the oscillator fails to start, or fails to reach the
occur after coming out of reset, if the instruction cycle clock minimum specified frequency. The specification for the
frequency has not reached a minimum specified value, in- Clock Monitor is as follows:
cluding the case where the oscillator fails to start. 1/tc l 10 kHzÐNo clock rejection.
The WDSVR register can be written to only once after reset 1/tc k 10 HzÐGuaranteed clock rejection.
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR WATCHDOG AND CLOCK MONITOR SUMMARY
register involves two irrevocable choices: (i) the selection of The following salient points regarding the device WATCH-
the WATCHDOG service window (ii) enabling or disabling of DOG and CLOCK MONITOR should be noted:
the Clock Monitor. Hence, the first write to WDSVR Register # Both the WATCHDOG and Clock Monitor detector cir-
involves selecting or deselecting the Clock Monitor, select cuits are inhibited during RESET.
the WATCHDOG service window and match the WATCH-
# Following RESET, the WATCHDOG and CLOCK MONI-
DOG key data. Subsequent writes to the WDSVR register
TOR are both enabled, with the WATCHDOG having the
will compare the value being written by the user to the
maximum service window selected.
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table V shows the se- # The WATCHDOG service window and Clock Monitor
quence of events that can occur. enable/disable option can only be changed once, during
the initial WATCHDOG service following RESET.
The user must service the WATCHDOG at least once be-
fore the upper limit of the service window expires. The # The initial WATCHDOG service must match the key data
WATCHDOG may not be serviced more than once in every value in the WATCHDOG Service register WDSVR in or-
lower limit of the service window. The user may service the der to avoid a WATCHDOG error.
WATCHDOG as many times as wished in the time period # Subsequent WATCHDOG services must match all three
between the lower and upper limits of the service window. data fields in WDSVR in order to avoid WATCHDOG er-
The first write to the WDSVR Register is also counted as a rors.
WATCHDOG service. # The correct key data value cannot be read from the
The WATCHDOG has an output pin associated with it. This WATCHDOG Service register WDSVR. Any attempt to
is the WDOUT pin, on pin 1 of the port G. WDOUT is active read this key data value of 01100 from WDSVR will read
low. The WDOUT pin is in the high impedance state in the as key data value of all 0’s.
inactive state. Upon triggering the WATCHDOG, the logic # The WATCHDOG detector circuit is inhibited during both
will pull the WDOUT (G1) pin low for an additional the HALT and IDLE modes.
16 tc – 32 tc cycles after the signal level on WDOUT pin goes
# The Clock Monitor detector circuit is active during both
below the lower Schmitt trigger threshold. After this delay, the HALT and IDLE modes. Consequently, the device
the device will stop forcing the WDOUT output low. inadvertently entering the HALT mode wil be detected as
The WATCHDOG service window will restart when the a Clock Monitor error (provided that the Clock Monitor
WDOUT pin goes high. It is recommended that the user tie enable option has been selected by the program).
the WDOUT pin back to VCC through a resistor in order to
# With the single-pin R/C oscillator mask option selected
pull WDOUT high.
and the CLKDLY bit reset, the WATCHDOG service win-
A WATCHDOG service while the WDOUT signal is active dow will resume following HALT mode from where it left
will be ignored. The state of the WDOUT pin is not guaran- off before entering the HALT mode.
teed on reset, but if it powers up low then the WATCHDOG
# With the crystal oscillator mask option selected, or with
will time out and WDOUT will enter high impedance state.
the single-pin R/C oscillator mask option selected and
The Clock Monitor forces the G1 pin low upon detecting a the CLKDLY bit set, the WATCHDOG service window will
clock frequency error. The Clock Monitor error will continue

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 Thus, the chip can detect the following illegal conditions:
WATCHDOG Operation (Continued)
a. Executing from undefined ROM
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced b. Over ‘‘POP’’ing the stack by having more returns than
for at least 2048 instruction cycles following HALT, but calls.
must be serviced within the selected window to avoid a When the software interrupt occurs, the user can re-initialize
WATCHDOG error. the stack pointer and do a recovery procedure before re-
# The IDLE timer T0 is not initialized with RESET. starting (this recovery program is probably similar to that
# The user can sync in to the IDLE counter cycle with an following reset, but might not contain the same program
IDLE counter (T0) interrupt or by monitoring the T0PND initialization procedures). The recovery program should re-
flag. The T0PND flag is set whenever the thirteenth bit of set the software interrupt pending bit using the RPND in-
the IDLE counter toggles (every 4096 instruction cycles). struction.
The user is responsible for resetting the T0PND flag.
# A hardware WATCHDOG service occurs just as the de-
MICROWIRE/PLUS
vice exits the IDLE mode. Consequently, the WATCH- MICROWIRE/PLUS is a serial synchronous communica-
DOG should not be serviced for at least 2048 instruction tions interface. The MICROWIRE/PLUS capability enables
cycles following IDLE, but must be serviced within the the device to interface with any of National Semiconductor’s
selected window to avoid a WATCHDOG error. MICROWIRE peripherals (i.e. A/D converters, display driv-
ers, E2PROMs etc.) and with other microcontrollers which
# Following RESET, the initial WATCHDOG service (where
support the MICROWIRE interface. It consists of an 8-bit
the service window and the CLOCK MONITOR ena-
serial shift register (SIO) with serial data input (SI), serial
ble/disable must be selected) may be programmed any-
data output (SO) and serial shift clock (SK). Figure 17
where within the maximum service window (65,536 in-
shows a block diagram of the MICROWIRE/PLUS logic.
struction cycles) initialized by RESET. Note that this ini-
tial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCH-
DOG error.

Detection of Illegal Conditions

The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for soft-
ware interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to TL/DD/10830 – 21
subroutine), interrupt, or PUSH, and grows up for each re- FIGURE 17. MICROWIRE/PLUS Block Diagram
turn or POP. The stack pointer is initialized to RAM location The shift clock can be selected from either an internal
06F Hex during reset. Consequently, if there are more re- source or an external source. Operating the MICROWIRE/
turns than calls, the stack pointer will point to addresses PLUS arrangement with the internal clock source is called
070 and 071 Hex (which are undefined RAM). Undefined the Master mode of operation. Similarly, operating the
RAM from addresses 070 to 07F (Segment 0), 140 to 17F MICROWIRE/PLUS arrangement with an external shift
(Segment 1), and all other segments (i.e., Segments 3 . . . clock is called the Slave mode of operation.
etc.) is read as all 1’s, which in turn will cause the program The CNTRL register is used to configure and control the
to return to address 7FFF Hex. This is an undefined ROM MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
location and the instruction fetched (all 0’s) from this loca- the MSEL bit in the CNTRL register is set to one. In the
tion will generate a software interrupt signaling an illegal master mode, the SK clock rate is selected by the two bits,
condition. SL0 and SL1, in the CNTRL register. Table VI details the
different clock rates that may be selected.

TABLE V. WATCHDOG Service Actions

Key Window Clock
Action
Data Data Monitor
Match Match Match Valid Service: Restart Service Window
Don’t Care Mismatch Don’t Care Error: Generate WATCHDOG Output
Mismatch Don’t Care Don’t Care Error: Generate WATCHDOG Output
Don’t Care Don’t Care Mismatch Error: Generate WATCHDOG Output

TABLE VI. MICROWIRE/PLUS

Master Mode Clock Select
SL1 SL0 SK
0 0 2 c tc Where tc is the
0 1 4 c tc instruction cycle clock
1 x 8 c tc

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 MICROWIRE/PLUS (Continued)
MICROWIRE/PLUS OPERATION The user must set the BUSY flag immediately upon entering
Setting the BUSY bit in the PSW register causes the MI- the Slave mode. This will ensure that all data bits sent by
CROWIRE/PLUS to start shifting the data. It gets reset the Master will be shifted properly. After eight clock pulses
when eight data bits have been shifted. The user may reset the BUSY flag will be cleared and the sequence may be
the BUSY bit by software to allow less than 8 bits to shift. If repeated.
enabled, an interrupt is generated when eight data bits have Alternate SK Phase Operation
been shifted. The device may enter the MICROWIRE/PLUS
The device allows either the normal SK clock or an alternate
mode either as a Master or as a Slave. Figure 14 shows
phase SK clock to shift data in and out of the SIO register.
how two COP888CS microcontrollers and several peripher-
In both the modes the SK is normally low. In the normal
als may be interconnected using the MICROWIRE/PLUS
mode data is shifted in on the rising edge of the SK clock
arrangements.
and the data is shifted out on the falling edge of the SK
Warning: clock. The SIO register is shifted on each falling edge of the
The SIO register should only be loaded when the SK clock SK clock in the normal mode. In the alternate SK phase
is low. Loading the SIO register while the SK clock is high operation, data is shifted in on the falling edge of the SK
will result in undefined data in the SIO register. SK clock is clock and shifted out on the rising edge of the SK clock.
normally low when not shifting. A control flag, SKSEL, allows either the normal SK clock or
Setting the BUSY flag when the input SK clock is high in the the alternate SK clock to be selected. Resetting SKSEL
MICROWIRE/PLUS slave mode may cause the current SK causes the MICROWIRE/PLUS logic to be clocked from the
clock for the SIO shift register to be narrow. For safety, the normal SK signal. Setting the SKSEL flag selects the alter-
BUSY flag should only be set when the input SK clock is nate SK clock. The SKSEL is mapped into the G6 configura-
low. tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the TABLE VII
shift clock (SK) is generated internally. The MICROWIRE This table assumes that the control flag MSEL is set.
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO G4 (SO) G5 (SK) G4 G5
Operation
and SK functions onto the G Port. The SO and SK pins must Config. Bit Config. Bit Fun. Fun.
also be selected as outputs by setting appropriate bits in the 1 1 SO Int. MICROWIRE/PLUS
Port G configuration register. Table VII summarizes the bit
SK Master
settings required for Master mode of operation.
0 1 TRI- Int. MICROWIRE/PLUS
MICROWIRE/PLUS Slave Mode Operation
STATE SK Master
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL 1 0 SO Ext. MICROWIRE/PLUS
bit in the CNTRL register enables the SO and SK functions SK Slave
onto the G Port. The SK pin must be selected as an input
0 0 TRI- Ext. MICROWIRE/PLUS
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration reg- STATE SK Slave
ister. Table VII summarizes the settings required to enter
the Slave mode of operation.

TL/DD/10830 – 22
FIGURE 18. MICROWIRE/PLUS Application

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Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.

Address Address
Contents Contents
S/ADD REG S/ADD REG
0000 to 006F On-Chip RAM bytes (112 bytes) xxD0 Port L Data Register
xxD1 Port L Configuration Register
0070 to 007F Unused RAM Address Space (Reads
As All Ones) xxD2 Port L Input Pins (Read Only)
xx80 to xxAF Unused RAM Address Space (Reads xxD3 Reserved for Port L
Undefined Data) xxD4 Port G Data Register
xxD5 Port G Configuration Register
xxB0 to xxB6 Reserved
xxD6 Port G Input Pins (Read Only)
xxB7 Comparator Select Register (CMPSL)
xxD7 Port I Input Pins (Read Only)
xxB8 UART Transmit Buffer (TBUF)
xxD8 Port C Data Register
xxB9 UART Receive Buffer (RBUF)
xxD9 Port C Configuration Register
xxBA UART Control and Status Register
xxDA Port C Input Pins (Read Only)
(ENU)
xxDB Reserved for Port C
xxBB UART Receive Control and Status
Register (ENUR) xxDC Port D
xxBC UART Interrupt and Clock Source xxDD to DF Reserved for Port D
Register (ENUI) xxE0 to xxE5 Reserved for EE Control Registers
xxBD UART Baud Register (BAUD) xxE6 Timer T1 Autoload Register T1RB
xxBE UART Prescale Select Register (PSR) Lower Byte
xxBF Reserved for UART xxE7 Timer T1 Autoload Register T1RB
Upper Byte
xxC0 to xxC6 Reserved
xxE8 ICNTRL Register
xxC7 WATCHDOG Service Register
(Reg:WDSVR) xxE9 MICROWIRE/PLUS Shift Register
xxC8 MIWU Edge Select Register xxEA Timer T1 Lower Byte
(Reg:WKEDG) xxEB Timer T1 Upper Byte
xxC9 MIWU Enable Register (Reg:WKEN) xxEC Timer T1 Autoload Register T1RA
xxCA MIWU Pending Register Lower Byte
(Reg:WKPND) xxED Timer T1 Autoload Register T1RA
xxCB Reserved Upper Byte
xxCC Reserved xxEE CNTRL Control Register
xxCD to xxCF Reserved xxEF PSW Register
xxF0 to FB On-Chip RAM Mapped as Registers
xxFC X Register
xxFD SP Register
xxFE B Register
xxFF S Register
0100 – 013F On-Chip RAM Bytes (64 bytes)
Reading memory locations 0070H–007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H–00AFH (Segment 0) will return
undefined data. Reading unused memory locations 0140–017F (Segment 1)
will return all ones. Reading memory locations from other Segments (i.e.,
Segment 2, Segment 3, ... etc.) will return all ones.
All reserved location reads undefined data.

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 Addressing Modes
The device has ten addressing modes, six for operand ad- Indirect
dressing and four for transfer of control. This mode is used with the JID instruction. The contents of
OPERAND ADDRESSING MODES the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
Register Indirect
contents of this program memory location serve as a partial
This is the ‘‘normal’’ addressing mode. The operand is the address (lower 8 bits of PC) for the jump to the next instruc-
data memory addressed by the B pointer or X pointer. tion.
Register Indirect (with auto post increment or Note: The VIS is a special case of the Indirect Transfer of Control address-
decrement of pointer) ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
This addressing mode is used with the LD and X instruc- the program counter (PC) in order to jump to the associated interrupt
tions. The operand is the data memory addressed by the B service routine.
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X reg- Instruction Set
ister after executing the instruction.
Direct Register and Symbol Definition
The instruction contains an 8-bit address field that directly Registers
points to the data memory for the operand.
A 8-Bit Accumulator Register
Immediate
B 8-Bit Address Register
The instruction contains an 8-bit immediate field as the op-
X 8-Bit Address Register
erand.
SP 8-Bit Stack Pointer Register
Short Immediate
PC 15-Bit Program Counter Register
This addressing mode is used with the Load B Immediate PU Upper 7 Bits of PC
instruction. The instruction contains a 4-bit immediate field
PL Lower 8 Bits of PC
as the operand.
C 1 Bit of PSW Register for Carry
Indirect
HC 1 Bit of PSW Register for Half Carry
This addressing mode is used with the LAID instruction. The GIE 1 Bit of PSW Register for Global
contents of the accumulator are used as a partial address Interrupt Enable
(lower 8 bits of PC) for accessing a data operand from the
VU Interrupt Vector Upper Byte
program memory.
VL Interrupt Vector Lower Byte
TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new [B] Memory Indirectly Addressed by B
program location. JP has a range from b31 to a 32 to allow Register
a 1-byte relative jump (JP a 1 is implemented by a NOP [X] Memory Indirectly Addressed by X
instruction). There are no ‘‘pages’’ when using JP, since all Register
15 bits of PC are used. MD Direct Addressed Memory
Absolute Mem Direct Addressed Memory or [B]
This mode is used with the JMP and JSR instructions, with Meml Direct Addressed Memory or [B] or
the instruction field of 12 bits replacing the lower 12 bits of Immediate Data
the program counter (PC). This allows jumping to any loca- Imm 8-Bit Immediate Data
tion in the current 4k program memory segment. Reg Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Absolute Long
Bit Bit Number (0 to 7)
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
w Loaded with
bits of the program counter (PC). This allows jumping to any Ý Exchanged with
location in the current 4k program memory space.

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Instruction Set (Continued)
INSTRUCTION SET

ADD A,Meml ADD A w A a Meml

ADC A,Meml ADD with Carry A w A a Meml a C, C w Carry
HC w Half Carry
SUBC A,Meml Subtract with Carry A w A b MemI a C, C w Carry
HC w Half Carry
AND A,Meml Logical AND A w A and Meml
ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm) e 0
OR A,Meml Logical OR A w A or Meml
XOR A,Meml Logical EXclusive OR A w A xor Meml
IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD e Imm
IFEQ A,Meml IF EQual Compare A and Meml, Do next if A e Meml
IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A i Meml
IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A l Meml
IFBNE Ý If B Not Equal Do next if lower 4 bits of B i Imm
DRSZ Reg Decrement Reg., Skip if Zero Reg w Reg b 1, Skip if Reg e 0
SBIT Ý,Mem Set BIT 1 to bit, Mem (bit e 0 to 7 immediate)
RBIT Ý,Mem Reset BIT 0 to bit, Mem
IFBIT Ý,Mem IF BIT If bit in A or Mem is true do next instruction
RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag
X A,Mem EXchange A with Memory A Ý Mem
LD A,Meml LoaD A with Memory A w Meml
LD B,Imm LoaD B with Immed. B w Imm
LD Mem,Imm LoaD Memory Immed Mem w Imm
LD Reg,Imm LoaD Register Memory Immed. Reg w Imm
X A, [B g ] EXchange A with Memory [B] A Ý [B], (B w B g 1)
X A, [X g ] EXchange A with Memory [X] A Ý [X], (X w g 1)
LD A, [B g ] LoaD A with Memory [B] A w [B], (B w B g 1)
LD A, [X g ] LoaD A with Memory [X] A w [X], (X w X g 1)
LD [B g ],Imm LoaD Memory [B] Immed. [B] w Imm, (B w B g 1)
CLR A CLeaR A Aw0
INC A INCrement A AwA a 1
DEC A DECrementA AwA b 1
LAID Load A InDirect from ROM A w ROM (PU,A)
DCOR A Decimal CORrect A A w BCD correction of A (follows ADC, SUBC)
RRC A Rotate A Right thru C C x A7 x . . . x A0 x C
RLC A Rotate A Left thru C C w A7 w . . . w A0 w C
SWAP A SWAP nibbles of A A7 . . . A4 Ý A3 . . . A0
SC Set C C w 1, HC w 1
RC Reset C C w 0, HC w 0
IFC IF C IF C is true, do next instruction
IFNC IF Not C If C is not true, do next instruction
POP A POP the stack into A SP w SP a 1, A w [SP]
PUSH A PUSH A onto the stack [SP] w A, SP w SP b 1
VIS Vector to Interrupt Service Routine PU w [VU], PL w [VL]
JMPL Addr. Jump absolute Long PC w ii (ii e 15 bits, 0 to 32k)
JMP Addr. Jump absolute PC9 . . . 0 w i (i e 12 bits)
JP Disp. Jump relative short PC w PC a r (r is b31 to a 32, except 1)
JSRL Addr. Jump SubRoutine Long [SP] w PL, [SPb1] w PU,SPb2, PC w ii
JSR Addr Jump SubRoutine [SP] w PL, [SPb1] w PU,SPb2, PC9 . . . 0 w i
JID Jump InDirect PL w ROM (PU,A)
RET RETurn from subroutine SP a 2, PL w [SP], PU w [SPb1]
RETSK RETurn and SKip SP a 2, PL w [SP],PU w [SPb1]
RETI RETurn from Interrupt SP a 2, PL w [SP],PU w [SPb1],GIE w 1
INTR Generate an Interrupt [SP] w PL, [SPb1] w PU, SPb2, PC w 0FF
NOP No OPeration PC w PC a 1

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 Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction
opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions Instructions Using A & C Transfer of Control

Instructions
[B] Direct Immed. CLRA 1/1
INCA 1/1 JMPL 3/4
ADD 1/1 3/4 2/2
DECA 1/1 JMP 2/3
ADC 1/1 3/4 2/2
LAID 1/3 JP 1/3
SUBC 1/1 3/4 2/2
DCOR 1/1 JSRL 3/5
AND 1/1 3/4 2/2
RRCA 1/1 JSR 2/5
OR 1/1 3/4 2/2
RLCA 1/1 JID 1/3
XOR 1/1 3/4 2/2
SWAPA 1/1 VIS 1/5
IFEQ 1/1 3/4 2/2
SC 1/1 RET 1/5
IFNE 1/1 3/4 2/2
RC 1/1 RETSK 1/5
IFGT 1/1 3/4 2/2
IFC 1/1 RETI 1/5
IFBNE 1/1
IFNC 1/1 INTR 1/7
DRSZ 1/3
PUSHA 1/3 NOP 1/1
SBIT 1/1 3/4 POPA 1/3
RBIT 1/1 3/4 ANDSZ 2/2
IFBIT 1/1 3/4

RPND 1/1

Memory Transfer Instructions

Register Register Indirect
Direct Immed.
Indirect Auto Incr. & Decr.
[B] [X] [B a , Bb] [X a , Xb]
X A,* 1/1 1/3 2/3 1/2 1/3
LD A,* 1/1 1/3 2/3 2/2 1/2 1/3
LD B, Imm 1/1 (IF B k 16)
LD B, Imm 2/2 (IF B l 15)
LD Mem, Imm 2/2 3/3 2/2
LD Reg, Imm 2/3
IFEQ MD, Imm 3/3
* e l Memory location addressed by B or X or directly.

http://www.national.com 36
Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis

F E D C B A 9 8

JP b15 JP b31 LD 0F0, Ý i DRSZ 0F0 RRCA RC ADC A,Ýi ADC A,[B] 0
JP b14 JP b30 LD 0F1, Ý i DRSZ 0F1 * SC SUBC A, Ýi SUB A,[B] 1
JP b13 JP b29 LD 0F2, Ý i DRSZ 0F2 X A, [X a ] X A,[B a ] IFEQ A,Ýi IFEQ A,[B] 2
JP b12 JP b28 LD 0F3, Ý i DRSZ 0F3 X A, [Xb] X A,[Bb] IFGT A,Ýi IFGT A,[B] 3
JP b11 JP b27 LD 0F4, Ý i DRSZ 0F4 VIS LAID ADD A,Ýi ADD A,[B] 4

JP b10 JP b26 LD 0F5, Ý i DRSZ 0F5 RPND JID AND A,Ýi AND A,[B] 5
JP b9 JP b25 LD 0F6, Ý i DRSZ 0F6 X A,[X] X A,[B] XOR A,Ýi XOR A,[B] 6
JP b8 JP b24 LD 0F7, Ý i DRSZ 0F7 * * OR A,Ýi OR A,[B] 7
JP b7 JP b23 LD 0F8, Ý i DRSZ 0F8 NOP RLCA LD A,Ýi IFC 8
JP b6 JP b22 LD 0F9, Ý i DRSZ 0F9 IFNE IFEQ IFNE IFNC 9
A,[B] Md,Ýi A,Ýi
JP b5 JP b21 LD 0FA, Ý i DRSZ 0FA LD A,[X a ] LD A,[B a ] LD [B a ],Ýi INCA A
JP b4 JP b20 LD 0FB, Ý i DRSZ 0FB LD A,[Xb] LD A,[Bb] LD [Bb],Ýi DECA B

JP b3 JP b19 LD 0FC, Ý i DRSZ 0FC LD Md,Ýi JMPL X A,Md POPA C

JP b2 JP b18 LD 0FD, Ý i DRSZ 0FD DIR JSRL LD A,Md RETSK D
JP b1 JP b17 LD 0FE, Ý i DRSZ 0FE LD A,[X] LD A,[B] LD [B],Ýi RET E
JP b0 JP b16 LD 0FF, Ý i DRSZ 0FF * * LD B,Ýi RETI F

37 http://www.national.com
 Opcode Table (Continued)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
7 6 5 4 3 2 1 0
IFBIT ANDSZ LD B,Ý0F IFBNE 0 JSR JMP JP a 17 INTR 0
0,[B] A, Ýi x000 – x0FF x000 – x0FF
IFBIT * LD B,Ý0E IFBNE 1 JSR JMP JP a 18 JP a 2 1
1,[B] x100 – x1FF x100 – x1FF
IFBIT * LD B,Ý0D IFBNE 2 JSR JMP JP a 19 JP a 3 2
2,[B] x200 – x2FF x200 – x2FF
IFBIT * LD B,Ý0C IFBNE 3 JSR JMP JP a 20 JP a 4 3
3,[B] x300 – x3FF x300 – x3FF
IFBIT CLRA LD B,Ý0B IFBNE 4 JSR JMP JP a 21 JP a 5 4
4,[B] x400 – x4FF x400 – x4FF
IFBIT SWAPA LD B,Ý0A IFBNE 5 JSR JMP JP a 22 JP a 6 5
5,[B] x500 – x5FF x500 – x5FF
IFBIT DCORA LD B,Ý09 IFBNE 6 JSR JMP JP a 23 JP a 7 6
6,[B] x600 – x6FF x600 – x6FF
IFBIT PUSHA LD B,Ý08 IFBNE 7 JSR JMP JP a 24 JP a 8 7
7,[B] x700 – x7FF x700 – x7FF
SBIT RBIT LD B,Ý07 IFBNE 8 JSR JMP JP a 25 JP a 9 8
0,[B] 0,[B] x800 – x8FF x800 – x8FF
SBIT RBIT LD B,Ý06 IFBNE 9 JSR JMP JP a 26 JP a 10 9
1,[B] 1,[B] x900 – x9FF x900 – x9FF
SBIT RBIT LD B,Ý05 IFBNE 0A JSR JMP JP a 27 JP a 11 A
2,[B] 2,[B] xA00 – xAFF xA00 – xAFF
SBIT RBIT LD B,Ý04 IFBNE 0B JSR JMP JP a 28 JP a 12 B
3,[B] 3,[B] xB00 – xBFF xB00 – xBFF
SBIT RBIT LD B,Ý03 IFBNE 0C JSR JMP JP a 29 JP a 13 C
4,[B] 4,[B] xC00 – xCFF xC00 – xCFF
SBIT RBIT LD B,Ý02 IFBNE 0D JSR JMP JP a 30 JP a 14 D
5,[B] 5,[B] xD00 – xDFF xD00 – xDFF
SBIT RBIT LD B,Ý01 IFBNE 0E JSR JMP JP a 31 JP a 15 E
6,[B] 6,[B] xE00 – xEFF xE00 – xEFF
SBIT RBIT LD B,Ý00 IFBNE 0F JSR JMP JP a 32 JP a 16 F
7,[B] 7,[B] xF00 – xFFF xF00 – xFFF
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT Ýi,A

http://www.national.com 38
Mask Options Development Support
The device mask programmable options are shown below. SUMMARY
The options are programmed at the same time as the ROM
pattern submission.
# iceMASTERTM : IM-COP8/400ÐFull feature in-circuit em-
ulation for all COP8 products. A full set of COP8 Basic
OPTION 1: CLOCK CONFIGURATION and Feature Family device and package specific probes
4 1 Crystal Oscillator (CKI/10) are available.
G7 (CKO) is clock generator # COP8 Debug Module: Moderate cost in-circuit emulation
output to crystal/resonator and development programming unit.
CKI is the clock input # COP8 Evaluation and Programming Unit: EPU-
4 2 Single-pin RC controlled COP888GGÐlow cost in-circuit simulation and develop-
oscillator (CKI/10) ment programming unit.
G7 is available as a HALT # Assembler: COP8-DEV-IBMA. A DOS installable cross
restart and/or general purpose development Assembler, Linker, Librarian and Utility
input Software Development Tool Kit.
# C Compiler: COP8C. A DOS installable cross develop-
OPTION 2: HALT
ment Software Tool Kit.
4 1 Enable HALT mode
# OTP/EPROM Programmer Support: Covering needs
4 2 Disable HALT mode from engineering prototype, pilot production to full pro-
OPTION 3: BONDING OPTIONS duction environments.
4 1 44-Pin PLCC
4 2 40-Pin DIP
4 3 NA
4 4 28-Pin DIP
4 5 28-Pin SO

39 http://www.national.com
 Development Support (Continued)
IceMASTER (IM) IN-CIRCUIT EMULATION # Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by # Single base unit and debugger software reconfigurable to
MetaLink Corporation to support the whole COP8 family of support the entire COP8 family; only the probe personali-
products. National is a resale vendor for these products. ty needs to change. Debugger software is processor cus-
tomized, and reconfigured from a master model file.
See Figure 19 for configuration.
# Processor specific symbolic display of registers and bit
The iceMASTER IM-COP8/400 with its device specific
level assignments, configured from master model file.
COP8 Probe provides a rich feature set for developing, test-
ing and maintaining product: # Halt/Idle mode notification.
# Real-time in-circuit emulation; full 2.4V–5.5V operation # On-Line HELP customized to specific processor using
range, full DC-10 MHz clock. Chip options are program- master model file.
mable or jumper selectable. # Includes a copy of COP8-DEV-IBMA assembler and link-
# Direct connection to application board by package com- er SDK.
patible socket or surface mount assembly. IM Order Information
# Full 32 kbyte of loadable programming space that over- Base Unit
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on IM-COP8/400-1 iceMASTER Base Unit,
the probe as necessary. 110V Power Supply
# Full 4k frame synchronous trace memory. Address, in- IM-COP8/400-2 iceMASTER Base Unit,
struction, and 8 unspecified, circuit connectable trace 220V Power Supply
lines. Display can be HLL source (e.g., C source), assem-
bly or mixed. iceMASTER Probe
# A full 64k hardware configurable break, trace on, trace MHW-884EG28DWPC 28 DIP
off control, and pass count increment events.
MHW-888EG40DWPC 40 DIP
# Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD) MHW-888EG44PWPC 44 PLCC
linked object formats.
Adapter for SO Package
# Real time performance profiling analysis; selectable
bucket definition. MHW-SOIC 28 28 SO
# Watch windows, content updated automatically at each
execution break.

TL/DD/10830 – 32
FIGURE 19. COP8 iceMASTER Environment

http://www.national.com 40
Development Support (Continued)
iceMASTER DEBUG MODULE (DM) # Debugger software is processor customized, and recon-
figured from a master model file.
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM pro- # Processor specific symbolic display of registers and bit
gramming tool developed and marketed by MetaLink Corpo- level assignments, configured from master model file.
ration to support the whole COP8 family of products. Nation- # Halt/Idle mode notification.
al is a resale vendor for these products. # Programming menu supports full product line of program-
See Figure 20 for configuration. mable OTP and EPROM COP8 products. Program data
The iceMASTER Debug Module is a moderate cost devel- is taken directly from the overlay RAM.
opment tool. It has the capability of in-circuit emulation for a # Programming of 44 PLCC and 68 PLCC parts requires
specific COP8 microcontroller and in addition serves as a external programming adapters.
programming tool for COP8 OTP and EPROM product fami- # Includes wallmount power supply.
lies. Summary of features is as follows:
# On-board VPP generator from 5V input or connection to
# Real-time in-circuit emulation; full operating voltage external supply supported. Requires VPP level adjust-
range operation, full DC-10 MHz clock. ment per the family programming specification (correct
# All processor I/O pins can be cabled to an application level is provided on an on-screen pop-down display).
development board with package compatible cable to # On-line HELP customized to specific processor using
socket and surface mount assembly. master model file.
# Full 32 kbyte of loadable programming space that over- # Includes a copy of COP8-DEV-IBMA assembler and link-
lays (replaces) the on-chip ROM or EPROM. On-chip er SDK.
RAM and I/O blocks are used directly or recreated as
necessary. DM Order Information
# 100 frames of synchronous trace memory. The display Debug Module Unit
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the COP8-DM/888GG
trace memory. Cable Adapters
# Configured break points; uses INTR instruction which is
modestly intrusive. DM-COP8/28D 28 DIP

# SoftwareÐonly supported features are selectable. DM-COP8/40D 40 DIP

# Tool set integrated interactive symbolic debuggerÐsup- DM-COP8/44P 44 PLCC
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats. Adapter for SO Package
# Instruction by instruction memory/register changes dis- MHW-SOIC 28 28 SO
played when in single step operation.

TL/DD/10830 – 33
FIGURE 20. COP8-DM Environment

41 http://www.national.com
 Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE # BITS data type extension. Register declaration Ýpragma
DEVELOPMENT TOOL KIT with direct bit level definitions.
National Semiconductor offers a relocatable COP8 macro # C language support for interrupt routines.
cross assembler, linker, librarian and utility software devel- # Expert system, rule based code generation and optimiza-
opment tool kit. Features are summarized as follows: tion.
# Basic and Feature Family instruction set by ‘‘device’’ # Performs consistency checks against the architectural
type. definitions of the target COP8 device.
# Nested macro capability. # Generates program memory code.
# Extensive set of assembler directives. # Supports linking of compiled object or COP8 assembled
# Supported on PC/DOS platform. object formats.
# Generates National standard COFF output files. # Global optimization of linked code.
# Integrated Linker and Librarian. # Symbolic debug load format fully source level supported
by the MetaLink debugger.
# Integrated utilities to generate ROM code file outputs.
# DUMPCOFF utility. SINGLE CHIP OTP/EMULATOR SUPPORT
This product is integrated as a part of MetaLink tools as a The COP8 family is supported by single chip OTP emula-
development kit, fully supported by the MetaLink debugger. tors. For detailed information refer to the emulator specific
It may be ordered separately or it is bundled with the Meta- datasheet and the emulator selection table below:
Link products at no additional cost. OTP Emulator Ordering Information
Order Information
Clock
Device Number Package Emulates
Assembler SDK: Option
COP8-DEV-IBMA Assembler SDK on installable COP87L84EGN-XE Crystal 28 DIP COP884CS
3.5× PC/DOS Floppy Disk Drive
COP87L84EGM-XE Crystal 28 SO COP884CS
format. Periodic upgrades and
most recent version is available COP87L88EGN-XE Crystal 40 N COP888CS
on National’s BBS and Internet.
COP87L88EGV-XE Crystal 44 PLCC COP888CS
COP8 C COMPILER
INDUSTRY WIDE OTP/EPROM PROGRAMMING
A C Compiler is developed and marketed by Byte Craft Lim- SUPPORT
ited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embed- Programming support, in addition to the MetaLink develop-
ded configuration of the COP8 family of products. ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
Features are summarized as follows: laboratory to full production.
# ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.

Approved List

North
Manufacturer Europe Asia
America
BP (800) 225-2102 a 49-8152-4183 a 852-234-16611
Microsystems (713) 688-4600 a 49-8856-932616 a 852-2710-8121
Fax: (713) 688-0920
Data I/O (800) 426-1045 a 44-0734-440011 Call
(206) 881-6444 North America
Fax: (206) 882-1043
HI – LO (510) 623-8860 Call Asia a 886-2-764-0215
Fax: a 886-2-756-6403
ICE (800) 624-8949 a 44-1226-767404
Technology (919) 430-7915 Fax: 0-1226-370-434
MetaLink (800) 638-2423 a 49-80 9156 96-0 a 852-737-1800
(602) 926-0797 Fax: a 49-80 9123 86
Fax: (602) 693-0681
Systems (408) 263-6667 a 41-1-9450300 a 886-2-917-3005
General Fax: a 886-2-911-1283
Needhams (916) 924-8037
Fax: (916) 924-8065

http://www.national.com 42
Development Support (Continued)
AVAILABLE LITERATURE DIAL-A-HELPER via a WorldWide Web Browser
For more information, please see the COP8 Basic Family ftp://nscmicro.nsc.com
User’s Manual, Literature Number 620895, COP8 Feature
National Semiconductor on the WorldWide Web
Family User’s Manual, Literature Number 620897 and Na-
tional’s Family of 8-bit Microcontrollers COP8 Selection See us on the WorldWide Web at: http://www.national.com
Guide, Literature Number 630009. CUSTOMER RESPONSE CENTER
DIAL-A-HELPER SERVICE Complete product information and technical support is avail-
Dial-A-Helper is a service provided by the Microcontroller able from National’s customer response centers.
Applications group. The Dial-A-Helper is an Electronic Infor-
CANADA/U.S.: Tel: (800) 272-9959
mation System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Inter- email: support @ tevm2.nsc.com
net via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as Net- EUROPE: email: europe.support @ nsc.com
scape or Mosaic. Deutsch Tel: a 49 (0) 180-530 85 85
The Dial-A-Helper system provides access to an automated
English Tel: a 49 (0) 180-532 78 32
information storage and retrieval system. The system capa-
bilities include a MESSAGE SECTION (electronic mail, Fran3ais Tel: a 49 (0) 180-532 93 58
when accessed as a BBS) for communications to and from
Italiano Tel: a 49 (0) 180-534 16 80
the Microcontroller Applications Group and a FILE SEC-
TION which consists of several file areas where valuable JAPAN: Tel: a 81-043-299-2309
application software and utilities could be found.
S.E. ASIA: Beijing Tel: ( a 86) 10-6856-8601
DIAL-A-HELPER BBS via a Standard Modem
Shanghai Tel: ( a 86) 21-6415-4092
Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427 Hong Kong Tel: ( a 852) 2737-1600
EUROPE: ( a 49) 0-8141-351332 Korea Tel: ( a 82) 2-3771-6909
Baud: 14.4k Malaysia Tel: ( a 60-4) 644-9061
Set-up: Length: 8-Bit
Singapore Tel: ( a 65) 255-2226
Parity: None
Taiwan Tel: a 886-2-521-3288
Stop Bit: 1
Operation: 24 Hrs., 7 Days AUSTRALIA: Tel: ( a 61) 3-9558-9999

DIAL-A-HELPER via FTP INDIA: Tel: ( a 91) 80-559-9467

ftp nscmicro.nsc.com
user: anonymous
password: username @ yourhost.site.domain

43 http://www.national.com
 Physical Dimensions inches (millimeters) unless otherwise noted

28-Lead Small Outline Wide Body Package (M)

Order Number COP884CS-XXX/WM,
COP984CS-XXX/WM or COP984CSH-XXX/WM
NS Package Number M28B

http://www.national.com 44
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP884CS-XXX/N,
COP984CS-XXX/N or COP984CSH-XXX/N
NS Package Number N28B

Molded Dual-In-Line Package (N)

Order Number COP888CS-XXX/N,
COP988CS-XXX/N or COP988CSH-XXX/N
NS Package Number N40A

45 http://www.national.com
COP688CS/COP684CS/COP888CS/COP884CS/COP988CS/COP984CS
8-Bit Microcontroller with UART and One Multi-Function Timer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Plastic Leaded Chip Carrier (V)

Order Number COP888CS-XXX/V,
COP988CS-XXX/V or COP988CSH-XXX/V
NS Package Number V44A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: a49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
Arlington, TX 76017 Email: europe.support @ nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: a49 (0) 180-532 78 32 Hong Kong
Fran3ais Tel: a49 (0) 180-532 93 58 Tel: (852) 2737-1600
http://www.national.com Italiano Tel: a49 (0) 180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.