Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

DESCRIPTION PIN CONFIGURATIONS

The 555 monolithic timing circuit is a highly stable controller capable
of producing accurate time delays, or oscillation. In the time delay D, N, FE Packages
mode of operation, the time is precisely controlled by one external
resistor and capacitor. For a stable operation as an oscillator, the GND 1 8 VCC
free running frequency and the duty cycle are both accurately
TRIGGER 2 7 DISCHARGE
controlled with two external resistors and one capacitor. The circuit
may be triggered and reset on falling waveforms, and the output OUTPUT 3 6 THRESHOLD

structure can source or sink up to 200mA. RESET 4 5 CONTROL VOLTAGE

FEATURES F Package
• Turn-off time less than 2µs
GND 1 14 VCC
• Max. operating frequency greater than 500kHz NC 2 13 NC

• Timing from microseconds to hours TRIGGER 3 12 DISCHARGE

• Operates in both astable and monostable modes OUTPUT 4 11 NC

• High output current NC 5 10 THRESHOLD

RESET 6 9
• Adjustable duty cycle
NC

NC 7 8 CONTROL VOLTAGE
• TTL compatible
• Temperature stability of 0.005% per °C TOP VIEW

APPLICATIONS
• Precision timing
• Pulse generation
• Sequential timing
• Time delay generation
• Pulse width modulation

ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
8-Pin Plastic Small Outline (SO) Package 0 to +70°C NE555D 0174C
8-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE555N 0404B
8-Pin Plastic Dual In-Line Package (DIP) -40°C to +85°C SA555N 0404B
8-Pin Plastic Small Outline (SO) Package -40°C to +85°C SA555D 0174C
8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CFE
8-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555CN 0404B
14-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555N 0405B
8-Pin Hermetic Cerdip -55°C to +125°C SE555FE
14-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C NE555F 0581B
14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555F 0581B
14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CF 0581B

August 31, 1994 346 853-0036 13721

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

BLOCK DIAGRAM
VCC
8

R CONTROL
VOLTAGE
THRESH- 5
OLD
6 COMPARATOR

R
TRIGGER
COMPARATOR 2

DIS-
CHARGE
7 RESET
FLIP FLOP 4

OUTPUT
STAGE

3 1
OUTPUT GND

EQUIVALENT SCHEMATIC
FM
CONTROL VOLTAGE

VCC R1 R2 R3 R R R12
4.7K 330 4.7 4 7 6.8K
K 1 5
K K
Q21
Q5 Q6 Q7 Q9
Q22
Q8
Q19 R13
3.9K

Q1 Q4 R1
0
THRESHOLD Q2 Q3 82. OUTPUT
K Q23
C B
CB
Q18 R11
R5 E 4.7K Q20
10 R8
K Q11 Q12 5K
Q17 R14
Q10 Q13 220
TRIGGER Q16
Q24
Q25
RESET Q15
R9 R15
DISCHARGE Q14 R6 4.7K
100K 5K

R16
GND 100

NOTE: Pin numbers are for 8-Pin package

August 31, 1994 347

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT
Supply voltage
VCC SE555 +18 V
NE555, SE555C, SA555 +16 V
PD Maximum allowable power dissipation1 600 mW
TA Operating ambient temperature range
NE555 0 to +70 °C
SA555 -40 to +85 °C
SE555, SE555C -55 to +125 °C
TSTG Storage temperature range -65 to +150 °C
TSOLD Lead soldering temperature (10sec max) +300 °C
NOTES:
1. The junction temperature must be kept below 125°C for the D package and below 150°C for the FE, N and F packages. At ambient tempera-
tures above 25°C, where this limit would be derated by the following factors:
D package 160°C/W
FE package 150°C/W
N package 100°C/W
F package 105°C/W

August 31, 1994 348

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

DC AND AC ELECTRICAL CHARACTERISTICS

TA = 25°C, VCC = +5V to +15 unless otherwise specified.
SE555 NE555/SE555C
SYMBOL PARAMETER TEST CONDITIONS UNIT
Min Typ Max Min Typ Max
VCC Supply voltage 4.5 18 4.5 16 V
ICC Supply current (low VCC=5V, RL=∞ 3 5 3 6 mA
state)1 VCC=15V, RL=∞ 10 12 10 15 mA
Timing error (monostable) RA=2kΩ to 100kΩ
tM Initial accuracy2 C=0.1µF 0.5 2.0 1.0 3.0 %
∆tM/∆T Drift with temperature 30 100 50 150 ppm/°C
∆tM/∆VS Drift with supply voltage 0.05 0.2 0.1 0.5 %/V
Timing error (astable) RA, RB=1kΩ to 100kΩ
tA Initial accuracy2 C=0.1µF 4 6 5 13 %
∆tA/∆T Drift with temperature VCC=15V 500 500 ppm/°C
∆tA/∆VS Drift with supply voltage 0.15 0.6 0.3 1 %/V
VC Control voltage level VCC=15V 9.6 10.0 10.4 9.0 10.0 11.0 V
VCC=5V 2.9 3.33 3.8 2.6 3.33 4.0 V
VCC=15V 9.4 10.0 10.6 8.8 10.0 11.2 V
VTH Threshold voltage
VCC=5V 2.7 3.33 4.0 2.4 3.33 4.2 V
ITH Threshold current3 0.1 0.25 0.1 0.25 µA
VTRIG Trigger voltage VCC=15V 4.8 5.0 5.2 4.5 5.0 5.6 V
VCC=5V 1.45 1.67 1.9 1.1 1.67 2.2 V
ITRIG Trigger current VTRIG=0V 0.5 0.9 0.5 2.0 µA
VRESET Reset voltage4 VCC=15V, VTH =10.5V 0.3 1.0 0.3 1.0 V
IRESET Reset current VRESET=0.4V 0.1 0.4 0.1 0.4 mA
Reset current VRESET=0V 0.4 1.0 0.4 1.5 mA
VCC=15V
ISINK=10mA 0.1 0.15 0.1 0.25 V
ISINK=50mA 0.4 0.5 0.4 0.75 V
VOL Output voltage (low) ISINK=100mA 2.0 2.2 2.0 2.5 V
ISINK=200mA 2.5 2.5 V
VCC=5V
ISINK=8mA 0.1 0.25 0.3 0.4 V
ISINK=5mA 0.05 0.2 0.25 0.35 V
VCC=15V
ISOURCE=200mA 12.5 12.5 V
VOH Output voltage (high) ISOURCE=100mA 13.0 13.3 12.75 13.3 V
VCC=5V
ISOURCE=100mA 3.0 3.3 2.75 3.3 V
tOFF Turn-off time5 VRESET=VCC 0.5 2.0 0.5 2.0 µs
tR Rise time of output 100 200 100 300 ns
tF Fall time of output 100 200 100 300 ns
Discharge leakage current 20 100 20 100 nA
NOTES:
1. Supply current when output high typically 1mA less.
2. Tested at VCC=5V and VCC=15V.
3. This will determine the max value of RA+RB, for 15V operation, the max total R=10MΩ, and for 5V operation, the max. total R=3.4MΩ.
4. Specified with trigger input high.
5. Time measured from a positive going input pulse from 0 to 0.8×VCC into the threshold to the drop from high to low of the output. Trigger is
tied to threshold.

August 31, 1994 349

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Pulse Width Supply Current Delay Time
Required for Triggering vs Supply Voltage vs Temperature
150 10.0 1.015

125 +125oC
MINIMUM PULSE WIDTH (ns)

8.0 1.010

SUPPLY CURRENT – mA

NORMALIZED DELAY TIME

-55oC +25oC
100 1.005
6.0
0 oC
75 -55oC 1.000
+25oC 4.0
50 +70oC 0.995

2.0
25 +125oC 0.990

0 0 0.985
5.0 10.0 15.0 -50 -25 0 +25 +50 +75 +100 +125
0 0.1 0.2 0.3 0.4 (XVCC)
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE SUPPLY VOLTAGE – VOLTS
TEMPERATURE – oC

Low Output Voltage Low Output Voltage Low Output Voltage

vs Output Sink Current vs Output Sink Current vs Output Sink Current
10 10 10
VCC = 5V VCC = 10V VCC = 15V

1.0 -55oC 1.0

1.0 -55oC -55oC
+25oC
V OUT – VOLTS

V OUT – VOLTS
V OUT – VOLTS

+25oC
+25oC
+25oC +25oC
0.1 0.1 0.1 +25oC
+25oC
+25oC
-55oC 55oC

0.001 0.01 0.01

1.0 2.0 5.0 10 20 50 100 1.0 2.0 5.0 10 20 50 100 1.0 2.0 5.0 10 20 50 100

ISINK – mA ISINK – mA ISINK – mA

High Output Voltage Drop Delay Time Propagation Delay vs Voltage

vs Output Source Current vs Supply Voltage Level of Trigger Pulse
1.015 300
2.0
1.8 –55oC
1.010 250
PROPAGATION DELAY – ns
NORMALIZED DELAY TIME

1.6
+25oC -55oC
V CC V OUT – VOLTS

1.4 1.005 200

0 oC
1.2
+125oC
1.000 150
1.0

0.8 100
0.995 +25oC
0.6
+70oC
0.4 0.990 50
5V ≤ VCC ≤ 15V +25oC
0.2
0 0.985 0

1.0 2.0 5.0 10 20 50 100 0 5 10 15 20 0 0.1 0.2 0.3 0.4

ISOURCE – mA SUPPLY VOLTAGE – V LOWEST VOLTAGE LEVEL

OF TRIGGER PULSE – XVCC

August 31, 1994 350

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

TYPICAL APPLICATIONS
VCC

RA
8 555 OR 1/2 556

DISCHARGE 7

RB R
CONTROL 5
VOLTAGE
COMP
6
.01µF THRESHOLD

FLIP 3
R OUTPUT
FLOP
OUTPUT

2 COMP
TRIGGER

1.49
C f
4 (R A
2R B)C

RESET

Astable Operation

VCC

RA
8 555 OR 1/2 556

DISCHARGE 7

R
CONTROL 5
VOLTAGE | ∆t |
COMP
6
.01µF THRESHOLD

C
FLIP 3
R OUTPUT
FLOP
OUTPUT

2 COMP
TRIGGER

1 R
 V
3 CC

4 ∆T = 1.1RC

RESET

Monostable Operation

August 31, 1994 351

Philips Semiconductors Linear Products Product specification

Timer NE/SA/SE555/SE555C

TYPICAL APPLICATIONS

VCC

VCC VCC

10k

1/3 VCC
.001µF
2 555

OVOLTS
1
DURATION OF
TRIGGER PULSE AS
SEEN BY THE TIMER
SWITCH GROUNDED
AT THIS POINT
NOTE: All resistor values are in Ω

Figure 1. AC Coupling of the Trigger Pulse

Trigger Pulse Width Requirements and Time
Delays Another consideration is the “turn-off time”. This is the measurement
Due to the nature of the trigger circuitry, the timer will trigger on the of the amount of time required after the threshold reaches 2/3 VCC
negative going edge of the input pulse. For the device to time out to turn the output low. To explain further, Q1 at the threshold input
properly, it is necessary that the trigger voltage level be returned to turns on after reaching 2/3 VCC, which then turns on Q5, which turns
some voltage greater than one third of the supply before the time out on Q6. Current from Q6 turns on Q16 which turns Q17 off. This
period. This can be achieved by making either the trigger pulse allows current from Q19 to turn on Q20 and Q24 to given an output
sufficiently short or by AC coupling into the trigger. By AC coupling low. These steps cause the 2µs max. delay as stated in the data
the trigger, see Figure 1, a short negative going pulse is achieved sheet.
when the trigger signal goes to ground. AC coupling is most
frequently used in conjunction with a switch or a signal that goes to Also, a delay comparable to the turn-off time is the trigger release
ground which initiates the timing cycle. Should the trigger be held time. When the trigger is low, Q10 is on and turns on Q11 which turns
low, without AC coupling, for a longer duration than the timing cycle on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off
the output will remain in a high state for the duration of the low current to Q20 and Q24, which results in output high. When the
trigger signal, without regard to the threshold comparator state. This trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on
is due to the predominance of Q15 on the base of Q16, controlling and the circuit then follows the same path and time delay explained
the state of the bi-stable flip-flop. When the trigger signal then as “turn off time”. This trigger release time is very important in
returns to a high level, the output will fall immediately. Thus, the designing the trigger pulse width so as not to interfere with the
output signal will follow the trigger signal in this case. output signal as explained previously.

August 31, 1994 352

 CD4033BMS
December 1992 CMOS Decade Counter/Divider

Features Description
• High Voltage Types (20V Rating) CD4033BMS consists of a 5 stage Johnson decade counter
and an output decoder which converts the Johnson code to a 7
• Decoded 7 Segment Display Outputs and Ripple
segment decoded output for driving one stage in a numerical
Blanking
display.
• Counter and 7 Segment Decoding in One Package
This device is particularly advantageous in display applications
• Easily Interfaced with 7 Segment Display Types where low power dissipation and/or low package count is
• Fully Static Counter Operation DC to 6MHz (typ.) at VDD = important.
10V A high RESET signal clears the decade counter to its zero
• Ideal for Low-Power Displays count. The counter is advanced one count at the positive clock
signal transition if the CLOCK INHIBIT signal is low. Counter
• “Ripple Blanking” and Lamp Test advancement via the clock line is inhibited when the CLOCK
• 100% Tested for Quiescent Current at 20V INHIBIT signal is high. The CLOCK INHIBIT signal can be used
as a negative-edge clock if the clock line is held high. Antilock
• Standardized Symmetrical Output Characteristics gating is provided on the JOHNSON counter, thus assuring
proper counting sequence. The CARRY-OUT (Cout) signal
• 5V, 10V and 15V Parametric Ratings
completes one cycle every ten CLOCK INPUT cycles and is
• Schmitt-Triggered Clock Inputs used to clock the succeeding decade directly in a multi-decade
counting chain.
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip- The seven decoded outputs (a, b, c, d, e, f, g) illuminate the
tion of “B” Series CMOS Device’s proper segments in a seven segment display device used for
representing the decimal numbers 0 to 9. The 7 segment out-
Applications puts go high on selection.

• Decade Counting 7 Segment Decimal Display

• Frequency Division 7 Segment Decimal Displays
• Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/
Display
• Counter/Display Driver For Meter Applications

Pinout Functional Diagram

CD4033BMS VDD
TOP VIEW 16

1 10 a
7 DECODED OUTPUTS

CLOCK 1 16 VDD CLOCK 12 b

CLOCK INHIBIT 2 15 RESET 2 13 c
CLOCK
RIPPLE BLANKING IN 3 14 LAMP TEST 9 d
INHIBIT
RIPPLE BLANKING OUT 4 13 c
15 11 e
CARRY OUT 5 12 b RESET
6 f
f 6 11 e
14 7 g
g 7 10 a LAMP
TEST 5
9 d CARRY OUT
VSS 8
3 4
RIPPLE RIPPLE
BLK BLK
8
IN OUT
VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3301
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-826
 CD4033BMS

The CD4033BMS has provisions for automatic blanking of In a purely fractional number the zero immediately preceding
the non-significant zeros in a multi-digit decimal number the decimal point can be displayed by connecting the RBI of
which results in an easily readable display consistent with that stage to a high level voltage (instead of to the RBO of
normal writing practice. For example, the number 0050.0700 the next more-significant-stage). For example: optional zero
in an eight digit display would be displayed as 50.07. Zero → 0.7346. Likewise, the zero in a number such as 763.0 can
suppression on the integer side is obtained by connecting be displayed by connecting the RBI of the CD4033BMS
the RBI terminal of the CD4033BMS associated with the associated with it to a high-level voltage.
most significant digit in the display to a low-level voltage and
Ripple blanking of non-significant zeros provides an appre-
connecting the RBO terminal of that stage to the RBI termi-
ciable savings in display power.
nal of the CD4033BMS in the next-lower significant position
in the display. This procedure is continued for each succeed- The CD4033BMS has a LAMP TEST input which, when con-
ing CD4033BMS on the interger side of the display. nected to a high-level voltage, overrides normal decoder
operation and enables a check to be made on possible dis-
On the fraction side of the display the RBI of the
play malfunctions by putting the seven outputs in the high
CD4033BMS associated with the least significant bit is con-
state.
nected to a low-level voltage and the RBO of that
CD4033BMS is connected to the RBI terminal of the The CD4033BMS are supplied in these 16 lead outline pack-
CD4033BMS in the next more-significant-bit position. Again, ages:
this procedure is continued for all CD4033BMS’s on the frac-
tion side of the display. Braze Seal DIP H4W
Frit Seal DIP H2R
Ceramic Flatpack H6W

Logic Diagram

*LAMP TEST COUT

14
(CLOCK ÷ 10)
5

D Q D Q D Q D Q D Q
CL CL CL CL CL
CL Q CL Q CL Q CL Q CL Q 10
R R R R R a
15*

RESET 12
b

13
c

9
d

1 11
*CLOCK e
CL
*CLOCK
INHIBIT 2 6
f

7
g

3
*RBI 4
RBO
16 VDD a
VDD
8
*ALL INPUTS PROTECTED f g b
BY CMOS INPUT SEGMENT
GND DESIGNATIONS
PROTECTION NETWORK
e c

VSS d
FIGURE 1. CD4033BMS

7-827
 Specifications CD4033BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25o C -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

7-828
 Specifications CD4033BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns
Clock To Carry Out TPLH1
10, 11 +125oC, -55oC - 675 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 700 ns
Clock To Decode Out TPLH2
10, 11 +125oC, -55oC - 945 ns
Propagation Delay TPLH3 VDD = 5V, VIN = VDD or GND 9 +25oC - 550 ns
Reset To Carry Out
10, 11 +125oC, -55oC - 743 ns
Propagation Delay TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns
Reset To Decode Out TPLH4
10, 11 +125oC, -55oC - 810 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2.5 - MHz
Frequency
10, 11 +125oC, -55oC 1.85 - MHz
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 o
-55 C, +25 C o
- 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125 oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA

7-829
 Specifications CD4033BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
o
-55 C - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, +7 - V
-55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 200 ns
Clock To Carry Out TPLH1
VDD = 15V 1, 2, 3 +25oC - 150 ns
o
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25 C - 250 ns
Clock To Decode Out TPLH2 o
VDD = 15V 1, 2, 3 +25 C - 180 ns
Propagation Delay TPLH3 VDD = 10V 1, 2, 3 +25oC - 240 ns
Reset To Carry Out
VDD = 15V 1, 2, 3 +25oC - 160 ns
Propagation Delay TPHL4 VDD = 10V 1, 2, 3 +25oC - 250 ns
Reset To Decode Out TPLH4
VDD = 15V 1, 2, 3 +25oC - 180 ns
o
Transition Time TTHL VDD = 10V 1, 2, 3 +25 C - 100 ns
TTLH
VDD = 15V 1, 2, 3 +25oC - 50 ns
Maximum Clock Input FCL VDD = 10V 1, 2, 3 +25oC 5.5 - MHz
Frequency oC
VDD = 15V 1, 2, 3 +25 8 - MHz
Minimum Reset Pulse TW VDD = 5V 1, 2, 3 +25oC - 120 ns
Width o
VDD = 10V 1, 2, 3 +25 C - 100 ns
oC
VDD = 15V 1, 2, 3 +25 - 50 ns
Minimum Reset Removal TREM VDD = 5V 1, 2, 3 +25oC - 30 ns
Time oC
VDD = 10V 1, 2, 3 +25 - 15 ns
VDD = 15V 1, 2, 3 +25oC - 10 ns
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 220 ns
Width
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND

7-830
 Specifications CD4033BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9( Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER
Static Burn-In 1 4 - 7, 9 - 14 1 - 3, 8, 15 16
(Note 1)
Static Burn-In 2 1, 2, 14, 15 3 - 6, 8, 10 - 13 7, 9, 16
(Note 1)
Dynamic Burn- - 2, 8, 15 3, 16 4 - 7, 9 - 13 1
In (Note 1)
Irradiation 4 - 7, 9 - 14 8 1 - 3, 15, 16
(Note 2)
PART NUMBER CD4033BMS

7-831
 Specifications CD4033BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 4 - 7, 9 - 13 1 - 3, 8, 14, 15 16
Note 1
Static Burn-In 2 4 - 7, 9 - 13 8 1 - 3, 14 - 16
Note 1
Dynamic Burn- - 2, 3, 8, 14, 15 16 4 - 7, 9 - 13 1
In Note 1
Irradiation 4 - 7, 9 - 13 8 1 - 3, 14 - 16
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

Timing Diagram

CLOCK
RESET R
CLOCK
INHIBIT CL
CL
LAMP p
TEST p Q
RBI D
n
COUT n Q
(CLOCK ÷ 10)
CL CL CL
a CL
b p p
D Q
c n n
d CL Q ≡
e CL CL
R
CL
f
g CL CL
RBO
0 1 234 5 6 78 9 0 1 8 4 56 7 8 9 12

FIGURE 2. CD4033BMS TIMING DIAGRAM FIGURE 3. DETAIL OF TYPICAL FLIP-FLOP STAGE

7-832
 CD4033BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. TYPICAL N-CHANNEL OUTPUT LOW (SINK) FIGURE 5. MINIMUM N-CHANNEL OUTPUT LOW (SINK)
CURRENT CHARACTERISTICS CURRENT CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 6. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) FIGURE 7. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE)
CURRENT CHARACTERISTICS CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPLH, tPHL) (µs)

AMBIENT TEMPERATURE (TA) = +25oC

PROPAGATION DELAY TIME (tPLH, tPHL) (µs)

AMBIENT TEMPERATURE (TA) = +25oC

600 300
SUPPLY VOLTAGE (VDD) = 5V

400 SUPPLY VOLTAGE (VDD) = 5V 200

10V
200 100
10V

15V
15V

0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE FOR FUNCTION OF LOAD CAPACITANCE FOR
DECODED OUTPUTS CARRY-OUT OUTPUTS

7-833
 CD4033BMS

Typical Performance Characteristics (Continued)

MAXIMUM CLOCK INPUT - FREQUENCY (fCL) (MHz)
105 8 AMBIENT TEMPERATURE (TA) = +25oC
20 6
o 4
AMBIENT TEMPERATURE (TA) = +25 C
tr = tf = 20ns 2

POWER DISSIPATION (PD) (µW)

SUPPLY VOLTAGE (VDD) = 5V
104
8
15 6
4

2
10V
103
10 8 10V
6
4
15V
2

102
5 8
6
4

2 (CL) = 15pF
LOAD CAPACITANCE (CL) = 50pF
10
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
0 2 4 6 8 10 12 14 16 1 10 102 103 104 105
SUPPLY VOLTAGE (VDD) (V) INPUT PULSE FREQUENCY (fCL) (MHz)
FIGURE 10. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY FIGURE 11. TYPICAL POWER DISSIPATION AS A FUNCTION
AS A FUNCTION OF SUPPLY VOLTAGE OF CLOCK INPUT FREQUENCY

Light Emitting Diode Displays

VDD
1/7 CA3082
MONSANTO MAN 3 MONSANTO MAN 1 OR EQUIVALENT
OR EQUIVALENT VDD OR EQUIVALENT
(LOW POWER) MAN 1
IB 1/7 CA3082 R
VDD A
OR EQUIVALENT VDD
A R
A
A MAN 3 IF
CD4033BMS CD4033BMS A IB
CLOCK R CLOCK
7 A
INHIBIT INHIBIT 7
SEGMENTS SEGMENTS
RESET RESET
IB IF
R
G G
G
G R
VSS
G VSS
R IB
G
VDD ≥ 3.5V VDD 5V (MIN)
IF ≈ 5mA/SEGMENT IB 0.4mA
100% DUTY CYCLE IF 12mA/Seg.(100% DUTY CYCLE)
VP - VBE - VF(LED) bdc(MIN) 30
R= WHERE VP = INPUT PULSE VCE(SAT) £ 0.5V
ILED
VF = FORWARD DROP VDD - VCE(sat)-VF(LED)
R=
ACROSS DIODE ILED
WHERE VF = FORWARD DROP ACROSS DIODE

FIGURE 12. INTERFACING THE CD4033BMS WITH COMMERCIALLY

AVAILABLE LIGHT EMITTING DIODE DISPLAYS

7-834
 CD4033BMS

7-Segment Display Devices

INCANDESCENT READOUTS
1/7 VT Numitron DR2000 Series
SEGMENTS
TUBE REQUIREMENTS
IB IT VT = 3.5 - 5V
VDD IT = 24mA Segment
ASSUMED CD4049UB
TRANSISTOR
CD4033BMS CHARACTERISTICS at VCC = 10V (min)
CLOCK 1/7 CA3081
7 OR EQUIVALENT Vo “0” ≤ 2V
INHIBIT
SEGMENTS VT βdc (min) ≥ 25 IT = 8mA (min)
RESET VCE (sat) ≤ 0.5V VT ≈ 3.5V to 6V
VCC VDD = 8V (min)
IB = 1mA (min) CD4049UB
VSS 1 OF 7 IT = 24mA (min)
SEGMENTS
at VCC = 10V (min)
Vo “0” ≤ 0.6V
IT = 8mA (min)
1/6 CA4049UB IT

LOW-POWER INCANDESCENT READOUTS ASSUMED at VCC = 6V (min)

PINLITES INC-Series O and R TRANSISTOR Vo “0” ≤ 1V
CHARACTERISTICS IT = 5mA (min)
VT ≈ 1.5V to 3.5V
TUBE REQUIREMENTS VT(V) mA/Segment βdc (min) ≥ 30
0-03-15 1.5 8 VCE (sat) ≤ 0.5V
0-04-30 3 8
0-06-30 3 8 VCC ≥ 3.5V (min)
R-R3-20 2 4.3 IB ≥ 0.25mA (min)
R-R4-30 3 4.3 IT ≤ 7.5mA (min)
*The interfacing buffers shown, while a necessity with the CD4033A, are not required when using the “B” devices; the “B” outputs (≈ 10 times
the “A” outputs) can drive most display devices directly especially at voltages above 10V.

VT ª 170V DC VDD
VDD 1 OF 7
SEGMENTS

CD4033BMS CD4033BMS
CLOCK CLOCK
7
INHIBIT
SEGMENTS INHIBIT
13.5V 7
RESET
LOGIC RESET SEGMENTS
VOLTAGE

VSS d
e c
f b

VSS g a
≈ 4.5V

1.6V
WITH VON = 18V MEDIUM BRIGHTNESS AC OR DC
NEON READOUT (NIXIE TUBE**) IN LOW AMBIENT LIGHT BACKGROUND
1. Alco Electronics - MG19 WILL RESULT. THE POINT OF NO
2. Burroughs - B5971, B7971, B8971 NOTICEABLE GLOW IS VOFF ≈ 4.5V

TUBE REQUIREMENTS VT(Vdc) mA/Segment LOW VOLTAGE VACUUM FLORESCENT READOUTS

Alco MG19 180 0.5 1. Tung-Sol DIGIVAC S/G ‡ Type DT1704A or DT1705C
Burroughs B5971 170 3 2. Nippon Electric (NEC): Type DG12E or LD915
Burroughs B7971, B8971 170 6 TUBE REQUIREMENTS: 100 to 300 µA/segment at tube voltages of 12V
**(Trademark) Burroughs Corp. to 25V depending on required brightness Filament requirement 45mA at
TRANSISTOR CHARACTERISTICS 1.6V, ac or dc.
Leakage with transistor cutoff - 0.05mA
V(BR)CER >VT
βdc (min) ≥ 30 ‡ (Trademark) Wagner Electric Co.

FIGURE 13. INTERFACING THE CD4033BMS WITH COMMERCIALLY

AVAILABLE 7-SEGMENT DISPLAY DEVICES*

7-835
 CD4033BMS

Chip Dimensions and Pad Layouts

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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