UCC21520, UCC21520A

SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

UCC21520, UCC21520A 4A, 6A, 5.7kVRMS Isolated Dual-Channel Gate Drivers

1 Features 3 Description
• Junction temperature range –40 to +150°C The UCC21520 is an isolated dual-channel gate
• Switching parameters: driver with 4A source and 6A sink peak current. It is
– 33ns typical propagation delay designed to drive power MOSFETs, IGBTs, and SiC
– 20ns minimum pulse width MOSFETs up to 5MHz.
– 6ns maximum pulse-width distortion The input side is isolated from the two output
• Common-mode transient immunity (CMTI) greater drivers by a 5.7kVRMS reinforced isolation barrier,
than 125V/ns with a minimum of 125V/ns common-mode transient
• Surge immunity up to 10kV immunity (CMTI). Internal functional isolation between
• 4A peak source, 6A peak sink output the two secondary-side drivers allows a working
• 3V to 18V input VCCI range to interface with both voltage of up to 1500VDC.
digital and analog controllers
• Up to 25V VDD output drive supply Every driver can be configured as two low-side
– 5V and 8V VDD UVLO options drivers, two high-side drivers, or a half-bridge driver
• Programmable overlap and dead time with programmable dead time (DT). A disable pin
• Fast disable for power sequencing shuts down both outputs simultaneously when it is set
• Safety-related certifications (planned): high, and allows normal operation when left open or
– 8000VPK reinforced Isolation per DIN EN IEC grounded. As a fail-safe measure, primary-side logic
60747-17 (VDE 0884-17) failures force both outputs low.
– 5.7kVRMS isolation for 1 minute per UL 1577 Each device accepts VDD supply voltages up to 25V.
– CQC certification per GB4943.1-2022 A wide input VCCI range from 3V to 18V makes the
driver suitable for interfacing with both analog and
2 Applications digital controllers. All supply voltage pins have under
• HEV and BEV battery chargers voltage lock-out (UVLO) protection.
• Isolated converters in DC-DC and AC-DC power
With all these advanced features, the UCC21520
supplies
enables high efficiency, high power density, and
• Server, telecom, it and industrial infrastructures
robustness.
• Motor drive and DC-to-AC solar inverters
• LED lighting Device Information
• Inductive heating PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Uninterruptible power supply (UPS) UCC21520DW DW (SOIC 16) 10.30mm × 7.50mm
UCC21520ADW DW (SOIC 16) 10.30mm × 7.50mm

(1) For all available packages, see Section 14.

VCCI 3,8 16 VDDA

Driver

INA 1 MOD DEMOD UVLO 15 OUTA

14 VSSA
Reinforced Isolation

DIS 5

Disable,
13 NC
NC 7 UVLO Functional Isolation
and 12 NC
Deadtime
DT 6 11 VDDB
Driver
INB 2 MOD DEMOD UVLO 10 OUTB

GND 4
9 VSSB

Copyright © 2017, Texas Instruments Incorporated

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

Table of Contents
1 Features............................................................................1 8 Detailed Description......................................................18
2 Applications..................................................................... 1 8.1 Overview................................................................... 18
3 Description.......................................................................1 8.2 Functional Block Diagram......................................... 18
4 Description (continued).................................................. 3 8.3 Feature Description...................................................19
5 Pin Configuration and Functions...................................4 8.4 Device Functional Modes..........................................23
6 Specifications.................................................................. 5 9 Application and Implementation.................................. 26
6.1 Absolute Maximum Ratings........................................ 5 9.1 Application Information............................................. 26
6.2 ESD Ratings............................................................... 5 9.2 Typical Application.................................................... 26
6.3 Recommended Operating Conditions.........................5 10 Power Supply Recommendations..............................38
6.4 Thermal Information....................................................5 11 Layout........................................................................... 39
6.5 Power Ratings.............................................................6 11.1 Layout Guidelines................................................... 39
6.6 Insulation Specifications............................................. 7 11.2 Layout Example...................................................... 40
6.7 Safety Limiting Values.................................................8 12 Device and Documentation Support..........................42
6.8 Electrical Characteristics.............................................8 12.1 Third-Party Products Disclaimer............................. 42
6.9 Timing Requirements ................................................. 9 12.2 Documentation Support.......................................... 42
6.10 Switching Characteristics..........................................9 12.3 Certifications........................................................... 42
6.11 Insulation Characteristics Curves............................10 12.4 Receiving Notification of Documentation Updates..42
6.12 Typical Characteristics............................................ 11 12.5 Support Resources................................................. 42
7 Parameter Measurement Information.......................... 15 12.6 Trademarks............................................................. 42
7.1 Propagation Delay and Pulse Width Distortion......... 15 12.7 Electrostatic Discharge Caution..............................42
7.2 Rising and Falling Time.............................................15 12.8 Glossary..................................................................42
7.3 Input and Disable Response Time............................ 15 13 Revision History.......................................................... 42
7.4 Programable Dead Time........................................... 16 14 Mechanical, Packaging, and Orderable
7.5 Power-up UVLO Delay to OUTPUT..........................16 Information.................................................................... 44
7.6 CMTI Testing.............................................................17

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

4 Description (continued)
Each device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the
driver suitable for interfacing with both analog and digital controllers. All supply voltage pins have under voltage
lock-out (UVLO) protection.
With all these advanced features, the UCC21520 and the UCC21520A enable high efficiency, high power
density, and robustness in a wide variety of power applications.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

5 Pin Configuration and Functions

INA 1 16 VDDA
INB 2 15 OUTA
VCCI 3 14 VSSA
GND 4 13 NC
DISABLE 5 12 NC
DT 6 11 VDDB
NC 7 10 OUTB
VCCI 8 9 VSSB

Not to scale
Figure 5-1. DW Package 16-Pin SOIC Top View

Table 5-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
DISABLE 5 I
better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when
connecting to a micro controller with distance.
Programmable dead time function.
Tying DT to VCCI allows the outputs to overlap. Placing a 2-kΩ to 500-kΩ resistor (RDT)
DT 6 I between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is
recommended to parallel a ceramic capacitor, ≤1nF, close to the DT pin with RDT to achieve
better noise immunity. It is not recommended to leave DT floating.
GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin
INA 1 I is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin
INB 2 I is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC 7 – No Internal connection.
NC 12 – No internal connection.
NC 13 – No internal connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT.
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
VCCI 3 P
located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
VDDA 16 P
capacitor located as close to the device as possible.
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL
VDDB 11 P
capacitor located as close to the device as possible.
VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P = Power, G = Ground, I = Input, O = Output

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input bias pin supply voltage VCCI to GND –0.3 20 V
Driver bias supply VDDA-VSSA, VDDB-VSSB –0.3 30 V
OUTA to VSSA, OUTB to VSSB –0.3 VDDA/B + 0.3 V
Output signal voltage
OUTA to VSSA, OUTB to VSSB, Transient for 200 ns –2 VDDA/B + 0.3 V
INA, INB, DIS, DT to GND –0.3 VCCI + 0.3 V
Input signal voltage
INA, INB Transient for 50ns –5 VCCI + 0.3 V
Channel to channel voltage VSSA-VSSB, VSSB-VSSA 1500 V
Junction temperature, TJ (2) –40 150 ℃
Storage temperature, Tstg –65 150 ℃

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) To maintain the recommended operating conditions for TJ, see the Section 6.4

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
V(ESD) JEDEC JS-001(1)
Electrostatic discharge V
Charged device model (CDM), per JEDEC
±1000
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCI VCCI Input supply voltage 3 18 V
VDDA, UCC21520A 5-V
Driver output bias supply 6.5 25 V
VDDB UVLO version
VDDA, UCC21520 8-V
Driver output bias supply 9.2 25 V
VDDB UVLO version
TJ Junction temperature –40 150 ℃

6.4 Thermal Information

UCC21520
THERMAL METRIC(1) UNIT
DW-16 (SOIC)

RθJA Junction-to-ambient thermal resistance 69.8 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 33.1 °C/W
RθJB Junction-to-board thermal resistance 36.9 °C/W
ΨJT Junction-to-top(center) characterization parameter 22.2 °C/W
ΨJB Junction-to-board characterization parameter 36 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) 950 mW
Maximum power dissipation by VCCI = 5V, VDDA/VDDB = 20V, INA/B
PDI 50 mW
transmitter side = 3.3V, 460kHz 50% duty cycle square
wave, CL=2.2nF, TJ=150℃, TA=25℃
Maximum power dissipation by each
PDA, PDB 450 mW
driver side

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

6.6 Insulation Specifications

SPECIFIC
PARAMETER TEST CONDITIONS UNIT
ATION
General
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
Shortest terminal-to-terminal distance across the
CPG External Creepage(1) >8 mm
package surface
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664-1 I
Rated mains voltage ≤ 600 VRMS I-IV
Overvoltage category IEC 60664-1
Rated mains voltage ≤ 1000 VRMS I-III
(2)
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
AC voltage (sine wave); time-dependent dielectric
1500 VRMS
VIOWM Maximum isolation working voltage breakdown (TDDB) test
DC voltage 2121 VDC
Tested in air, 1.2/50-µs waveform per IEC
VIMP Maximum inpulse voltage 7692 VPK
62368-1
VTEST = VIOTM, t = 60 s (qualification)
VIOTM Maximum transient isolation voltage 8000 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification
VIOSM Maximum surge isolation voltage(3) 10000 VPK
test), 1.2/50-μs waveform per IEC 62368-1
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 ≤5
s
Method a: After environmental tests subgroup 1,
qpd Apparent charge(4) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = ≤5 pC
10 s
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = 1.2 × VIOTM, tini ≤5
= 1 s; Vpd(m) = 1.875 × VIORM , tm = 1 s
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~1.2 pF
VIO = 500 V, TA = 25°C >1012
RIO Insulation resistance, input to output(5) VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 Ω
VIO = 500 V at TS = 150°C >109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VISO Withstand isolation voltage VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% 5700 VRMS
production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

6.7 Safety Limiting Values

PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT
Rθ JA = 69.8°C/W, VDDA/B = 15 V, TJ = DRIVER 58
150°C, TA = 25°C A,
IS Safety output supply current mA
Rθ JA = 69.8°C/W, VDDA/B = 25 V, TJ = DRIVER
B 34
150°C, TA = 25°C
INPUT 50
DRIVER
870
Rθ JA = 69.8°C/W, TJ = 150°C, TA = A
PS Safety supply power mW
25°C DRIVER
870
B
TOTAL 1790
TS Maximum safety temperature(1) 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the
maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.

6.8 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.4 2.0 mA
IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 2.5 mA
IVCCI VCCI operating current (f = 500 kHz) current per channel 3 3.5 mA
(f = 500 kHz) current per channel, COUT
IVDDA, IVDDB VDDA and VDDB operating current 2.5 4.2 mA
= 100 pF
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
UVLO Rising threshold 5-V UVLO 5.7 6.0 6.3 V
VVDDB_ON
VVDDA_OFF,
UVLO Falling threshold 5-V UVLO 5.4 5.7 6.0 V
VVDDB_OFF
VVDDA_HYS,
UVLO Threshold hysteresis 5-V UVLO 0.3 V
VVDDB_HYS
VVDDA_ON,
UVLO Rising threshold 8-V UVLO 7.7 8.5 8.9 V
VVDDB_ON
VVDDA_OFF,
UVLO Falling threshold 8-V UVLO 7.2 7.9 8.4 V
VVDDB_OFF
VVDDA_HYS,
UVLO Threshold hysteresis 8-V UVLO 0.6 V
VVDDB_HYS
INA, INB AND ENABLE
VINAH, VINBH, VENH Input high threshold voltage 1.2 1.8 2 V
VINAL, VINBL, VENL Input low threshold voltage 0.8 1 1.2 V
VINA_HYS, VINB_HYS,
Input threshold hysteresis 0.8 V
VEN_HYS
Negative transient, ref to GND, 100
VINA, VINB Not production tested, bench test only –5 V
ns pulse
OUTPUT

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

6.8 Electrical Characteristics (continued)

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CVDD = 10 µF, CLOAD = 0.18 µF, f = 1
IOA+, IOB+ Peak output source current 4 A
kHz, bench measurement
CVDD = 10 µF, CLOAD = 0.18 µF, f = 1
IOA-, IOB- Peak output sink current 6 A
kHz, bench measurement
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pull-up
ROHA, ROHB Output resistance at high state 5 Ω
performance. See tRISE in Section 6.10
and Section 8.3.4 for details.
ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω
VVDDA, VVDDB = 15 V, IOUT = –10 mA, TA
VOHA, VOHB Output voltage at high state 14.95 V
= 25°C
VVDDA, VVDDB = 15 V, IOUT = 10 mA, TA
VOLA, VOLB Output voltage at low state 5.5 mV
= 25°C

6.9 Timing Requirements

DEADTIME AND OVERLAP PROGRAMMING MIN NOM MAX UNIT
Ovelap Ovelap Ovelap
DT DT pin tied to VCCI determined determined determined ns
by INA, INB by INA, INB by INA, INB
DT Dead time, RDT = 10 kΩ 80 100 120 ns
DT Dead time, RDT = 20 kΩ 160 200 240 ns
DT Dead time, RDT = 50 kΩ 400 500 600 ns

6.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB
to VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C. (over recommended operating conditions unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output rise time, 20% to 80%
tRISE COUT = 1.8 nF 6 16 ns
measured points
Output fall time, 90% to 10%
tFALL COUT = 1.8 nF 7 12 ns
measured points
tPWmin Minimum pulse width Output off for less than minimum, COUT = 0pF 20 ns
Propagation delay from INx to OUTx
tPDHL 26 33 45 ns
falling edges
Propagation delay from INx to OUTx
tPDLH 26 33 45 ns
rising edges
tPWD Pulse width distortion |tPDLH – tPDHL| 6 ns
Propagation Delay Matching for Dual Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C
tDM 6.5 ns
Channel Driver |tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|
Input Pulse Width = 100ns, 500kHz, TJ = -10°C to
Propagation Delay Matching for Dual
tDM +150°C 5 ns
Channel Driver
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|
VCCI Power-up Delay Time: UVLO
tVCCI+ to OUT INA or INB tied to VCCI 50 μs
Rise to OUTA, OUTB
VDDA. VDDB Power-up Delay Time:
tVDD+ to OUT INA or INB tied to VCCI 10 μs
UVLO Rise to OUTA, OUTB
High-level common-mode transient Slew rate of GND versus VSSA/B, INA and INB both are
|CMH| 125 V/ns
immunity (See Section 7.6) tied to GND or VCCI; VCM = 1500V
Low-level common-mode transient Slew rate of GND versus VSSA/B, INA and INB both are
|CML| 125 V/ns
immunity (See Section 7.6) tied to GND or VCCI; VCM = 1500V

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

6.11 Insulation Characteristics Curves

Figure 6-1. Reinforced Isolation Capacitor Life Time Projection

60 1800
Safety Limiting Current per Channel (mA)

IVDDA/B for VDD=15V

IVDDA/B for VDD=25V 1600
50
Safety Limiting Power (mW)

1400

40 1200

1000
30
800

20 600

400
10 200

0
0 0 20 40 60 80 100 120 140 160
0 20 40 60 80 100 120 140 160 Ambient Te mperature (°C)
Ambient Te mperature (°C)
Figure 6-3. Thermal Derating Curve for Safety-Related Limiting
Figure 6-2. Thermal Derating Curve for Safety-Related Limiting Power
Current (Current in Each Channel with Both Channels Running
Simultaneously)

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

6.12 Typical Characteristics

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

17.5 50
45
15
40
12.5 35
Current (mA)

Current (mA)
10 30
25
7.5
20
5 15
10
2.5 VDD=15V VDD=15V
VDD=25V 5 VDD=25V
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
Frequency (kHz)
Figure 6-4. Per Channel Current Consumption vs Frequency Figure 6-5. Per Channel Current Consumption (IVDDA/B) vs
(No Load, VDD = 15 V or 25 V) Frequency (1-nF Load, VDD = 15 V or 25 V)
30 14
500kHz
27 1000kHz
12
24 2000kHz
3000kHz
21 10
Current (mA)

Current (mA)

18
8
15
6
12
9 4
6
VDD=15V 2
3 VDD=25V
0 0
10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140 160
Frequency (kHz) Te mperature (°C)
Figure 6-6. Per Channel Current Consumption (IVDDA/B) vs Figure 6-7. Per Channel (IVDDA/B) Supply Current vs
Frequency (10-nF Load, VDD = 15 V or 25 V) Temperature (No Load, Different Switching Frequencies)
2 1.6

1.6
1.5
Current (mA)

Current (mA)

1.2
1.4
0.8

1.3
0.4
VDD=15V VCC=3.3V
VDD=25V VCC=5V
0 1.2
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Te mperature (°C) Te mperature (°C)
Figure 6-8. Per Channel (IVDDA/B) Quiescent Supply Current vs Figure 6-9. IVCCI Quiescent Supply Current vs Temperature (No
Temperature (No Load, Input Low, No Switching) Load, Input Low, No Switching)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

6.12 Typical Characteristics (continued)

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

30 6
Output Pull-Up
27.5 5.5
Output Pull-Down
25 5

22.5 4.5

Resistance (Ohm)
4
20
Time (ns)

3.5
17.5
3
15
2.5
12.5
2
10 1.5
tRise
7.5 tFall 1
5 0.5
1 2 3 4 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 140 160
Load (nF) Te mperature (°C)
Figure 6-10. Rising and Falling Times vs Load (VDD = 15 V) Figure 6-11. Output Resistance vs Temperature
40 36

36
34
Propagation Delay (ns)

Propagation Delay (ns)

32

32
28

30
24
Rising Edge (tPDLH) Rising Edge (tPDLH)
Falling Edge (tPDHL) Falling Edge (tPDHL)
20 28
-40 -20 0 20 40 60 80 100 120 140 160 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5
Te mperature (°C) VCCI (V)
Figure 6-12. Propagation Delay vs Temperature Figure 6-13. Propagation Delay vs VCCI
3 2

1.5
Propagation Delay Matching (ns)

2
Pulse Width Distortion (ns)

1
1
0.5

0 0

-0.5
-1
-1
-2
-1.5 Rising Edge
Falling Edge
-3 -2
-40 -20 0 20 40 60 80 100 120 140 160 15 16 17 18 19 20 21 22 23 24 25
Te mperature (°C) VDD (V)
Figure 6-14. Pulse Width Distortion vs Temperature Figure 6-15. Propagation Delay Matching (tDM) vs VDD

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

6.12 Typical Characteristics (continued)

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

2 0.8

1.5
Propagation Delay Matching (ns)

0.7
1

UVLO Hysteresis (V)

0.6
0.5

0 0.5

-0.5 0.4

-1
0.3
-1.5 Rising Edge
Falling Edge
0.2
-2
-40 -20 0 20 40 60 80 100 120 140 160
-40 -20 0 20 40 60 80 100 120 140
Te mperature (°C)
Te mperature (°C)
Figure 6-17. VDD 5-V UVLO Hysteresis vs Temperature
Figure 6-16. Propagation Delay Matching (tDM) vs Temperature
8 1
VVDD_ON
VVDD_OFF
0.9
7
UVLO Hysteresis (V)
UVLO Threshold (V)

0.8

6 0.7

0.6

5
0.5

0.4
4
-40 -20 0 20 40 60 80 100 120 140 160
-40 -20 0 20 40 60 80 100 120 140 160
Te mperature (°C)
Te mperature (°C)
Figure 6-19. VDD 8-V UVLO Hysteresis vs Temperature
Figure 6-18. VDD 5-V UVLO Threshold vs Temperature
10 0.9
VVDD_ON
VVDD_OFF
9 0.89
UVLO Threshold (V)

Hysteresis (V)

8 0.88

7 0.87

6 0.86
VCC=3.3V
VCC=5V
5 0.85
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140
Te mperature (°C) Te mperature (°C)
Figure 6-20. VDD 8-V UVLO Threshold vs Temperature Figure 6-21. IN/DIS Hysteresis vs Temperature

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

6.12 Typical Characteristics (continued)

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

1.2 2

1.14 1.92

IN/DIS High Threshold (V)

IN/DIS Low Threshold (V)

1.08 1.84

1.02 1.76

0.96 VCC=3.3V 1.68 VCC=3.3V

VCC= 5V VCC= 5V
VCC=12V VCC=12V
0.9 1.6
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) D001
Temperature (qC) D001

Figure 6-22. IN/DIS Low Threshold Figure 6-23. IN/DIS High Threshold
1500 5
RDT= 20k:
RDT= 100k:
1200 -6
Dead Time (ns)

900 -17
'DT (ns)

600 -28

300 -39
RDT= 20k:
RDT = 100k:
0 -50
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) D001 Temperature (qC) D001
Figure 6-24. Dead Time vs Temperature (with RDT = 20 kΩ and Figure 6-25. Dead Time Matching vs Temperature (with RDT = 20
100 kΩ) kΩ and 100 kΩ)
20
2.2nF Load
10nF Load
15
Y Axis Title (Unit)

10

-5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
TIME
Figure 6-26. Typical Output Waveforms

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion
Figure 7-1 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the
propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and
disabling the dead time function by shorting the DT Pin to VCC.

INA/B

tPDLHA tPDHLA
tDM
OUTA

tPDLHB tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB

Figure 7-1. Overlapping Inputs, Dead Time Disabled

7.2 Rising and Falling Time

Figure 7-2 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Section 8.3.4.

80% 90%

tRISE tFALL
20%
10%

Figure 7-2. Rising and Falling Time Criteria

7.3 Input and Disable Response Time

Figure 7-3 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low
ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more
information, see Section 8.4.1.

INA

DIS High
Response Time
DIS
DIS Low
Response Time
OUTA tPDLH
90% 90%
tPDHL

10% 10% 10%

Figure 7-3. Disable Pin Timing

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

7.4 Programable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (RDT) sets a dead-time interval. For
more details on dead time, refer to Section 8.4.2.

INA

INB

90%
OUTA 10%

tPDHL tPDLH
OUTB 90%
10%

Dead Time
tPDHL
Dead Time
(Set by RDT) (Determined by Input signals if
longer than DT set by RDT)

Figure 7-4. Dead-Time Switching Parameters

7.5 Power-up UVLO Delay to OUTPUT

Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge
to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40us) and tVDD+ to OUT for VDD UVLO (Max
10us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and
VDD bias supply is ready. Figure 7-5 and Figure 7-6 show the power-up UVLO delay timing diagram for VCCI
and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will
not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when
either VCCI or VDD receive a voltage less than their respective off thresholds, there is <2µs delay, depending on
the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to
ensure safe operation during VCCI or VDD brownouts.

VCCI, VCCI,
INx VVCCI_ON VVCCI_OFF INx

VDDx VDDx
tVCCI+ to OUT VVDD_ON tVDD+ to OUT VVDD_OFF

OUTx OUTx

Figure 7-5. VCCI Power-up UVLO Delay Figure 7-6. VDDA/B Power-up UVLO Delay

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

7.6 CMTI Testing

Figure 7-7 is a simplified diagram of the CMTI testing configuration.
VCC VDD
INA VDDA
1 16
OUTA
INB OUTA
2 15

VCC VSSA
VCCI 14

Reinforced Isolation
3

Input Logic
GND Functional
4
Isolation
DIS VDDB
5 11

DT OUTB
6 OUTB
10

VCCI VSSB
8 9

GND VSS
Common Mode Surge
Generator
Copyright © 2017, Texas Instruments Incorporated

Figure 7-7. Simplified CMTI Testing Setup

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21520, UCC21520A are flexible dual gate drivers which can be configured to fit a variety of power
supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The
UCC21520, UCC21520A have many features that allow it to integrate well with control circuitry and protect the
gates it drives such as: resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock
out (UVLO) for both input and output voltages. The UCC21520 and the UCC21520A also hold its outputs low
when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and
TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its
respective input pins (INA and INB), allowing full and independent control of each of the outputs.
8.2 Functional Block Diagram

INA 1 16 VDDA

200 k Driver
VCCI MOD DEMOD Deglitch
Filter 15 OUTA
UVLO
VCCI 3,8 UVLO
14 VSSA
Reinforced Isolation

GND 4
13 NC
Deadtime Functional Isolation
DT 6 Control 12 NC

DIS 5
11 VDDB
200 k
Driver
MOD DEMOD Deglitch
Filter 10 OUTB
UVLO
INB 2
9 VSSB
200 k
NC 7

Copyright © 2024, Texas Instruments Incorporated

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

8.3 Feature Description

8.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
The UCC21520 and the UCC21520A have an internal undervoltage lock out (UVLO) protection feature on the
supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower
than V VDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected
output low, regardless of the status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by
an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 8-1). In this condition,
the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through
RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS
device, typically around 1.5 V, when no bias power is available.

VDD
RHI_Z

Output
OUT
Control
RCLAMP

RCLAMP is activated
during UVLO VSS

Figure 8-1. Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is
bound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21520 and the UCC21520A also has an internal undervoltage lock out (UVLO)
protection feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And
a signal will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO
for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

All versions of the UCC21520 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.
Table 8-1. UCC21520 and UCC21520A VCCI UVLO Feature Logic
INPUTS OUTPUTS
CONDITION
INA INB OUTA OUTB
VCCI-GND < VVCCI_ON during device start up H L L L
VCCI-GND < VVCCI_ON during device start up L H L L
VCCI-GND < VVCCI_ON during device start up H H L L
VCCI-GND < VVCCI_ON during device start up L L L L
VCCI-GND < VVCCI_OFF after device start up H L L L
VCCI-GND < VVCCI_OFF after device start up L H L L
VCCI-GND < VVCCI_OFF after device start up H H L L
VCCI-GND < VVCCI_OFF after device start up L L L L

Table 8-2. UCC21520 and UCC21520A VDD UVLO Feature Logic

INPUTS OUTPUTS
CONDITION
INA INB OUTA OUTB
VDD-VSS < VVDD_ON during device start up H L L L
VDD-VSS < VVDD_ON during device start up L H L L
VDD-VSS < VVDD_ON during device start up H H L L
VDD-VSS < VVDD_ON during device start up L L L L
VDD-VSS < VVDD_OFF after device start up H L L L
VDD-VSS < VVDD_OFF after device start up L H L L
VDD-VSS < VVDD_OFF after device start up H H L L
VDD-VSS < VVDD_OFF after device start up L L L L

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

8.3.2 Input and Output Logic Table

Table 8-3. INPUT/OUTPUT Logic Table (1)
Assume VCCI, VDDA, VDDB are powered up. See Section 8.3.1 for more information on UVLO operation modes.
INPUTS OUTPUTS
DISABLE NOTE
INA INB OUTA OUTB
L L L L L
If Dead Time function is used, output transitions occur after the
L H L L H
dead time expires. See Section 8.4.2
H L L H L
H H L L L DT is left open or programmed with RDT
H H L H H DT pin pulled to VCCI
Left Open Left Open L L L -
X X H or Left Open L L -

(1) "X" means L, H or left open.

8.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC21520 and the UCC21520A are based on a TTL and CMOS
compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to
drive with logic-level control signals (such as those from 3.3-V micro-controllers), since the UCC21520 and the
UCC21520A have a typical high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little
with temperature (see Figure 6-22, Figure 6-23). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise
immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin
low. These resistors are typically 200 kΩ (see Section 8.2). However, it is still recommended to ground an input if
it is not being used.
Since the input side of the UCC21520 and the UCC21520A is isolated from the output drivers, the input signal
amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows
greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient
VDD for their chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a
voltage higher than VCCI.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

8.3.4 Output Stage

The UCC21520 and the UCC21520A output stages feature a pull-up structure which delivers the highest peak-
source current when it is most needed, during the Miller plateau region of the power-switch turn on transition
(when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features
a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by
briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to
high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on
only for a brief instant when the output is changing states from low to high. Therefore the effective resistance
of the UCC21520and the UCC21520A pull-up stage during this brief turn-on phase is much lower than what is
represented by the ROH parameter. Therefore, the value of ROH belies the fast nature of the UCC21520 and the
UCC21520A's turn-on time.
The pull-down structure in the UCC21520 and the UCC21520A is simply composed of an N-channel MOSFET.
The ROL parameter, which is also a DC measurement, is representative of the impedance of the pull-down
state in the device. Both outputs of the UCC21520 and the UCC21520A are capable of delivering 4-A peak
source and 6-A peak sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail
operation, thanks to the MOS-out stage which delivers very low drop-out.
To ensure robust and reliable operation of gate drivers, pay special attention to the minimum pulse width.
The minimum pulse width shown in the electrical characteristics table describes the minimum input pulse that
would be passed to the output in an unloaded driver. This is dictated by the deglitch filter present in the
driver IC. An input ON or OFF pulse width longer than the maximum specification is needed to guarantee an
output state change and avoid potential shoot-through. With a loaded driver, extra precaution must be taken
to ensure robust operation of the system. During gate switching, if the output state changes before the driver
completes each transition, a non-zero current switching event occurs. Combined with layout parasitics, non-zero
current switching can cause internal rail overshoot and EOS damage of the gate driver. Thus, a minimum
output width is needed for reliable system operation. This minimum output pulse width is dependent on several
factors: gate capacitance, VDD supply voltage, gate resistance, and PCB layout parasitics. The minimum pulse
width for robust operation might be magnitudes larger than the minimum pulse width shown in the electrical
characteristics table. System-level study should be carried out to determine the minimum output pulse width
required for each system.

VDD

ROH
Shoot-
RNMOS
Input Through
OUT
Signal Prevention
Circuitry ROL
Pull Up

VSS

Figure 8-2. Output Stage

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

8.3.5 Diode Structure in the UCC21520 and the UCC21520A

Figure 8-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21520 and the
UCC21520A. This provides a pictorial representation of the absolute maximum rating for the device.

Figure 8-3. ESD Structure

8.4 Device Functional Modes

8.4.1 Disable Pin
Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE
pin allows the UCC21520 and the UCC21520A to operate normally. The DISABLE response time is in the range
of 20 ns and quite responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and
necessary) when VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the
DISABLE pin is not used to achieve better noise immunity, and it is recommended to bypass using a ≈1-nF low
ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

8.4.2 Programmable Dead-Time (DT) Pin

The UCC21520 and the UCC21520A allow the user to adjust dead time (DT) in the following ways:
8.4.2.1 Tying the DT Pin to VCC
Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.
8.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
One can program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can
be determined from Equation 1, where RDT is in kΩ and tDT is in ns:

tDT » 10 ´ RDT (1)

The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when
RDT=100kΩ. When using RDT> 5kΩ, it is recommended to parallel a ceramic capacitor, ≤1nF, close to the
chip with RDT to achieve better noise immunity and better dead time matching between two channels. It is not
recommended to leave the DT pin floating.
An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead
time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.
If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent
shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead
time logic operating conditions are illustrated and explained in:

INA

INB

DT

OUTA

OUTB

A B C D E F

Figure 8-4. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,
when INA goes high, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it
immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls
OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to
OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls
OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to
OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The UCC21520 or the UCC21520A effectively combines both isolation and buffer-drive functions. The flexible,
universal capability of the UCC21520 and the UCC21520A (with up to 18-V VCCI and 25-V VDDA/VDDB) allows
the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or
SiC MOSFETs. With integrated components, advanced protection features (UVLO, dead time, and disable) and
optimized switching performance; the UCC21520 and the UCC21520A enables designers to build smaller, more
robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in Figure 9-1 shows a reference design with the UCC21520 driving a typical half-bridge configuration
which could be used in several popular power converter topologies such as synchronous buck, synchronous
boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VDD
VCC RBOOT
HV DC-Link

VCC
INA VDDA ROFF
PWM-A 1 16

OUTA RON CIN

RIN INB
PWM-B 2 15
CBOOT
VSSA RGS
VCCI 14
Reinforced Isolation

CIN 3
C CVCC SW
Input Logic

GND Functional
4
Isolation VDD
Analog DIS
Disable VDDB
or 5 11 ROFF
Digital

1nF DT OUTB RON
RDIS 6 10
CVDD
VCCI RGS
RDT VSSB
8 9

VSS Copyright © 2024, Texas Instruments Incorporated

Figure 9-1. Typical Application Schematic

26 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

9.2.1 Design Requirements

Table 9-1 lists reference design parameters for the example application: UCC21520 driving 1200-V SiC-
MOSFETs in a high side-low side configuration.
Table 9-1. UCC21520 Design Requirements
PARAMETER VALUE UNITS
Power transistor C2M0080120D -
VCC 5.0 V
VDD 20 V
Input signal amplitude 3.3 V
Switching frequency (fs) 100 kHz
DC link voltage 800 V

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.2 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the
loss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage
is 800 VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good
margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.
When designing a bootstrap supply, it is recommended to use a bootstrap resistor, RBOOT. A bootstrap resistor,
is also used to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VDDA-VSSA
during each switching cycle.
Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET and UCC21520
may result in permanent damage to the device in certain cases.
The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode used. In the example, a
current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst
case peak current through DBoot is,

VDD VBDF 20V 2.5V

IDBoot pk | 8A
RBoot 2.2: (2)

where
• VBDF is the estimated bootstrap diode forward voltage drop at 8 A.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to:
1. Limit ringing caused by parasitic inductances/capacitances.
2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4. Reduce electromagnetic interference (EMI).
As mentioned in Section 8.3.4, the UCC21520 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:

§ VDD VBDF ·
IOA min ¨ 4A, ¸
¨ RNMOS || ROH RON RGFET _ Int ¸¹
© (3)

§ VDD ·
IOB min ¨ 4A, ¸
¨ R || R RON RGFET _ Int ¸¹
© NMOS OH (4)

where
• RON: External turn-on resistance.
• RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
• IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
In this example:

VDD VBDF 20V 0.8V

IOA | 2.4A
RNMOS || ROH RON RGFET _ Int 1.47: || 5: 2.2: 4.6: (5)

VDD 20V
IOB | 2.5A
RNMOS || ROH RON RGFET _ Int 1.47: || 5: 2.2: 4.6: (6)

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:

§ VDD VBDF VGDF ·

IOA min ¨ 6A, ¸
¨ ROL ROFF || RON RGFET _ Int ¸¹
© (7)

§ VDD VGDF ·
IOB min ¨ 6A, ¸
¨ ROL ROFF || RON RGFET _ Int ¸¹
© (8)

where
• ROFF: External turn-off resistance;
• VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is
an MSS1P4.
• IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.

28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

In this example,

VDD VBDF VGDF 20V 0.8V 0.75V

IOA | 3.6A
ROL ROFF || R ON R GFET _ Int 0.55: 0: 4.6: (9)

VDD VGDF 20V-0.75V

IOB | 3.7A
ROL ROFF || R ON RGFET _ Int 0.55: 0: 4.6: (10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the
power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close
to the parasitic ringing period.
Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including
transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing,
it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added
in the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx
voltages.
9.2.2.4 Gate to Source Resistor Selection
A gate to source resistor, RGS, is recommended to pull down the gate to the source voltage when the gate driver
output is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of dv/dt induced
turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically
sized between 5.1kΩ and 20kΩ, depending on the Vth and ratio of CGD to CGS of the power device.
9.2.2.5 Estimate Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21520 (PGD) and the
power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not
included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21520, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well
as driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 6-4 shows the per output channel current consumption vs operating frequency
with no load. In this example, VVCCI = 5 V and VVDD = 20 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI = 2.5 mA, and IVDDA = IVDDB = 1.5 mA. Therefore,
the PGDQ can be calculated with

PGDQ VVCCI u IVCCI VVDDA u IDDA VVDDB u IDDB | 72mW (11)

The second component is switching operation loss, PGDO, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW,
can be estimated with

PGSW 2 u VDD u QG u fSW (12)

where

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

• QG is the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:

PGSW 2 u 20V u 60nC u 100kHz 240mW (13)

QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change
with different testing conditions. The UCC21520 gate driver loss on the output stage, PGDO, is part of PGSW.
PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss is
dissipated inside the UCC21520. If there are external turn-on and turn-off resistances, the total loss will be
distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the
pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,
however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two
scenarios.
Case 1 - Linear Pull-Up/Down Resistor:

PGSW § ROH || RNMOS ROL ·

PGDO u¨ ¸
2 ¨ ROH || RNMOS RON RGFET _ Int ROL ROFF || RON RGFET _ Int ¸
© ¹
(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520
gate driver loss can be estimated with:

240mW § 5: || 1.47: 0.55: ·

PGDO u¨ ¸ | 30mW
2 © 5: || 1.47: 2.2: 4.6: 0.55: 0: 4.6: ¹ (15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

ª TR _ Sys TF _ Sys
º
PGDO 2 u fSW u « 4A u ³ VDD VOUTA/B t dt 6A u ³ VOUTA/B t dt »
¬« 0 0 ¼» (16)

where
• VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the
PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up
and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver
UCC21520, PGD, is:

PGD PGDQ PGDO (17)

which is equal to 102 mW in the design example.

9.2.2.6 Estimating Junction Temperature
The junction temperature (TJ) of the UCC21520 can be estimated with:

TJ = TC + Y JT ´ PGD (18)

30 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

where
• TC is the UCC21520 case-top temperature measured with a thermocouple or some other instrument, and
• ΨJT is the Junction-to-top characterization parameter from the Thermal Information table.
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package
Thermal Metrics Application Report.
9.2.2.7 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC)
with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an
MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only
500 nF when a DC bias of 15 VDC is applied.
9.2.2.7.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for
this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with

IVDD @100kHz No Load 1.5mA

QTotal QG 60nC 75nC
fSW 100kHz (19)

where
• QTotal: Total charge needed
• QG: Gate charge of the power transistor.
• IVDD: The channel self-current consumption with no load at 100kHz.
• fSW: The switching frequency of the gate driver
Therefore, the absolute minimum CBoot requirement is:

QTotal 75nC
CBoot 150nF
'VVDDA 0.5V (20)

where
• ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

CBoot 1 ) (21)

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not
drop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor
should be sized such that it can supply the initial charge to switch the power device, and then continuously
supply the gate driver quiescent current for the duration of the high-side on-time.
If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turn
off and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and high
dv/dt transients on the output of the driver and may result in permanent damage to the device.
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor
placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is
placed in parallel with CBoot to optimize the transient performance.

Note
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could
stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during
initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.

32 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

9.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in
Figure 9-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,
with a value over 10 µF, should be used in parallel with CVDD.
9.2.2.8 Dead Time Setting Guidelines
For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor
is important for preventing shoot-through during dynamic switching.
The UCC21520 dead time specification in the electrical table is defined as the time interval from 90% of one
channel’s falling edge to 10% of the other channel’s rising edge (see Figure 7-4). This definition ensures that
the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.
However, this dead time setting may not reflect the dead time in the power converter system, since the dead
time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as
well as the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC21520:

DTSetting DTReq TF _ Sys TR _ Sys TD on

(22)

where
• DTsetting: UCC21520 dead time setting in ns, DTSetting = 10 × RDT(in kΩ).
• DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough
margin, or ZVS requirement.
• TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
• TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
• TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.
In the example, DTSetting is set to 250 ns.
It should be noted that the UCC21520 dead time setting is decided by the DT pin configuration (see Section
8.4.2), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to
parallel a ceramic capacitor, ≤1nF, close to the DT pin with RDT to achieve better noise immunity.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

9.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example,
TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power
transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of
unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep
such ringing below the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 9-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
VDDA ROFF
1 16
CA1 +
RZ 25 V VA RON CIN
OUTA ±
2 15
CA2
VSSA
Reinforced Isolation

3 14
VZ = 5.1 V
Input Logic

Functional SW
4
Isolation

5 VDDB
11

6 OUTB
10
Copyright © 2017, Texas Instruments Incorporated
VSSB
8 9

Figure 9-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

34 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

Figure 9-3 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.

VDDA HV DC-Link
16 ROFF
1 CA1 +
VA+ RON
OUTA ± CIN
2 15
CA2 +
VSSA VA-
Reinforced Isolation

3 ±
14
Input Logic

4 Functional
Isolation SW

5 VDDB
11

6 OUTB
10

VSSB Copyright © 2017, Texas Instruments Incorporated

8 9

Figure 9-3. Negative Bias with Two Iso-Bias Power Supplies

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

The last example, shown in Figure 9-4, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply
and the bootstrap power supply can be used for the high side drive. This design requires the least cost and
design effort among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which
means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a
fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors favor this
solution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in
the other two example circuits.
VDD
RBOOT

HV DC-Link
VDDA CZ ROFF
1 16

OUTA VZ RON CIN

2 15
CBOOT RGS
VSSA
14
Reinforced Isolation

3
Input Logic

Functional SW
4
Isolation VDD

5 VDDB CZ ROFF
11

OUTB VZ RON
6 10
CVDD RGS
VSSB
8 9

VSS Copyright © 2017, Texas Instruments Incorporated

Figure 9-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

36 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

9.2.3 Application Curves

Figure 9-5 and Figure 9-6 shows the bench test waveforms for the design example shown in Figure 9-1 under
these conditions: VCC = 5 V, VDD = 20 V, fSW = 100 kHz, VDC-Link = 0 V.
Channel 1 (Yellow): UCC21520 INA pin signal.
Channel 2 (Blue): UCC21520 INB pin signal.
Channel 3 (Pink): Gate-source signal on the high side power transistor.
Channel 4 (Green): Gate-source signal on the low side power transistor.
In Figure 9-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on
the power transistor have a 250-ns dead time, shown in the measurement section of Figure 9-5. The dead-time
matching is less than 1 ns with the 250-ns dead-time setting.
Figure 9-6 shows a zoomed-in version of the waveform of Figure 9-5, with measurements for propagation
delay and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is
measured between the power transistors’ gate and source pins, and is not measured directly from the driver
OUTA and OUTB pins. Due to the split on and off resistors (Ron,Roff) and different sink and source currents,
different rising (16 ns) and falling time (9 ns) are observed in Figure 9-6.

Figure 9-5. Bench Test Waveform for INA/B and Figure 9-6. Zoomed-In Bench Test Waveform
OUTA/B

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21520 and the UCC21520A is between 3 V and 18
V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21520 one is using.
The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection
feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more
information on UVLO see Section 8.3.1). The upper end of the VDDA/VDDB range depends on the maximum
gate voltage of the power device being driven by the UCC21520 and the UCC21520A. The UCC21520 and the
UCC21520A have a recommended maximum VDDA/VDDB of 25 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further
suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional
≤100-nF capacitor in parallel for high frequency filtering.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount
of current drawn by the logic circuitry within the input side of the UCC21520 and the UCC21520A, this bypass
capacitor has a minimum recommended value of 100 nF.

38 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

11 Layout
11.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520 and the
UCC21520A. Below are some key points.
Component Placement:
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be minimized.
• It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of
the UCC21520 or the UCC21520A.
• It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to
a µC with distance.
Grounding Considerations:
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-
referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor
is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
High-Voltage Considerations:
• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination
that may compromise the isolation performance of the UCC21520 and the UCC21520A.
• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could
operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB
layout between the high and low-side PCB traces.
Thermal Considerations:
• A large amount of power may be dissipated by the UCC21520 or the UCC21520A if the driving voltage is
high, the load is heavy, or the switching frequency is high (refer to Section 9.2.2.5 for more details). Proper
PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal
impedance (θJB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 11-2 and Figure 11-3). However, high voltage
PCB considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind
that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

11.2 Layout Example

Figure 11-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 11-1. Layout Example

Figure 11-2 and Figure 11-3 shows top and bottom layer traces and copper.

Note
There are no PCB traces or copper between the primary and secondary side, which ensures isolation
performance.

40 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 11-2. Top Layer Traces and Copper Figure 11-3. Bottom Layer Traces and Copper

Note
The location of the PCB cutout between the primary side and secondary sides, which ensures
isolation performance.

Figure 11-4. 3-D PCB Top View Figure 11-5. 3-D PCB Bottom View

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

12 Device and Documentation Support

12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Semiconductor and IC Package Thermal Metrics Application Report
• Isolation Glossary
12.3 Certifications
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate
Number: 20160516-E181974,
VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance
CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate
Number:CQC16001155011
CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master
Contract Number:220991
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

42 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 UCC21520, UCC21520A
www.ti.com SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024

Changes from Revision E (December 2021) to Revision F (November 2024) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Deleted 5ns maximum delay matching from Features section...........................................................................1
• Changed Typ propagation delay from 19ns to 33ns...........................................................................................1
• Changed 10ns minmum pulse width to 20ns......................................................................................................1
• Changed operating temperature range to junction temeperature range............................................................ 1
• Changed CMTI specification from 100V/ns to 125V/ns......................................................................................1
• Changed surge immunity value from 12.8kV to 10kV........................................................................................ 1
• Deleted bullet on isolation barrier life >40 years................................................................................................ 1
• Deleted "Rejects input pulses and noise transients shorter than 5ns"............................................................... 1
• Updated safety certifications to latest standards................................................................................................ 1
• Deleted CSA certification....................................................................................................................................1
• Updated Description section to match new spec values.................................................................................... 1
• Updated DT pin description to recommend ≤1nF capacitor on DT pin...............................................................4
• Changed DT pin Min resistor recommendations from 500Ω to 2kΩ...................................................................4
• Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD
industry standards.............................................................................................................................................. 5
• Deleted ambient temperature spec.................................................................................................................... 5
• Changed Max junction temp to 150C................................................................................................................. 5
• Updated values from RθJA = 67.3°C/W, RθJC(top) = 34.4°C/W, RθJB = 32.1°C/W, ψJT = 18°C/W, ψJB =
31.6°C/W to RθJA = 69.8°C/W, RθJC(top) = 33.1°C/W, RθJB = 36.9°C/W, ψJT = 22.2°C/W, ψJB = 36°C/W.. 5
• Updated values from PD = 1.05W, PDI = 0.05W, PDA/PDB = 0.5W to PD = 950mW, PDI = 50mW, PDA/PDB
= 450mW............................................................................................................................................................ 6
• Updated values from DTI = 21mm, VIOSM = 8000VPK to DTI = 17mm, VIOSM = 10000VPK and added
VIMP = 7692VPK................................................................................................................................................7
• Deleted safety related certifications section....................................................................................................... 7
• Updated values from IS = 75mA/36mA, PS = 50mW/900mW/900mW/1850mW to IS = 58mA/34mA, PS =
50mW/870mW/870mW/1790mW....................................................................................................................... 8
• Changed test condition from VDDA=VDDB=12V to VDDA=VDDB=15V........................................................... 8
• Updated IVCCI quiescent current spec 1.4mA typical value to 1.5mA typical................................................... 8
• Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mA............................................ 8
• Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mA..................... 8
• Added IVDDA/IVDDB operating current Max = 4.2mA.......................................................................................8
• Updated values from Rising threshold Min = 8.3V, Typ = 8.7V, Max = 9.2V to Min = 7.7V, Typ = 8.5V, Max =
8.9V.................................................................................................................................................................... 8
• Updated values from Falling threshold Min = 7.8V, Typ = 8.2V, Max = 8.7V to Min = 7.2V, Typ = 7.9V, Max =
8.4V.................................................................................................................................................................... 8
• Updated 8-V UVLO hysteresis typ = 0.5V to 0.6V..............................................................................................8
• Updated Input high threshold Min value from 1.6V to 1.2V................................................................................8
• Changed output voltage at high state spec from 11.95V Typ to 14.95V Typ. Changed test condition from
VDDA=VDDB=15V to VDDA=VDDB=12V. ........................................................................................................8
• Deleted Dead time parameter from Electrical Characteristics and added new Timing Requirements............... 9
• Changed propagation delay TPDHL and TPDLH from Min=14ns, Typ = 19ns, Max = 30ns to Min=26ns. Typ =
33ns, Max = 45ns............................................................................................................................................... 9
• Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns
from TJ = -10C to 150C......................................................................................................................................9
• Added VCCI power up delay.............................................................................................................................. 9
• Updated VDDA/VDDB power-up delay from Max = 100us to 10us....................................................................9
• Updated CMTI from Min = 100V/ns to 125V/ns..................................................................................................9
• Updated insulation and thermal curves to match updated characteristics....................................................... 10
• Updated typical characteristics figures............................................................................................................. 11
• Updated Power-up UVLO Delay to OUTPUT section to match device electrical characteristics .................... 16
• Changed the Functional Block Diagram to add deglitch filter block................................................................. 18

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43

Product Folder Links: UCC21520 UCC21520A
UCC21520, UCC21520A
SLUSCJ9F – JUNE 2016 – REVISED NOVEMBER 2024 www.ti.com

• Changed DISABLE logic; DISABLE left open will pull outputs low...................................................................21
• Added paragraph on minimum pulse width to Output Stage section................................................................22
• Updated ESD diode structure...........................................................................................................................23
• Updated DT Pin Connected to a Programming Resistor Between DT and GND Pins section to recommend
<=1nF capacitor on DT pin. .............................................................................................................................24
• Updated typical schematic DT pin capacitor recommendation ........................................................................26
• Updated Dead Time Setting Guidelines section to recommend <=1nF capacitor on DT pin. ......................... 33

Changes from Revision D (March 2020) to Revision E (December 2021) Page

• Updated Features ..............................................................................................................................................1

Changes from Revision C (December 2019) to Revision D (March 2020) Page

• Changed DT pin description............................................................................................................................... 4
• Changed DT pin configuration recommendations ........................................................................................... 24
• Added update to bootstrap circuit recommendations....................................................................................... 27
• Added update to gate resistor selection recommendations .............................................................................28
• Added gate to source resistor recommendation ..............................................................................................29
• Added update to Cboot selection recommendations .......................................................................................31

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

44 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21520 UCC21520A

 PACKAGE OPTION ADDENDUM

www.ti.com 7-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

UCC21520ADW Obsolete Production SOIC (DW) | 16 - - Call TI Call TI -40 to 125 UCC21520A
UCC21520ADWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520A
UCC21520DW Obsolete Production SOIC (DW) | 16 - - Call TI Call TI -40 to 125 UCC21520
UCC21520DWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC21520 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 7-May-2025

• Automotive : UCC21520-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC21520ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UCC21520DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC21520ADWR SOIC DW 16 2000 356.0 356.0 35.0
UCC21520DWR SOIC DW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated