UNIT-4

The Memory Organization:

Basic Concepts:
The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
For example, a 16-bit computer that generates 16-bit addresses is capable of
addressing upto 216 =64K memory locations.
 If a machine generates 32-bit addresses, it can access upto 232 = 4G memory
locations. This number represents the size of address space of the computer.
If the smallest addressable unit of information is a memory word, the
machine iscalled word-addressable.
If individual memory bytes are assigned distinct addresses, the
computer is called byte-addressable.
Most of the commercial machines are byte- addressable.
For example in a byte-addressable 32-bit computer, each memory
wordcontains 4 bytes. A possible word-address assignment would be:
 Basic Concepts of Memory
 The speed of the memory is determined by the address sequencing
 For example if a computer generates instructions with 16-bit addresses, then the memory
consists of 216=64K memory locations
 If the address is 32-bit then it consists of 232=4G memory locations
 If the address is 40-bits then it consists of 240 =1 T memory locations
 The memory is designed to store and retrieve data in word length
 Word length means the number of bits stored or retrieved in one memory access
 For example when a 32-bit address is sent from processor then the high order 30 bits determines
which word will be accessed and low order 2 bits specifies which byte location is involved
From the system standpoint, the Main Memory (MM) unit can be viewed as a “block
box”.
Data transfer between CPU and MM takes place through the use of two CPU registers,
usually called MAR (Memory Address Register) and MDR (Memory Data Register).
If MAR is K bits long and MDR is ‘n’ bits long, then the MM unit may contain upto 2k
addressable locations and each location will be ‘n’ bits wide, while the word length is
equal to ‘n’ bits.
During a “memory cycle”, n bits of data may be transferred between the MM and CPU.
This transfer takes place over the processor bus, which has k address lines (address bus),
n data lines (data bus) and control lines like Read, Write, Memory Function completed
(MFC), Bytes specifiers etc (control bus).
For a read operation, the CPU loads the address into MAR, set READ to 1 and sets other
control signals if required.
The data from the MM is loaded into MDR and MFC is set to 1.
For a write operation, MAR, MDR are suitably loaded by the CPU, write is set to 1 and
other control signals are set suitably. The MM control circuitry loads the data into
appropriate locations and sets MFC to 1.
 Memory
K-Bit address bus Upto 2k
MAR
addressable
Processor n-Bit data bus locations
Word
MDR Length= n
bits

Control Lines
( R/W, MFC etc )
[Connection of the memory to the processor]
 Data transfer between processor and memory can be performed with two registers MAR and
MDR
 If MAR is ‘K’ bit register and MDR is ‘n’ bit register then memory consists of 2k stored locations
 During the data transfer the data can be interms of n-bits
 The two control lines R/W and MFC (Memory Function Completed) are used to control the data
transfers
 Other control lines used to indicate how many bytes of data can be transferred
 In the case of read operation the processor loads the location into MAR and sets the R/W line to 1
then memory reads the data in that location and then it places the data on the data lines and also it
activates the MFC signal
 After receiving the MFC signal, the processor reads the data and then load it into MDR
 In the case of write operation the processor stores the address into MAR and the data can be
written into MDR and also sets the R/W line to ‘0’
 The speed of the memory is measured interms of memory access time i.e it is the time difference
between the times of initiation of one operation and completion of that operation
SEMI CONDUCTOR RAM MEMORIES:
Semi-Conductor memories are available is a wide range of speeds.
Their cycle time ranges from 100ns to 10ns.
First introduced in the late 1960s, they were much more expensive. But now they are
very cheap, and used almost exclusively in implementing main memories.
STATIC MEMORIES:
Memories that consist of circuits capable of retaining their state as long as power is
applied are known as static memory.
Static random-access memory (SRAM) is a type of semiconductor memory that uses
bistable latching circuitry to store each bit.
The term static differentiates it from dynamic
RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence, but
is still volatile in the conventional sense that data is eventually lost when the memory is
not powered.
The following figure shows the implementation of static RAM.
Two inverters are cross connected to form a latch. The latch is connected to two bit
lines by transistors T1 and T2. These transistors act as switches that can be opened
/ closed under the control of the word line. When the word line is at ground level,
the transistors are turned off and the latch retains its state.
Read Operation:
In order to read the state of the SRAM cell, the word line is activated to close
switches T1and T2.
If the cell is in state 1, the signal on bit line b is high and the signal on the bit line
bꞌ is low. Thus b and bꞌ are complement of each other.
Sense / write circuit at the end of the bit line monitors the state of b and bꞌ and
set the output according.
Write Operation:
The state of the cell is set by placing the appropriate value on bit line b and its
complement on bꞌ and then activating the word line. This forces the cell into the
corresponding state.
The required signal on the bit lines are generated by Sense / Write circuit.
Read Only Memories (ROM):
 Both SRAM and DRAM chips are volatile, which means that they lose the stored information if power is
turned off.
 Many applications require Non-volatile memory (which retains the stored information if power is turned
off).
E.g.:
 Operating System software has to be loaded from disk to memory which requires the program that boots
the Operating System. i.e., it requires non-volatile memory.
 Non volatile memory is used in embedded system.
 Since the normal operation involves only reading of stored data, a memory of this type is called ROM.

ROM cell
 At Logic value ‗0‘ → Transistor (T) is connected to the ground point (P).
Transistor switch is closed and voltage on bit line nearly drops to zero.
 At Logic value ‗1‘ → Transistor switch is open. The bit line remains at high
voltage. To read the state of the cell, the word line is activated. A Sense circuit at
the end of the bit line generates the proper output value.
Different types of non-volatile memory are:
• PROM
• EPROM
• EEPROM
• Flash Memory
PROM (Programmable read-only memory):
PROM is a form of digital memory. In this type of ROM, each bit is locked by a fuse or
anti-fuse.
The data stored in it are permanently stored and can not be changed or erasable. It is
used in low-level programs such as firmware or microcode.
EPROM (Erasable programmable read-only memory):
EPROM also called EROM, is a type of PROM but it can be reprogrammed.
The data stored in EPROM can be erased and reprogrammed again by ultraviolet light.
Reprogrammed it is limited.
Before the era of EEPROM and flash memory, EPROM was used in microcontrollers.
EEPROM (Electrically erasable programmable read-only memory):
As its name refers, it can be programmed and erased electrically.
The data and program of this ROM can be erased and programmed about ten thousand
times.
The duration of erasing and programming of the EEPROM is about 4ms to 10ms. It is
used in microcontrollers and remote keyless systems.
FLASH MEMORY:
 In EEPROM, it is possible to read and write the contents of a single cell.
 In Flash device, it is possible to read the contents of a single cell but it is only
possible to write the entire contents of a block.
Prior to writing, the previous contents of the block are erased.
E.g.: In MP3 player, the flash memory stores the data that represents sound.
SPEED, SIZE AND COST

Magnetic Disk:
A huge amount of cost effective storage can be provided by magnetic disk.
 MEMORY HIERARCHY
Increasing Size Processor Increasing Speed Increasing cost per bit

Registers

Primary
Cache L1
Processor

Secondary Cache L2

Main Memory

Magnetic Disk
Secondary Memory
 The above figure shows the hierarchy of memory management
 The processor consists of registers and primary cache L1
 For the fast accessing, the data is placed in processor registers
 The next level of hierarchy a small amount of memory that can be implemented on the processor
chip, this memory called a processor cache
 It holds the copies of instructions and data stored in main memory
There are two levels of cache
 A primary cache is located on processor
 A secondary cache is placed between primary memory and rest of the memory
 It is implemented using S-RAM chips
 The next level is main memory, it is much larger but slower than the cache memory
 Generally, the access time for the main memory is 10 times longer than the access time for cache
memory
 Disk devices provides a huge amount of inexpensive storage, they very slow
 It includes Magnetic Disk, Magnetic Tape, CD-ROM etc.

 CACHE MEMORY
The devices that provide back-up storage are called auxiliary memory devices

Magnetic Tapes I/O Processor Main Memory

Magnetic Disks
CPU Cache Memory

 If the active portions of the program and data are placed in a fast and small memory, then the
average memory access time can be reduced
 Thus, reducing the total execution time of the program
 A small fast memory is called cache memory
 It is placed between CPU and rest main memory
 The cache memory access time is less than the access time of main memory by a factor of 5-10
 When CPU needs to access memory, first the cache is examined
 If the word is found in the cache, then it is read from the cache
 If the word is not present in the cache, then it is read from main memory and a copy of it is stored
in cache memory
 The performance of cache memory is measured interms of hit ratio

Number of hits
Hit Ratio = * 100
Number of Read/Write Cycles
 If the required word is present in the cache, then it is said to be a hit
 If the required word is not present in the cache, then it is said to be a miss
 MAPPING PROCEDURE
 The transformation of data from main memory to cache memory is called mapping
 There are three types of mapping procedures
1. Associative Mapping
2. Direct Mapping
3. Set Associative Mapping
1. Associative Mapping:
CPU Address (15 Bits)

Argument Register

Address Data
01000 3450
02777 6710
22345 1234
 The associative memory stores both the address and contents of memory word
 If the required word is searched based on the content rather than its address is called Associative
mapping
 In the associative mapping, the data can be placed along with address
 The address is in terms of 5 digit octal number and the data is in terms of 4 digit octal number
 For getting the required word, CPU address of 15-bits is placed in the argument register
 Associative mapping is searched for a matching address
 If the address is found, then the corresponding 12-bit data is read and sent to CPU
 If there is no match, then the main memory is accessed and a copy of it is stored in cache
memory
2. Direct Mapping
6 Bits 9 Bits

TAG INDEX

00 000 000
32K X 12 Main 512 X 12
Memory Cache Memory
Octal Address=15 Bits Octal Address=9 Bits
Data=12 Bits Data=12 Bits
Address Address
77 777 777
 The CPU address of 15 bits is divided into two fields
 The 9 least significant bits represents index field and the remaining 6 bits represents tag field
 The figure shows for accessing the main memory it requires both the tag and index fields
 For accessing the cache memory, it requires only the index field
Memory Address Index Address
MEMORY DATA TAG DATA
00000
1220 00 1220
000
00777
2340
01000
3450

01777 777 02 6710

4560
02000 5670 b) Cache Memory

02777 6710
a) Main Memory
 Each word in the cache consists of data word and the data word corresponding tag
 When the new word is brought into cache, the tag bits are stored along with the data bits
 When the CPU generate a memory request, the index field is used for accessing the cache
 The tag field of the CPU address is compared with the tag in the word read from cache
 If the two tags match then there is a hit and the desired data word is in the cache
 If there is no match then there is a miss and the desired word is read from main memory, then it
is stored in cache together with the new tag, replacing the previous value
 The disadvantage of direct mapping is the hit ratio can drop if two or more words whose address
has the same index but different tags are accessed repeatedly
Eg:
 The word at address 0 is presently stored in the cache (Index=000, tag=00, data1220)
 Suppose the CPU wants to access the word at address 02000, the index address is 000, so it is
used to access the cache. The two tags are then compared
 The cache tag is 00 but the address tag is 02, which does not produce a match
 Therefore the main memory is accessed and the data word 5670 is transferred to CPU
3. Set Associative Mapping:

Index
TAG DATA TAG DATA
000 01 3450 02 5670

02 6710 00 2340
777
 In this technique, each word of cache can store two or more words of memory under the same
index
 Each data word is stored together with its tag and the number of tag data items in one word of
cache is said to form set
 In the above figure, each index address refers to two data words and their tags
 Each tag requires 6-bits and each data word has 12-bits
 So, the word length is 2(6+12)=36 Bits
Performance Considerations
 The success of a computer depends upon the performance and cost.
 For best performance, the cost should be less.
Performance depends on how fast machine instructions can be brought into the
processor, for execution and how fast they can be executed.
Interleaving:

a. Consecutive words in a module. b. Consecutive words in consecutive modules.

The main memory module has its address buffer register(ABR) and data buffer
register(DBR).
The memory access operations can be performed in more than one module at
the same time thus we can increase the data transmission.
The first figure show shows the memory address generated by the processor is
decoded.
The high order K-bits represents one of the ‘n’-modules and low order ‘m’ bits
represents particular word in that module.
When consecutive locations are accessed, then only one module is involved.
The second figure represents interleaving concept.
The low order K-bit address represents a module and the high order m-bits
represents a location within that module.
There, the consecutive address are located in the successive modules.
Hit rate and miss penalty:
Hit rate means, it is the ratio of the number of hits to the total CPU
reference.
Miss rate is the ratio of the number of misses to the total CPU
references.
The performance is affected by the actions that must be taken after a
miss.
The extra time needed to bring the desired information into the
cache is called miss penalty.
Caches on processor chip:
In higher performance, processor two levels of caches are used.
The L1 cache is on the processor chip.
The L2 cache is larger and it is implemented using S-RAM chips.
If both L1 and L2 caches are used, then L1 cache is used mainly for fast accessing by
the processor, because it is faster than L2 cache.
The average access time taken by the processor with two levels of cache is
Tavg = h1c1 + (1-h1)h2c2 +(1-h1)(1-h2)M
Where,
h1 = Hit rate in L1 cache
h2 = Hit rate in L2 cache
c1 = Time required for accessing in L1 cache
c2 = Time required for accessing in L2 cache
M = Time required for accessing information in main memory
 VIRTUAL MEMORY
Virtual memory techniques moves the program and data blocks into physical
memory, when they are required for execution
An address used by a programmer is called a ‘Virtual Address’ and the set of such
address is called the address space
An address which is in main memory is called physical address, the set of such
location is called memory space
The virtual or logical address are translated into the physical address by some
software and hardware components
If a virtual address refers to a part of the program i.e currently in physical
memory, then the contents of the appropriate location in the main memory are
accessed immediately
If the referenced address is not in the main memory, its contents must be
brought into the suitable location in the memory
(Virtual Memory Organisation)
 The memory management unit(MMU), translates virtual addresses into physical addresses

 When the desired data or instructions are in the main memory, then they are fetched by using
cache

 If the data are not in the main memory, the MMU causes the operating system to bring the data
into memory from the disk

 Data transfer between disk and main memory is performed by DMA

Address Translation:
 A method of translating virtual addresses into physical addresses assumes that all the programs
and data are stored in fixed length units called pages, each page consists of a block of words &
they occupy locations in the main memory
 Generally the pages length range is from 2K to 16K bytes
 Pages should not be too small because the access of the magnetic disk is longer than the access
time of the main memory
 Each virtual address of instruction of data is interpreted as virtual page number (High order bits)
and offset (Low order bits), it specifies the location of a particular word within a page
 Information about each page is stored in page-table
 This information includes the main memory address, where the page is stored and the current
status of page
 A place which holds one page is called a page frame
 The starting address of the page table is stored in page table base register
 By adding the virtual page number to the contents of this register, the address of the
corresponding entry is obtained
 The contents of this location gives the starting address of the page, which is main memory
 Each entry in the page table consists of control bits that describe the status of the page
 One bit indicates the validity of the page whether the page is loaded in main memory or not
 Another bit indicate whether the page has been modified or not
Memory Management Requirements:
Management routines are part of the Operating system.
Assembling the OS routine into virtual address space is called „System Space‟.
The virtual space in which the user application program reside is called the User Space.
Each user space has a separate page table.
The MMU uses the page table to determine the address of the table to be used in the
translation process.
Hence by changing the contents of this register, the OS can switch from one space to another.

The process has two stages. They are,

User State
Supervisor state.
User State:
In this state, the processor executes the user program.
Supervisor State:
When the processor executes the operating system routines, the
processor will be in supervisor state.
Privileged Instruction:
 In user state, the machine instructions cannot be executed.
Hence a user program is prevented from accessing the page table of
other user spaces or system spaces.
The control bits in each entry can be set to control the access
privileges granted to each program.
One program may be allowed to read/write a given page, while the
other programs may be given only red access.
SECONDARY STORAGE:
The Semi-conductor memories do not provide all the storage capability.
The Secondary storage devices provide larger storage requirements.
Some of the Secondary Storage devices are,
 Magnetic Disk
 Optical Disk
 Magnetic Tapes
Magnetic Disk:
A magnetic Disk is a type of secondary memory that is a flat disc covered with a
magnetic coating to hold information.
 It is used to store various programs and files.
The polarized information in one direction is represented by 1, and vice versa.
The direction is indicated by 0.
Magnetic disks are less expensive than RAM and can store large amounts of data,
but the data access rate is slower than main memory because of secondary
memory.
Data can be modified or can be deleted easily in the magnetic disk memory. It
also allows random access to data.
Types of Magnetic Disks:
1. Hard Disk Drives (HDDs)
2. Floppy Disks (Diskettes)
Optical Disks:
Optical Disk is a storage medium that relies on laser technology to read and write
data, in shape, it is a flat circular disk which is made up of polycarbonate or a
similar material with a very shiny reflective layer on the surface.
They are mainly used for sharing, storing and backup Data as they have a great
life span and capacity compared to older technologies like floppy disks.
Types of Optical Disk
1. Compact Disc (CD)
2. Digital Versatile Disc (DVD)
3. Blu-ray Disc (BD)
Magnetic tapes
In magnetic tape only one side of the ribbon is used for storing data.
It is sequential memory which contains thin plastic ribbon to store
data and coated by magnetic oxide.
Data read/write speed is slower because of sequential access. It is
highly reliable which requires magnetic tape drive writing and reading
data.
Data is recorded on the tape by magnetizing specific areas of the
coating.
Phase Encoding or Manchester Encoding is the technique to combine the clocking
information with data.
The Read/Write heads must be maintained at a very small distance from the
moving disk surfaces in order to achieve high bit densities.
When the disk are moving at their steady state, the air pressure develops
between the disk surfaces & the head & it forces the head away from the surface.
The flexible spring connection between head and its arm mounting permits the
head to fly at the desired distance away from the surface.