Other registers of 8086

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is
usedto control which instruction the CPU executes. The IP, or program counter, is used to
store the memory location of the next instruction to be executed. The CPU checks the
program counter to ascertain which instruction to carry out next. It then updates the program
counter to point to the next instruction. Thus the program counter will always point to the
next instruction to be executed.

Flag Register contains a group of status bits called flags that indicate the status of the
CPU orthe result of arithmetic operations. There are two types of flags:

1. The status flags which reflect the result of executing an instruction. The
programmer cannotset/reset these flags directly.
2. The control flags enable or disable certain CPU operations. The programmer
can set/reset these bits to control the CPU's operation.

Nine individual bits of the status register are used as control flags (3 of them) and status flags
(6 of them).The remaining 7 are not used.

A flag can only take on the values 0 and 1. We say a flag is set if it has the value
1.The status flags are used to record specific characteristics of arithmetic and of logical
instructions.
 Control Flags: There are three control flags

The Direction Flag (D): Affects the direction of moving data blocks by such instructions as
MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by
the STD (set D) and CLD (clear D) instructions.

The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are
actions initiated by hardware block such as input devices that will interrupt the normal
execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts
and can be manipulated by the CLI (clear I) and STI (set I) instructions.

The Trap Flag (T): Determines whether or not the CPU is halted after the executionof
each instruction. When this flag is set (i.e. = 1), the programmer can single step through his
program to debug any errors. When this flag = 0 this feature is off. Thisflag can be set
by the INT 3 instruction.

Status Flags: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic
operation is too large to fit in the destination register. This happens when there is an
end carry in an addition operation or there an end borrows in a subtraction operation.
A value of 1 = carry and 0 = no carry.

2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic
operation is too large to fit in the destination register (i.e. when an overflow occurs).
Overflow can occur when adding two numbers with the same sign (i.e. both
positive or both negative). A value of 1 = overflow and 0 = no overflow.

3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation
is negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1
means negative and 0 = positive.

4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic
operation is equalto zero. A value of 1 means the result is zero and a value of 0 means
the result is not zero.

5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry
from bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry
and 0 = no carry.

6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation.
If the number of 1s is even its value = 1 and if the number of 1s is odd then its value =
0.
 Explanation of Architecture of 8086

Figure: 8086 Architecture

Bus Interface Unit:

It provides a full 16 bit bidirectional data bus and 20 bit address bus.

• The bus interface unit is responsible for performing all external bus operations.

• Specifically it has the following functions:

• Instruction fetch Instruction queuing, Operand fetch and storage, Address

relocation and Buscontrol.

• The BIU uses a mechanism known as an instruction stream queue to

implement pipelinearchitecture.
• This queue permits prefetch of up to six bytes of instruction code. When
ever the queue ofthe BIU is not full, it has room for at least two more bytes
 and at the same time the EU is not requesting it to read or write operands from
memory, the BIU is free to look ahead in theprogram by prefetching the next
sequential instruction.

• These prefetching instructions are held in its FIFO queue. With its 16 bit data
bus, the BIU fetches two instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.

• The EU accesses the queue from the output end. It reads one instruction byte
after theother from the output of the queue. If the queue is full and the EU is
not requesting access to operand in memory.

• These intervals of no bus activity, which may occur between bus cycles are
known as Idlestate.

• If the BIU is already in the process of fetching an instruction when the EU

request it to read or write operands from memory or I/O, the BIU first
completes the instruction fetch bus cycle before initiating the operand read /
write cycle.

• The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16bit segment address and a 16 bit offset address.

• For example: The physical address of the next instruction to be fetched is

formed by combining the current contents of the code segment CS register and
the current contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those
for memory reador write and I/O read or write.

Execution Unit

• The Execution unit is responsible for decoding and executing all instructions.

• The EU extracts instructions from the top of the queue in the BIU, decodes
them, generates operands if necessary, passes them to the BIU and requests it to
perform the read or write bus cycles to memory or I/O and perform the operation
specified by the instruction on the operands.

• During the execution of the instruction, the EU tests the status and control
flags andupdates them based on the results of executing the instruction.

• If the queue is empty, the EU waits for the next instruction byte to be
fetched and shifted to top of the queue.

• When the EU executes a branch or jump instruction, it transfers

control to a locationcorresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then
begins to fetchinstructions from this new location to refill the queue.