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Lab 7

The lab focuses on designing a circuit to calculate the greatest common divisor (GCD) of two 8-bit numbers using a start signal and providing an output signal upon completion. Students are required to run a testbench simulation with specific inputs and demonstrate the module on an FPGA, using switches for input and LEDs for output. The report must include a detailed explanation of the design, algorithm used, circuit type, simulation results, and potential optimizations.

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Nilsu Asiltürk
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26 views1 page

Lab 7

The lab focuses on designing a circuit to calculate the greatest common divisor (GCD) of two 8-bit numbers using a start signal and providing an output signal upon completion. Students are required to run a testbench simulation with specific inputs and demonstrate the module on an FPGA, using switches for input and LEDs for output. The report must include a detailed explanation of the design, algorithm used, circuit type, simulation results, and potential optimizations.

Uploaded by

Nilsu Asiltürk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 7: Greatest Common Divisor

The purpose of this lab is to design a circuit that calculates the greatest common divisor (GCD) of two 8-
bit numbers.

In this lab, you are allowed to reuse codes that you wrote in the Arithmetic Logic Unit and Chronometer
labs. If you have lost your code or do not want to adapt, you can also use codes from other resources by
properly citing them. In either case, please do not include recycled/borrowed codes in your report.

Design a module that calculates the GCD of two 8-bit numbers. This module should start
calculating with a start signal from a button, and when the calculation is done, it should
indicate this via an output signal.

Run a testbench simulation using inputs 140 and 12. How many clock cycles does the
calculation take from the start signal till the end? Include in your report.

Demonstrate this module on your FPGA. Take 8-bit numbers from switches, the start signal
from a button; and display the result on the LEDs. Show a few working examples to your TA
and get their approval.

There are multiple ways to calculate the GCD of two binary numbers. You can choose one and implement
it.

In your report, clearly explain your design, show your results, and try to answer the following questions:

• What was your algorithm to calculate the GCD?


• Is your module a combinational circuit or an FSM? If the latter, is it a Moore machine or a Mealy
machine? Would it be cheaper to implement GCD as a combinational circuit or as an FSM? Would
it be faster? What are the drawbacks in each case?
• How many clock cycles did it take in your simulation to calculate the GCD? Do you think this can
be optimized? How so?

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