LOC-2 Unit 1

Sequential Logic Circuits

The combinational circuit does not use any memory. Hence the previous state of input does not
have any effect on the present state of the circuit. But sequential circuit has memory so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.
Block diagram

1. Sequential circuits are commonly used in digital systems to implement state

machines, timers, counters, and memory elements. The memory elements in
sequential circuits can be implemented using flip-flops, which are circuits
that store binary values and maintain their state even when the inputs
change.
2. There are two types of sequential circuits: finite state machines (FSMs) and
synchronous sequential circuits. FSMs are designed to have a limited
number of states and are typically used to implement state machines and
control systems. Synchronous sequential circuits, on the other hand, are
designed to have an infinite number of states and are typically used to
implement timers, counters, and memory elements.
In summary, sequential circuits are digital circuits that store and use previous
state information to determine their next state. They are commonly used in
digital systems to implement state machines, timers, counters, and memory
elements and are essential components in digital systems design.
Sequential circuit is a combinational logic circuit that consists of inputs variable
(X), logic gates (Computational circuit), and output variable (Z).
 3.
A combinational circuit produces an output based on input variables only, but
a sequential circuit produces an output based on current input and previous
output variables. That means sequential circuits include memory elements that
are capable of storing binary information. That binary information defines the
state of the sequential circuit at that time. A latch capable of storing one bit of
information.

As shown in the figure, there are two types of input to the combinational logic :
1. External inputs which are not controlled by the circuit.
2. Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements,
whereas secondary outputs are excitations for the storage elements.
Types of Sequential Circuits:
There are two types of sequential circuits:
Type 1: Asynchronous sequential circuit: These circuits do not use a clock
signal but uses the pulses of the inputs. These circuits are faster than
synchronous sequential circuits because there is clock pulse and change their
state immediately when there is a change in the input signal. We use
asynchronous sequential circuits when speed of operation is important
and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.

Type2: Synchronous sequential circuit: These circuits uses clock signal and
level inputs (or pulsed) (with restrictions on pulse width and circuit propagation).
The output pulse is the same duration as the clock pulse for the clocked
sequential circuits. Since they wait for the next clock pulse to arrive to perform
the next operation, so these circuits are bit slower compared to asynchronous.
Level output changes state at the start of an input pulse and remains in that
until the next input or clock pulse.
Advantages of Sequential Circuits:

1. Memory: Sequential circuits have the ability to store binary values, which
makes them ideal for applications that require memory elements, such as
timers and counters.
2. Timing: Sequential circuits are commonly used to implement timing and
synchronization in digital systems, making them essential for real-time
control applications.
3. State machine implementation: Sequential circuits can be used to implement
state machines, which are useful for controlling complex digital systems and
ensuring that they operate as intended.
4. Error detection: Sequential circuits can be designed to detect errors in digital
systems and respond accordingly, improving the reliability of digital systems.

Disadvantages of Sequential Circuits:

1. Complexity: Sequential circuits are typically more complex than

combinational circuits and require more components to implement.
2. Timing constraints: The design of sequential circuits can be challenging due
to the need to ensure that the timing of the inputs and outputs is correct.
3. Testing and debugging: Testing and debugging sequential circuits can be
more difficult compared to combinational circuits due to their complex
structure and state-dependant outputs.

The main characteristics of combinational circuits and Sequential circuits are as

following below-

Combinational Circuits Sequential Circuits

The output depends only upon the present The output depends upon both present
input and there is no need for feedback for input and present state (previous output),
input and output, so memory element is not so a memory element is required to save
required. the feedback state.

It is not easier to design, use and handle

It is easier to design, use and handle. than combinational circuits.

Clock signals are required, and it is

Clock signals are not required, and it is not dependent on time and clock so need
dependent on time. triggering.
 Combinational Circuits Sequential Circuits

Elementary building blocks are only logic

gates. Elementary building blocks are Flip-Flops.

These circuits are slower than

These are faster logic circuits. combinational circuits.

These circuits are expensive. These circuits are comparatively cheaper.

Example: Parallel adder Example: Serial Adder

Basics of Flip Flop

A circuit that has two stable states is treated as a flip flop. These stable
states are used to store binary data that can be changed by applying varying
inputs. The flip flops are the fundamental building blocks of the digital
system. Flip flops and latches are examples of data storage elements. In the
sequential logical circuit, the flip flop is the basic storage element. The
latches and flip flops are the basic storage elements but different in working.
There are the following types of flip flops:

SR Flip Flop
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET
and RESET. The SET input 'S' set the device or produce the output 1, and the
RESET input 'R' reset the device or produce the output 0. The SET and RESET
inputs are labeled as S and R, respectively.

The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get
back the flip flop to its original state from the current state with an output
'Q'. This output depends on the set and reset conditions, which is either at
the logic level "0" or "1".

The NAND gate SR flip flop is a basic flip flop which provides feedback from
both of its outputs back to its opposing input. This circuit is used to store the
single data bit in the memory circuit. So, the SR flip flop has a total of three
inputs, i.e., 'S' and 'R', and current output 'Q'. This output 'Q' is related to the
current history or state. The term "flip-flop" relates to the actual operation of
the device, as it can be "flipped" to a logic set state or "flopped" back to the
opposing logic reset state.

The NAND Gate SR Flip-Flop

We can implement the set-reset flip flop by connecting two cross-coupled 2-
input NAND gates together. In the SR flip flop circuit, from each output to
one of the other NAND gate inputs, feedback is connected. So, the device
has two inputs, i.e., Set 'S' and Reset 'R' with two outputs Q and Q'
respectively. Below are the block diagram and circuit diagram of the S-R flip
flop.

Block Diagram:

Circuit Diagram:
The Set State
In the above diagram, when the input R is set to false or 0 and the input S is
set to true or 1, the NAND gate Y has an input 0, which will produce the
output Q' 1. The value of Q' is faded to the NAND gate 'X' as input 'A', and
now both the inputs of the NAND gate 'X' are 1(S=A=1), which will produce
the output 'Q' 0.

Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND
gate 'Y' is R=1 and B=0. Here, one of the inputs is also 0, so the output of Q'
is 1. So, the flip flop circuit is set or latched with Q=0 and Q'=1.

Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by
R =1 and S = 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1.
Output Q is faded to NAND gate Y as input B. So, both the inputs to NAND
gate Y are set to 1, therefore, Q' = 0.

Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be
0 and there is no change in state. So, the reset state of the flip flop circuit
has been latched, and the set/reset actions are defined in the following truth
table:

From the above truth table, we can see that when set 'S' and reset 'R' inputs
are set to 1, the outputs Q and Q' will be either 1 or 0. These outputs depend
on the input state S or R before the input condition exist. So, when the inputs
are 1, the states of the outputs remain unchanged.

The condition in which both the inputs states are set to 0 is treated as invalid
and must be avoided
JK Flip Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the
following switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always
avoided.
o When the Set or Reset input changes their state while the enable input
is 1, the incorrect latching action occurs.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip
flop is a universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S'
and 'R' are the shortened abbreviated letters for Set and Reset, but J and K
are not. The J and K are themselves autonomous letters which are chosen to
distinguish the flip flop design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop
has 'J' and 'K' flip flop instead of 'S' and 'R'. The only difference between JK
flip flop and SR flip flop is that when both inputs of SR flip flop is set to 1, the
circuit produces the invalid states as outputs, but in case of JK flip flop, there
are no invalid states even if both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input
circuitry. The invalid or illegal output condition occurs when both of the
inputs are set to 1 and are prevented by the addition of a clock input circuit.
So, the JK flip-flop has four possible input combinations, i.e., 1, 0, "no
change" and "toggle". The symbol of JK flip flop is the same as SR Bistable
Latch except for the addition of a clock input.
Block Diagram:

Circuit Diagram:

In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K.
It means the J and K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The
third input of each gate is connected to the outputs at Q and Q'. The cross-
coupling of the SR flip-flop permits the previous invalid condition of (S = "1",
R = "1") to be used to produce the "toggle action" as the two inputs are now
interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q'
through the lower NAND gate. If the circuit is "RESET", K input is interrupted
from 0 positions of Q through the upper NAND gate. Since Q and Q' are
always different, we can use them to control the input. When both inputs 'J'
and 'K' are set to 1, the JK toggles the flip flop as per the given truth table.

Truth Table:

When both of the inputs of JK flip flop are set to 1 and clock input is also
pulse "High" then from the SET state to a RESET state, the circuit will be
toggled. The JK flip flop work as a T-type toggle flip flop when both of its
inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is
changed before the clock input's timing pulse has time to go "Off". We have
to keep short timing plus period (T) for avoiding this period.

Truth Table:
D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET =
"0" and RESET = "0" is forbidden. It is the drawback of the SR flip flop. This
state:

1. Override the feedback latching action.

2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the

inverter between the Set and Reset inputs for producing another type of flip
flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It
ensures that at the same time, both the inputs, i.e., S and R, are never equal
to 1. The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input
and for the complementary "Reset" input, the inverter is used. Thus, the
level-sensitive D-type or D flip flop is constructed from a level-sensitive SR
flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram
Circuit Diagram

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the
output and another to "RESET" the output. By using an inverter, we can set
and reset the outputs with only one input as now the two input signals
complement each other. In SR flip flop, when both the inputs are 0, that state
is no longer possible. It is an ambiguity that is removed by the complement
in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the
data input is set to 1, the flip flop would be set, and when it is set to 0, the
flip flop would change and become reset. However, this would be pointless
since the output of the flip flop would always change on every pulse applied
to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data
input from the flip flop's latching circuitry. When the clock input is set to
true, the D input condition is only copied to the output Q. This forms the
basis of another sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop
are both set to 1. So it will not change the state and store the data present
on its output before the clock transition occurred. In simple words, the output
is "latched" at either 0 or 1.
Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop
assumed these symbols as edge-triggers.

Truth Table:

T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a
single input called "Toggle" or "Trigger" input to avoid an intermediate state
occurrence. Now, this flip-flop work as a Toggle switch. The next output state
is changed with the complement of the present state output. This process is
known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop".
The "T Flip Flop" has only one input, which is constructed by connecting the
input of JK flip flop. This single input is called T. In simple words, we can
construct the "T Flip Flop" by converting a "JK Flip Flop". Sometimes the "T
Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle
input", and CLK defines the clock signal input.
T Flip Flop Circuit
There are the following two methods which are used to form the "T Flip
Flop":

o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.

Construction
The "T Flip Flop" is designed by passing the AND gate's output as input to
the NOR gate of the "SR Flip Flop". The inputs of the "AND" gates, the
present output state Q, and its complement Q' are sent back to each AND
gate. The toggle input is passed to the AND gates as input. These gates are
connected to the Clock (CLK) signal. In the "T Flip Flop", a pulse train of
narrow triggers are passed as the toggle input, which changes the flip flop's
output state. The circuit diagram of the "T Flip Flop" using "SR Flip Flop" is
given below:
Truth Table of T Flip Flop

Truth Table:

What is SR Clocked Flip-Flop?

The SR flip-flop is also named as RS flipflop. When both the inputs of the SR
flip-flop are high, then the indeterminate state is theirs. In other programming
environments, it is required to assign determinate outputs to all flipflop
conditions. Hence, RS and SR flip-flops were designed. The clocked SR flip-
flop is shown below.
SR Flip-Flop Circuit Diagram

The circuit is similar to the SR latch except for the clock signal and two AND
gates. The SR flip-flop circuit responds to the positive edge of the clock pulse
to the inputs S and R.

SR Flip-Flop is Used as

SR Flip-Flop is Used as a storage device for a single data bit.

SR Flip-Flop Truth Table

'S' and 'R' are the two inputs to the SR flip-flop. The Qn represents the state of
the SR flip-flop before applying the inputs, and Qn+1 represents the state of the
SR flip-flop as output. The truth table for SR flip-flop is shown below:

SR Flip-Flop Truth Table

Clock S R Qn+1 State

0 X X Qn X
1 0 0 Qn Hold
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 X Invalid

Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then
Q output toggle until the CLK is 1. Thus, the uncertain or unreliable output
produces. This problem is referred to as a race-round condition in JK flip-flop
and avoided by ensuring that the CLK set to 1 only for a very short time.

Explanation
The master-slave flip flop is constructed by combining two JK flip flops. These
flip flops are connected in a series configuration. In these two flip flops, the
1st flip flop work as "master", called the master flip flop, and the 2nd work as
a "slave", called slave flip flop. The master-slave flip flop is designed in such
a way that the output of the "master" flip flop is passed to both the inputs of
the "slave" flip flop. The output of the "slave" flip flop is passed to inputs of
the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT
gate is also used. For passing the inverted clock pulse to the "slave" flip flop,
the inverter is connected to the clock's pulse. In simple words, when CP set
to false for "master", then CP is set to true for "slave", and when CP set to
true for "master", then CP is set to false for "slave".
Working:
o When the clock pulse is true, the slave flip flop will be in the isolated state,
and the system's state may be affected by the J and K inputs. The "slave"
remains isolated until the CP is 1. When the CP set to 0, the master flip-flop
passes the information to the slave flip flop to obtain the output.
o The master flip flop responds first from the slave because the master flip flop
is the positive level trigger, and the slave flip flop is the negative level
trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an
input K when the input J set to 0 and K set to 1. The clock forces the slave flip
flop to work as reset, and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The
clock's negative transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs
J and K set to 1. At that time, the slave flip flop toggles on the clock's
negative transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs
of the JK flip flop set to 0.
Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one
until the clock input remains 0.
o When the clock pulse becomes high again, then the master's output is 0,
which will be set to 1 when the clock becomes one again.
o The master flip flop is operational when the clock pulse is 1. The slave's
output remains 0 until the clock is not set to 0 because the slave flip flop is
not operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the
master remains one until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once
in the cycle.

State diagram
The state diagram is the pictorial representation of the
behavior of sequential circuits. It clearly shows the transition of
states from the present state to the next state and output for a
corresponding input.

 In this diagram, each present state is represented inside a circle.

  The transition from the present state to the next state is
represented by a directed line connecting the circles.
 If the directed line connects the circle itself, which indicates that
there is no change in the state(the next state is the same as the
present state).
 For mealy model, the directed line is labeled with binary numbers
separated with ‘/’, as shown in the below diagram.
 The input value, which causes the transition to occur is labeled
first ‘1/’. The output produced for the corresponding input is
labeled second ‘/0’.

 For Moore circuit, the directed lines are labeled with only one
binary number. It is nothing but the input value which causes
the transition.
 The output value is indicated inside the circle below the present
state. It is because, in Moore model, the output depends on the
present state but not on the input.

State table
The information contained in the state diagram is transformed
into a table called a state table or state synthesis
table. Although the state diagram describes the behavior of the
sequential circuit, in order to implement it in the circuit, it has to be
transformed into the tabular form.
The below table shows the state table for Mealy state machine
model. As you can see, it has the present state, next state and output.
The present state is the state before the occurrence of the clock pulse.

After the application of the clock pulse, depending on the input(X = 0

or 1), the state changes. It is indicated in the ‘next state’ column. The
output produced for each input is represented in the last column.

The table shown below is the state table for Moore state machine
model. Since, in Moore state machine model, the output depends only
on the present state, the last column has only output.