AN EFFICIENT VLSI DESIGN FOR PIPELINED ADVANCED ENCRYPTION
STANDARD IN CRYPTOGRAPHY
Jayanita Devi R, Padmapriya A
Supervisor: Ms. JAYAMANI K, Assistant Professor
Department of Electronics and Communication Engineering
ABSTRACT:
In today’s data-driven world, ensuring the confidentiality and integrity of
information is crucial, especially in resource-constrained embedded systems Design Input: The Nano-AES architecture is implemented in Verilog HDL with an
like IoT devices. This project presents a efficient VLSI implementation of the 8-bit data path, optimized for IoT devices.
Advanced Encryption Standard (AES), focusing on a compact, low-power,
and high-speed design suitable for secure hardware environments. This ● Encryption Flow: The design processes plaintext through key AES stages—
architecture supports 128-bit AES encryption, integrating optimized Sub- Sub-Bytes, Shift-Rows (embedded in the State-Register), Mix Columns, and Add
Bytes, Mix-Columns, and embedded Shift-Rows for area efficiency. A single Round Key—using a pipelined approach
Sub-Bytes module is shared between key expansion and encryption, reducing
logic overhead. Clock gating is applied across key blocks to minimize ● Power Optimization: Clock gating is applied to key components like the State-
dynamic power usage, while constant-time operations enhance resistance to Register and Key-Register to reduce power consumption during idle states.
side-channel attacks. Implemented on the Xilinx XC3S200TQ-144 FPGA
using Verilog HDL, the design is verified through ModelSim simulations and ● Simulation and Synthesis: The design is verified using ModelSim and
synthesized using Xilinx ISE. The result is a compact AES core that achieves
synthesized on an FPGA using Xilinx ISE tools.
a balanced trade-off between speed, area, and power—ideal for real-time
encryption in resource-limited environments. This work demonstrates a
scalable and secure AES solution ideal for real-time encryption in resource- ● Performance: The optimized architecture significantly reduces area and delay
limited environments. compared to conventional AES designs, making it ideal for secure, low-power
applications.
INTRODUCTION:
In an increasing digital world, data security has become a critical concern.
Cryptography plays a central role in ensuring confidentiality, integrity, and
authentication of information in communication systems. The Advanced RESULT:
Encryption Standard (AES) is one of the most widely used symmetric key
encryption algorithms, standardized by NIST due to its strong security and
performance. Implementing AES in hardware offers significant advantages in
terms of speed, parallelism, and resistance to software-based attacks.
However, achieving high performance while minimizing power consumption
and area is a major design challenge, especially for embedded and IoT systems
where resources are limited. This project focuses on designing an efficient
VLSI architecture for the AES algorithm using an 8-bit pipelined structure.
The design aims to reduce silicon area, optimize power usage, and maintain
high throughput. Key architectural optimizations, including clock gating,
embedded Shift-Rows, and shared Sub-Bytes modules, are introduced to
enhance overall efficiency and security. The result is a compact, power-aware
AES engine suitable for lightweight cryptographic applications on FPGA
platforms.
METHODOLOGY:
CONCLUSION:
This project presents a compact and efficient VLSI implementation of the
AES algorithm using an 8-bit pipelined architecture. Key optimizations such
as embedded Shift-Rows, shared Sub-Bytes, and clock gating help reduce
power and area while maintaining high performance. The design, implemented
on a Xilinx FPGA, is well-suited for secure, real-time encryption in embedded
and IoT systems. Overall, the architecture offers a practical balance of speed,
security, and resource efficiency for lightweight cryptographic applications.
