EXPERIMENT-10
Realization of RS, D, JK and T flip-flops using logic gates
Aim:
To study and verify the truth table of RS, D, JK and T flip-flops using logic gates.
Apparatus Required:
SI.No. COMPONENT SPECIFICATION QTY.
1. NAND GATE IC7400 2
2. NOT GATE IC 7404 1
3. IC TRAINER KIT 1
4. PATCH CORDS
Theorv:
Flip-flop is a circuit that maintains a state until directed by input to change the state. Aflip flop
is an electronic circuit with two stable states that can be used to store binary data. The stored data
can be changed by applying varying inputs. Flip-flops and latches are fundamental building
blocks of digital electronics systems used in computers, communications, and many other types
of systems. Flip-flopsand latches are used as data storage elements. It is the basic storage
element in sequential logic.A basic flip-flop can be constructed using four-NAND or four-NOR
gates.
Types of flip-flops:
RS Flip Flop
JK Flip Flop
D Flip Flop
T Flip Flop
Logic diagrams and truth tables of the different types of flip-flops are as follows:
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S-R Flip Flop:
SR flip-flop operates with only positive clock transitions or negative clock transitions. This
simple flip flop circuit has a set input (S) and a reset input (R). In this circuit when you Set g"
as active the output "QN would be high and QN+1 willbe low. Once the outputs are
established, the wiring of the circuit is maintained until s" or "R" go high, or power is turned
off. As shown above, it is the simplest and the easiest to understand. The two outputs, as shown
above,are the inverse of each other. The truth table of SR Flip Flop is highlighted below.
The circuit diagram of SR flip-flop is shown in the following figure.
TRUTH TABLE
R ON QN
1 0
0 1
1 1
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D Flip Flop:
D flip flop is a better alternative that is very popular with digital electronics. They are commonly
used for counters and shift-registers and input synchronization.
CLK
D Flip-Flop
In aD flip flop, the output can be only changed at the clock edge, and ifthe inpüt changes at other
times, the output will be unaffected.
Clock QN QN+1
0 0 1
‘»1 0
1 1
‘» 1 1 0
The change of state of the output is dependent on the rising edge of the clock. The output (0) is same
as the input and can only change at the rising edge of the clock.
JK Flip-flop:
Due to the undefined state in the SR flip flop, another flip flop is required in electronics. The JK flip
flop is an improvement on the SR flip flop where S=R=1 is not a problem.
J
CLK
K
JK Flip-Flop
The input condition of J-K=1, gives an output inverting the output state. However, the outputs are
the same when one tests the circuit practically.
In simple words, If J and Kdata input are diferent (i.e. high and low) then the output Qtakes the
value of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both
high at the clock ed#e then the output will toggle from one state to the other.K Flip Flop can
function as Set or Reset Flip flop
J K QN
0 1
1 1
1 1
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T Flip Flop:
AT flipflop is like JK flip-flop. These are basicallya single input version of JK flip flop. This
modified forn of JK' flip-flop is obtained by connecting both inputs J andK together. This flip
flop has only one input along with the clock input.
CLK
TFlip-Flop
These flip-flops are called T flip-flops because of their ability to complement its state (i.e.)
Toggle, hence the name Toggle flip-flop.
T Q N+1
0 0
1 1.
0 1
1 0
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Procedure:
()Connections are given as per circuit diagram.
(ii) Inputs are given as per circuit diagram.
(iii) Logical observe the output and verify the truth table.
Result:
Observed output matches theoretical concept.
Precautions:
Allconnection should be made neat and tight.
Digital lab kits and ICs should be handled with outmost care.
While making connections main voltage should be kept switched off.
Never touch live and naked wires.
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EXPERIMENT-11
Realization of Register using flip-flops && logic gates
Aim:- Torealize and study of register like shift register using flip-flops and logic gates
To design and implement
i) SISO(Serial in serial out)
(i) SPO(Serial in parallel out)
(iii) PISO (Parallel in serial out)
(iv) PIPO Parallel in parallel out)
Apparatus Reguired:
SI.No. COMPONENT SPECIFICATION QTY.
1. DFLIP-FLOP IC 7474 2
2. OR GATE IC 7432
3. IC TRAINER KIT 1
4. PATCH CORDS
Theorv:
both directions is
A tegister is capable of shifting its binary information in one or
flop
known as shift register. The logical configuration of shift register consist of a D-Flip
receive
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
possible
common clock pulses which causes the shift in the output of the flip flop.The simplest
flop is connected to the
shift register is one that uses only flip flop. The output of a given flip
content of register one bit
input of next flip flop of the register. Each clock pulse shifts the
position to right.
PIN DIAGRAM:
CLRO 14-VCC
DO C 13 CLR1
CLKO 3 7 12 D1
PREO 4 11CLK1
SO 7 10 PRE1
9 Q1
4
GND 7 01
SISO (Serialin serial out):
LOGIC DIAGRAM:
DATA
PRE OUTPUT
U1B U2A 10 U2B
UIA
~2PR ~1PR ~2PR
DATA IP -1PR
2 20
2
1D 12 2D 20 9
*10
1CLK -1O B2cK -20 Bi 1CLK -1Q 2cLK -20
CLK ~2CLR -1CLR ~2CLR
-1CLR
T13 747N 7474N 13 7474N
1 7474N
CLR
TRUTH TABLE:
CLK Serial in Serial out
1 0
1
2 0
3 0 0
4 1
5 X 0
6 X 0
7 X
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SIPO(Serial in parallel out):
LOGIC DIAGRAM:
|03 OUTPUT
|02
PRESET Q0
IA UIB
4 U2A
~lPR w2PR 10 U2B
DATA ~lPR ~2PR
D 2D 20 9
2 20 9
CLK Soo 1CLK -10 2CLK 20 8
~2CLR 2CLR
1ab 2cLK ~20
alCLR w2CLR
7474
13 7474 7474 7474
CLR
TRUTH TABLE:
OUTPUT
CLK DATA QA QB Qe QD
* 1 1 0
2 1
3 1 1
4 1 1 1
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PISO (Parallel in serial out):
LOGIC DIAGRAM:
OUTPUT
03 Q2 Q1
PRE
4
~1PR ~2PR »1 PR w2PR
10 20 9 10 20
7432 7432 7432
1CLK -10 6 b 2cLK -20 1CLK -10 2CLK -20 2
CLK w1CLR ~2CLR -1CLR -2CLR
1 7474 T13 7474 1 7474 13 7474
CLR
TRUTH TABLE:
CLK Q3 Q2 .Q1 Q0 o/P
3.
1 0 1 1
1 0 0 0
2 0
3 0 0 1
PIPO (Parallel in Parallel out):
LOGIC DIAGRAM:
Q3 |D2 Q2 01 DO Output Q0
D3DATA
PRESET
UIA UIB U2A U2B
-lPR ~2PR l PR w2PR
2D 20
9 10 20 9
Lp 2cLK ~20 pi 2CLK ~20
CLK -2CLR ~1CLR ~2CLR
-1CLR
7474 13 7474 7474 13 7474
CLA
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TRUTH TABLE:
DATAINPUT OUTPUT
CLK DA Dg Dc Dp QA
1 1 0 1
2 1 0 1 0 1 0
PROCEDURE:
() Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Result:
Observed output matches theoretical concept.
Precautions:
Allconnection should be made neat and tight.
Digital lab kits and ICs should be handled with outmost care.
While making connections main voltage should be kept switched off.
Never touch live and naked wires.
EXPERIMENT-12
Realization of Up/Down Counters
Aim:- To design and implement 3 bit synchronous up/down counter.
Apparatus Required:
SL.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 IP AND GATE IC 7411 1
3. OR GATE IC7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6 ICTRAINER KIT
7 PATCHCORDS 35
Theory
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that is
capable of progressing in increasing order or decreasing order through 'a certain sequence. An
up/down counter is also called bidirectional counter. Usually up/down operation of the counter is
controlled by up/down signal. When this signal is high counter goes through up sequence and
when up/down signal is lowcounter follows reverse sequence.
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LOGIC DIAGRAM:
(UpiDown) 7404 |High
74LS11 PRE
2 l2
7486
7432 11
l1 20 20
l o CLK 2CLK l o 1CLK
/t40-4 12 2K 20 n
T8 7476 3 7476
CLKI
CLR
741S1!
KMAP:
QB QC QB QC QB QC
UD QA UD QA UD QA
1 X X 1 X x
X X X 1 1 X 1
X 1 1 X X 1
1 X x X X X
KA= UD QB QC+ UD QB QC JC=1
JA =UD QB QC+ UD QB QC
QB QC QB QC QB QC
UD QA UD QA UDQA
X X 1 X
1
X 1 X 1 X
1 X X
X X 1 1 X
X X
1 X 1 1 X
X X
JB= UDQC KB= (UDOQC) KC=1
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STATE DIAGRAM:
010
110
404
TRUTH TABLE:
A 3 C
Present State Next State
Input J K
J KA
Up/Down
1 1 1 X 1 X
0
X 0
1 1 1 1 0
0
0 1
1
1 1 1
1 1 0
1 0
0 0
0
1 0
1 1 0
1 X
1 1
1 0 X
1 1 1
1 X
1 1 0
1 0 1
1 1
1 1 1 1
1 1 1 X 1 X 1X 1
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PROCEDURE:
() Connections are given as per circuit diagram.
(i1) Logical inputsare given as per circuit diagram.
(ii) Observe the output and verify the truth table.
Result:
Observed output matches theoretical concept.
Precautions:
All connection should be made neat and tight.
Digital lab kits and ICs should be handled with outmost care.
While making connections main voltage should be kept switched off.
Never touch live and naked wires.
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