PEX
(PARASITIC EXCTRACTION)
- written by CVNReddy Seelam
Parasitic Extraction (PEX)
Once your layout has passed DRC and LVS, you're not done yet—because the real silicon won't
behave ideally. That’s where Parasitic Extraction (PEX) comes in, giving you a real-world view of
how layout-induced resistances and capacitances impact your design.
What Is PEX in VLSI?
Parasitic Extraction (PEX) is the process of analyzing the physical layout of an integrated circuit
and extracting the unintentional parasitic resistances (R), capacitances (C), and sometimes
inductances (L) that are introduced by interconnects, vias, and diffusion areas.
These parasitics are inevitable in real silicon and can drastically affect:
• Timing
• Power consumption
• Signal integrity
• Noise margins
Why Are Parasitics Important?
In nanometer nodes, interconnect parasitics can dominate transistor delays. Failing to model them
can result in:
• Setup/Hold violations
• Clock skew
• Crosstalk noise
• Power delivery failures
For instance, a long metal wire connecting two gates may behave like a capacitor, delaying the
signal significantly. In high-speed designs, even small parasitics can kill performance.
PEX Flow – Step by Step
1.Input: Clean Layout :- Post-DRC and LVS-verified GDSII or OASIS layout.
2.Use of Extraction Tool:- Tools like Calibre xRC, StarRC, Quantus QRC, or Assura QRC are
used.
3.Technology Rule Deck:- Provided by the foundry as part of the PDK—contains metal layer info,
spacing, thickness, via resistance, dielectric constants, etc.
4.Netlist Extraction (SPICE):- PEX tool generates a post-layout netlist (.sp) with extracted Rs and
Cs.
5. Re-simulation or STA
The extracted netlist is used for:
• SPICE simulation (for analog/RF)
• Static Timing Analysis (STA) (for digital)
• Power analysis
• EM/IR drop analysis
What Does PEX Extract
Element Explanation Example
Parasitic Resistance (R) Resistance of metal wires and vias Long metal-1 segment, stacked
vias
Parasitic Capacitance (C) Cap between adjacent metal layers M1 to M2, M2 to Substrate
or wires
Parasitic Inductance (L) Magnetic coupling due to high- Clock nets, I/O pads
frequency
Coupling Capacitance(Cc) Capacitance between adjacent nets Aggressor-victim signals
Example: Impact of PEX
Suppose a signal path has a clean delay of 300 ps (pre-layout).
Post-PEX, the delay increases to 410 ps due to:
• Metal resistance of 50Ω
• Coupling capacitance to nearby clocks
• Parasitic cap of 2.5 fF on node
This extra 110 ps could cause timing failure.
Accuracy vs Speed – Extraction Modes
Mode Description Use Case
RC-lite Approximate, fast Early-stage analysis
RC-full Accurate, detailed Sign-off level timing
Coupled RC Includes mutual capacitances Noise, Crosstalk analysis
R-only / C-only Partial extraction Focused deb
Types of Netlists Generated by PEX
• Flat Netlist – All parasitics in one level; used for sign-off.
• Hierarchical Netlist – Preserves module structure; useful for debugging.
• Back-annotated Netlist – Parasitics added to original schematic for re-simulation.
• Spef / Rspf Format – Standardized for timing tools.
Common PEX-Related Errors and Warnings
• Floating nodes – Unconnected parasitics from poor layout.
• Unresolved nets – Missing net mappings due to hierarchy.
• Excessive RC – Indicates long routes or poor metal stack usage.
• Unknown layers – Layout layers not recognized by the tech deck.
• Coupling Dominance – Aggressor nets affecting victims severely
PEX In Analog Vs Digital
Spect Analog Design Digital Design
Accuracy Required Very High High
Tool Type SPICE-based Timing-based
Use Matching, linearity, and gain Timing closure, power
Parasitics Included Full R, C, L Mainly R and C
Popular PEX Tools
Tool Vendor Key Features
Calibre xRC Siemens Sign-off accurate, full RC, SPICE output
StarRC Synopsys Fast digital PEX, STA ready
QRC Cadence Cadence Tight integration with Innovus
Conclusion
Parasitic Extraction isn’t just a backend formality—It’s a window into how your layout behaves in
reality.
DRC and LVS ensure manufacturability and correctness,
PEX ensures performance and reliability.
Thank You
The VLSI Voyager
-C.V.N Reddy Seelam
