Omni ision

Advanced Information
® Preliminary Datasheet

OV9655 Color CMOS SXGA (1.3 MegaPixel) CAMERACHIPTM with OmniPixel® Technology

General Description Applications

• Cellular and Picture Phones
The OV9655 CAMERACHIPTM is a low voltage CMOS
image sensor that provides the full functionality of a • Toys
single-chip SXGA (1280x1024) camera and image • PC Multimedia
processor in a small footprint package. The OV9655 • Digital Still Cameras
provides full-frame, sub-sampled, scaled or windowed
8-bit/10-bit images in a wide range of formats, controlled Key Specifications
through the Serial Camera Control Bus (SCCB) interface.
Active Array Size 1280 x 1024
This product has an image array capable of operating at Core 1.8VDC + 10%
up to 15 frames per second (fps) in SXGA resolution with Power Supply Analog 2.45 to 2.8VDC
complete user control over image quality, formatting and I/O 1.7V to 3.3Va
output data transfer. All required image processing Power 90 mW typical
Active
(15fps SXGA YUV format)
functions, including exposure control, gamma, white Requirements Standby <20 µA
balance, color saturation, hue control, white pixel Temperature Operation -30°C to 70°C
canceling, noise canceling, and more, are also Range Stable Image 0°C to 50°C
programmable through the SCCB interface. In addition, • YUV/YCbCr 4:2:2
OmniVision CAMERACHIPS use proprietary sensor • RGB565/555
technology to improve image quality by reducing or Output Formats (8-bit)
• GRB 4:2:2
eliminating common lighting/electrical sources of image • Raw RGB Data
contamination, such as fixed pattern noise, smearing, Lens Size 1/4"
etc., to produce a clean, fully stable color image. Chief Ray Angle 25°
Maximum SXGA 15 fps
Note: The OV9655 uses a lead-free Image VGA, CIF and 30 fps
Pb package. Transfer Rate down scaling
Sensitivity 1.1 V/(Lux • sec)
S/N Ratio 42 dB
Features Dynamic Range 50 dB
Scan Mode Progressive
• High sensitivity for low-light operation Maximum Exposure Interval 1050 x tROW
• Low operating voltage for embedded portable apps Gamma Correction Programmable
• Standard SCCB interface Pixel Size 3.18 µm x 3.18 µm
Dark Current 15 mV/s at 60°C
• Output support for Raw RGB, RGB (GRB 4:2:2,
Well Capacity 10 K e
RGB565/555), YUV (4:2:2) and YCbCr (4:2:2) Fixed Pattern Noise <0.03% of VPEAK-TO-PEAK
formats Image Area 4.17 mm x 3.29 mm
• Supports image sizes: SXGA, VGA, CIF, and any Package Dimensions 5145 µm x 6145 µm
size scaling down from CIF to 40x30 a. I/O power should be 2.45V or higher when using the internal
• VarioPixel® method for sub-sampling regulator for Core (1.8V); otherwise, it is necessary to provide
• Automatic image control functions including an external 1.8V for the Core power supply.
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB), Figure 1 OV9655 Pin Diagram (Top View)
Automatic Band Filter (ABF), and Automatic
Black-Level Calibration (ABLC) A1 A2 A3 A4 A5

• Image quality controls including color saturation, PWDN AREF1 AGND SIO_C STROBE

gamma, sharpness (edge enhancement), lens B1 B2 B3 B4 B5

correction, white pixel canceling, noise canceling, RESET# AREF2 AVDD SIO_D VSYNC

and 50/60 Hz luminance detection C1 C2 C4 C5

• Supports LED and flash strobe mode D0 NC

OV9655
DOVDD HREF

• Supports scaling D1 D2 D4 D5
D1 D4 NC D9

Ordering Information E1 E2 E3 E4 E5
D2 XVCLK1 DOGND D6 D8
Product Package F1 F2 F3 F4 F5
D3 D5 PCLK DVDD D7
OV09655-VL1A (Color, lead-free) 28-pin CSP2

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Functional Description
Figure 2 shows the functional block diagram of the OV9655 image sensor. The OV9655 includes:
• Image Sensor Array (1300 x 1028 active image array)
• Analog Signal Processor
• A/D Converters
• Digital Signal Processor (DSP)
• Output Formatter
• Timing Generator
• SCCB Interface
• Digital Video Port

Figure 2 Functional Block Diagram

Buffer Buffer

Test
Pattern
Generator
G
DSP Image Video
Analog FIFO
(Lens shading Scaler Port
Processing A/D correction, D[9:0]
de-noise, white/
R black pixel
50/60 Hz correction, auto
white balance,
Auto etc.)
B Detect

Column Sense Amp Exposure/Gain

Detect
Row Select

Image Array
(1300 x 1028)
Registers

SCCB
Clock Video Timing Generator
Interface
Exposure/Gain
Control

XVCLK1 STROBE HREF PCLK VSYNC RESET# PWDN SIO_C SIO_D

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Omni ision Functional Description

Image Sensor Array In general, the combination of the A/D Range Multiplier
and A/D Range Control sets the A/D range and maximum
The OV9655 sensor has an active image array of 1300 value to allow the user to adjust the final image brightness
columns by 1028 rows (1,336,400 pixels). Figure 3 shows as a function of the individual application.
a cross-section of the image sensor array.

Figure 3 Image Sensor Array Digital Signal Processor (DSP)

Microlens This block controls the interpolation from Raw data to
Glass RGB and some image quality control.
• Edge enhancement (a two-dimensional high pass
filter)
• Color space converter (can change Raw data to RGB
or YUV/YCbCr)
Blue Green Red • RGB matrix to eliminate color cross talk
• Hue and saturation control
• Programmable gamma control
• Transfer 10-bit data to 8-bit
Timing Generator • White pixel canceling
• De-noise
In general, the timing generator controls the following
functions:
• Array control and frame generation Output Formatter
• Internal timing signal generation and distribution
This block controls all output and data formatting required
• Frame rate timing prior to sending the image out.
• Automatic Exposure Control (AEC)
• External timing outputs (VSYNC, HREF/HSYNC, and
PCLK) Scaling Image Output
The OV9655 is capable of scaling down the image size
from VGA to 40x30. By using register bits COM14[1]
Analog Signal Processor (0x3E), COM16[0] (0x41), and registers POIDX (0x72),
XINDX (0x74), and YINDX (0x75), the user can output the
This block performs all analog image functions including: desired image size. At certain image sizes, HREF is not
• Automatic Gain Control (AGC) consistent in a frame.
• Automatic White Balance (AWB)

Strobe Mode
A/D Converters The OV9655 has a Strobe mode that allows it to work with
an external flash and LED.
After the Analog Processing block, the bayer pattern Raw
signal is fed to two 10-bit analog-to-digital (A/D)
converters via two multiplexers, one for the G channel and
one shared by the BR channels. These A/D converters Digital Video Port
operate at speeds up to 12 MHz and are fully synchronous
Register bits COM2[1:0] increase IOL/IOH drive current
to the pixel rate (actual conversion rate is related to the
and can be adjusted as a function of the customer’s
frame rate).
loading.
In addition to the A/D conversion, this block also has the
following functions:
• Digital Black-Level Calibration (BLC) SCCB Interface
• Optional U/V channel delay The Serial Camera Control Bus (SCCB) interface controls
• Additional A/D range controls the CAMERACHIP operation. Refer to OmniVision
Technologies Serial Camera Control Bus (SCCB)
Specification for detailed usage of the serial control port.

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Pin Description
Table 1 Pin Description

Pin Location Name Pin Type Function/Description

Power Down Mode Selection - active high, internal pull-down resistor.
Function
A1 PWDN 0: Normal mode
(default = 0)
1: Power down mode
A2 AREF1 VREF Internal voltage reference - connect to ground through 1µF capacitor
A3 AGND Power Analog ground
A4 SIO_C Input SCCB serial interface clock input
A5 STROBE Output Flash strobe signal output
Clears all registers and resets them to their default values.
0: Reset mode
B1 RESET# Input 1: Normal mode

NOTE: This is for REV5 of the OV9655 sensor. For previous REV of the
sensor, this pin is RESET (high for reset).
B2 AREF2 VREF Voltage reference
B3 AVDD Power Analog power supply
B4 SIO_D I/O SCCB serial interface data I/O
B5 VSYNC Output Vertical sync output
C1 D0 Output Output bit[0] - LSB for 10-bit Raw RGB data only
C2 NC — No connection
C4 DOVDD Power Digital power supply for I/O
C5 HREF Output HREF output
D1 D1 Output Output bit[1] - for 10-bit RGB only
D2 D4 Output Output bit[4]
D4 NC — No connection
Output bit[9] - MSB for 10-bit Raw RGB data and 8-bit YUV or
D5 D9 Output
RGB565/RGB555
E1 D2 Output Output bit[2] - LSB for 8-bit YUV or RGB565/RGB555
E2 XVCLK1 Input System clock input
E3 DOGND Power Digital ground
E4 D6 Output Output bit[6]
E5 D8 Output Output bit[8]
F1 D3 Output Output bit[3]
F2 D5 Output Output bit[5]
F3 PCLK Output Pixel clock output
F4 DVDD Power Power supply for digital core logic
F5 D7 Output Output bit[7]

NOTE:
D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB)
D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB)

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Omni ision Electrical Characteristics

Electrical Characteristics

Table 2 Absolute Maximum Ratings

Ambient Storage Temperature -40ºC to +95ºC

VDD-A 4.5 V

Supply Voltages (with respect to Ground) VDD-C 3V

VDD-IO 3V

All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+0.5V

Lead-free Temperature, Surface-mount process 245ºC

ESD Rating, Human Body model 2000V

NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 3 DC Characteristics (-30°C < TA < 70°C)

Symbol Parameter Condition Min Typ Max Unit

VDD-A DC supply voltage – Analog – 2.45 2.5 2.8 V

VDD-C DC supply voltage – Core – 1.62 1.8 1.98 V

VDD-IO DC supply voltage – I/O power – 1.7 – 3.3 V

IDDA Active (Operating) Current See Note a 20 mA

IDDS-SCCB Standby Current 1 mA

See Note b
IDDS-PWDN Standby Current 10 µA

VIH Input voltage HIGH CMOS 0.7 x VDD-IO V

VIL Input voltage LOW 0.3 x VDD-IO V

VOH Output voltage HIGH CMOS 0.9 x VDD-IO V

VOL Output voltage LOW 0.1 x VDD-IO V

IOH Output current HIGH See Note c 8 mA

IOL Output current LOW 15 mA

IL Input/Output Leakage GND to VDD-IO ±1 µA

a. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V

IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 7.5 fps YUV output, no I/O loading
b. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V
IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby
c. Standard Output Loading = 25pF, 1.2KΩ

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Table 4 Functional and AC Characteristics (-30°C < TA < 70°C)

Symbol Parameter Min Typ Max Unit
Functional Characteristics
A/D Differential Non-Linearity + 1/2 LSB
A/D Integral Non-Linearity +1 LSB
AGC Range 18 dB
Red/Blue Adjustment Range 12 dB
Inputs (PWDN, CLK, RESET#)

fCLK Input Clock Frequency 10 24 48 MHz

tCLK Input Clock Period 21 42 100 ns

tCLK:DC Clock Duty Cycle 45 50 55 %

tS:RESET# Setting time after software/hardware reset 1 ms

tS:REG Settling time for register change (10 frames required) 300 ms
SCCB Timing (see Figure 4)

fSIO_C Clock Frequency 400 KHz

tLOW Clock Low Period 1.3 μs

tHIGH Clock High Period 600 ns

tAA SIO_C low to Data Out valid 100 900 ns

tBUF Bus free time before new START 1.3 μs

tHD:STA START condition Hold time 600 ns

tSU:STA START condition Setup time 600 ns

tHD:DAT Data-in Hold time 0 μs

tSU:DAT Data-in Setup time 100 ns

tSU:STO STOP condition Setup time 600 ns

tR, tF SCCB Rise/Fall times 300 ns

tDH Data-out Hold time 50 ns

Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure 5, Figure 6, and Figure 7)

tPDV PCLK[↓] to Data-out Valid 5 ns

tSU D[9:0] Setup time 15 ns

tHD D[9:0] Hold time 8 ns

tPHH PCLK[↓] to HREF[↑] 0 5 ns

tPHL PCLK[↓] to HREF[↓] 0 5 ns

• VDD: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V

• Rise/Fall Times: I/O: 5ns, Maximum
AC SCCB: 300ns, Maximum
Conditions: • Input Capacitance: 10pf
• Output Loading: 25pF, 1.2KΩ to 2.5V
• fCLK: 24MHz

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Omni ision Timing Specifications

Timing Specifications

Figure 4 SCCB Timing Diagram

tF t HIGH tR
tLOW

SIO_C
t HD:STA t HD:DAT t SU:DAT
tSU:STA tSU:STO

SIO_D
IN
t BUF
tAA t DH
SIO_D
OUT

Figure 5 Horizontal Timing

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[9:0] Last Byte Zero First Byte Last Byte

tPDV

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Figure 6 SXGA Frame Timing

1050 x tLINE

VSYNC
tLINE = 1520 tP
15227 tP
4 x tLINE 18453 tP 240 tP

HREF

1280 tP
16 tP 80 tP 117 tP 43 tP
HSYNC

D[9:0] Invalid Data Invalid Data

P0 - P1279
Row 0 Row 1 Row 2 Row 1023
NOTE:
For Raw data, tP = internal pixel clock
For YUV/RGB, tP = 2 x internal pixel clock

Figure 7 VGA Frame Timing

500 x tLINE

VSYNC
tLINE = 800 tP
6413.5 tP
4 x tLINE 6546.5 tP 160 tP

HREF

640 tP
8 tP 40 tP 98.5 tP 21.5 tP
HSYNC

D[9:0] Invalid Data Invalid Data

P0 - P639
NOTE: Row 0 Row 1 Row 2 Row 479
For Raw data, tP = internal pixel clock
For YUV/RGB, tP = 2 x internal pixel clock

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Omni ision Timing Specifications

Figure 8 RGB 565 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[9:2] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[9] R4 G2 D[9]
D[8] D[8]
D[7] G0 D[7]
D[6] B4 D[6]
D[5] R0 D[5]
D[4] G5 D[4]
D[3] D[3]
D[2] G3 B0 D[2]

Figure 9 RGB 555 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[9:2] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[9] X G2 D[9]
D[8] R4 D[8]
D[7] G0 D[7]
D[6] B4 D[6]
D[5] D[5]
D[4] R0 D[4]
D[3] G4 D[3]
D[2] G3 B0 D[2]

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Register Set
Table 5 provides a list and description of the Device Control registers contained in the OV9655. For all register Enable/Disable
bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read.

Table 5 Device Control Register List

Address Register Default

(Hex) Name (Hex) R/W Description

AGC[7:0] – Gain control gain setting

00 GAIN 00 RW
• Range: [00] to [FF]

AWB – Blue channel gain setting

01 BLUE 80 RW
• Range: [00] to [FF]

AWB – Red channel gain setting

02 RED 80 RW
• Range: [00] to [FF]

Vertical Frame Control

Bit[7:6]: AGC[9:8] (see register GAIN for AGC[7:0])
03 VREF 4A RW
Bit[5:3]: VREF end low 3 bits (high 8 bits at VSTOP[7:0]
Bit[2:0]: VREF start low 3 bits (high 8 bits at VSTRT[7:0]

Common Control 1
Bit[7]: Reserved
Bit[6]: CCIR656 format
Bit[5:4]: Reserved
Bit[3:2]: HREF skip option
04 COM1 00 RW 00: No skip
01: YUV/RGB skip every other row for YUV/RGB, skip 2
rows for every 4 rows for Raw data
1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows
for every 8 rows for Raw data
Bit[1:0]: AEC low 2 LSBs (see registers AECH for AEC[15:10] and
AEC for AEC[9:2])

U/B Average Level

05 BAVE 00 RW
Automatically updated based on chip output format

Y/Gb Average Level

06 GbAVE 00 RW
Automatically updated based on chip output format

07 GrAVE 00 – Gr Average Level

V/R Average Level

08 RAVE 00 RW
Automatically updated based on chip output format

Common Control 2
Bit[7:5]: Reserved
Bit[4]: Soft sleep mode
Bit[3:2]: Reserved
09 COM2 01 RW Bit[1:0]: Output drive capability
00: 1x
01: 2x
10: 2x
11: 4x

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

0A PID 96 R Product ID Number MSB (Read only)

0B VER 57 R Product ID Number LSB (Read only)

Common Control 3
Bit[7]: Color bar output
Bit[6]: Output data MSB and LSB swap
Bit[5:4]: Reserved
Bit[3]: Pin selection
1: Change RESET# pin to EXPST_B (frame exposure
0C COM3 00 RW mode timing) and change PWDN pin to FREX (frame
exposure enable)
Bit[2]: RGB 565 format option
0: RGB 565 format
1: Output data average
Bit[1]: Reserved
Bit[0]: Single frame output (used for Frame Exposure mode only)

Common Control 4
Bit[7:4]: Reserved
Bit[3]: One-pin frame exposure option ON/OFF selection
0: OFF
1: ON
Bit[2]: Tri-state option for output clock at power-down period
0D COM4 40 RW
0: Tri-state at this period
1: No tri-state at this period
Bit[1]: Tri-state option for output data at power-down period
0: Tri-state at this period
1: No tri-state at this period
Bit[0]: Reserved

Common Control 5
Bit[7:5]: Reserved
Bit[4]: Slam mode enable
0: Master mode
0E COM5 01 RW 1: Slam mode (used for slave mode)
Bit[3:1]: Reserved
Bit[0]: Exposure step can be set longer than VSYNC time
1: In Normal mode, AEC changes by 1/16 and in Fast
mode, AEC changes by double

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 6
Bit[7]: Output of optical black line option
0: Disable HREF at optical black
1: Enable HREF at optical black
Bit[6]: BLC input selection
0: Use electrical black line as BLC signal
1: Use optical black line as BLC signal
Bit[5:4]: Reserved
0F COM6 42 RW Bit[3]: Enable bias for B/Gr/Gb/R channel
Bit[2]: Output window setting auto/manual selection when mode
is changed
0: Need to manually update window size when working
mode changes
1: Auto change registers HSTART (0x17), HSTOP
(0x18), VSTRT (0x19), and VSTOP (0x1A) when
working mode changes
Bit[1]: Reset all timing when format changes
Bit[0]: Enable ADBLC option

Exposure Value (middle 8-bits)

10 AEC 40 RW Bit[7:0]: AEC[9:2] (see registers AECH for AEC[15:10] and COM1
for AEC[1:0])

Data Format and Internal Clock

Bit[7]: Reserved
11 CLKRC 00 RW Bit[6]: Use external clock directly (no clock pre-scale available)
Bit[5:0]: Internal clock pre-scalar
F(internal clock) = F(input clock)/(Bit[5:0]+1)
• Range: [0 0000] to [1 1111]

Common Control 7
bit[7]: SCCB register reset
0: No change
1: Resets all registers to default values
Bit[6:4]: Format control
000: Full resolution or 15fps VGA
101: 30fps VGA without VarioPixel
12 COM7 00 RW
110: 30fps VGA with VarioPixel
Bit[3:2]: Reserved
Bit[1:0]: Output format selection
00: Raw RGB data
01: Raw RGB interpolation
10: YUV
11: RGB

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 8
Bit[7]: Enable fast AGC/AEC algorithm
Bit[6]: AEC - Step size limit (used only in fast condition and
COM5[0] is low)
0: Fast condition change maximum step is VSYNC
1: Unlimited step size
13 COM8 8F RW Bit[5]: Banding filter ON/OFF
Bit[4]: Reserved
Bit[3]: Enable "AEC time can be less than 1 line" option
Bit[2]: AGC Enable
Bit[1]: AWB Enable
Bit[0]: AEC Enable

Common Control 9
Bit[7]: Reserved
Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
14 COM9 4A RW 101: 64x
110: 128x
Bit[3]: Exposure timing can be less than limit of banding filter
when light is too strong
Bit[2]: Data format - VSYNC drop option
0: VSYNC always exists
1: VSYNC will drop when frame data drops
Bit[1]: Enable drop frame when AEC step is larger than the
Exposure Gap
Bit[0]: Freeze AGC/AEC

Common Control 10
Bit[7]: Set pin definition
1: Set RESET# to SLHS (slave mode horizontal sync)
and set PWDN to SLVS (slave mode vertical sync)
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
15 COM10 00 RW 0: PCLK always output
1: No PCLK output when HREF is low
Bit[4]: PCLK reverse
Bit[3]: HREF reverse
Bit[2]: Reset signal end point option
Bit[1]: VSYNC negative
Bit[0]: HSYNC negative

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Register 16 Control
Bit[7:6]: RGB656 format SAV position option
Bit[5:4]: Automatically add dummy frame option
00: Add dummy frame when gain is greater than 2x
16 REG16 04 RW 01: Add dummy frame when gain is greater than 4x
10: Add dummy frame when gain is greater than 8x
Bit[3:2]: Reserved
Bit[1]: Enable output "AA" and "55 at blanking period
Bit[0]: Reserved

Output Format - Horizontal Frame (HREF column) start high 8-bit (low
17 HSTART 24 RW
3 bits are at HREF[2:0])

Output Format - Horizontal Frame (HREF column) end high 8-bit (low
18 HSTOP C4 RW
3 bits are at HREF[5:3])

Output Format - Vertical Frame (row) start high 8-bit (low 3 bits are at
19 VSTRT 01 RW
VREF[2:0])

Output Format - Vertical Frame (row) end high 8-bit (low 3 bits are at
1A VSTOP F1 RW
VREF[5:3])

Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative
to HREF in pixel units)
1B PSHFT 00 RW
• Range: [00] (no delay) to [FF] (256 pixel delay which accounts for
whole array)

1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)

1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)

Mirror/VFlip Enable
Bit[7:6]: Reserved
Bit[5]: Mirror
0: Normal image
1E MVFP 00 RW 1: Mirror image
Bit[4]: VFlip enable
0: VFlip disable
1: VFlip enable
Bit[3:0]: Reserved

1F LAEC 00 RW Reserved

B Channel ADBLC Result

Bit[7]: Offset adjustment sign
20 BOS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

Gb channel ADBLC result

Bit[7]: Offset adjustment sign
21 GBOS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Gr channel ADBLC result

Bit[7]: Offset adjustment sign
22 GROS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

R channel ADBLC result

Bit[7]: Offset adjustment sign
23 ROS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

24 AEW 78 RW AGC/AEC - Stable Operating Region (Upper Limit)

25 AEB 68 RW AGC/AEC - Stable Operating Region (Lower Limit)

AGC/AEC Fast Mode Operating Region

26 VPT D4 RW Bit[7:4]: High nibble of upper limit
Bit[3:0]: High nibble of lower limit

B Channel Signal Output Bias (effective only when COM6[0] = 1)

Bit[7]: Bias adjustment sign
27 BBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

Gb Channel Signal Output Bias (effective only when COM6[0] = 1)

Bit[7]: Bias adjustment sign
28 GbBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

RGB Channel Pre-gain

Bit[7:6]: Reserved
29 PREGAIN 00 RW Bit[5:4]: G channel pre-gain
Bit[3:2]: R channel pre-gain
Bit[1:0]: B channel pre-gain

Dummy Pixel Insert MSB

Bit[7:4]: 4 MSB for dummy pixel insert in horizontal direction
2A EXHCH 00 RW
Bit[3:2]: HSYNC falling edge delay 2 MSB
Bit[1:0]: HSYNC rising edge delay 2 MSB

Dummy Pixel Insert LSB

2B EXHCL 00 RW
8 LSB for dummy pixel insert in horizontal direction

R Channel Signal Output Bias (effective only when COM6[0] = 1)

Bit[7]: Bias adjustment sign
2C RBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

2D ADVFL 00 RW LSB of insert dummy lines in vertical direction (1 bit equals 1 line)

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

2E ADVFH 00 RW MSB of insert dummy lines in vertical direction

2F YAVE 00 RW Y/G Channel Average Value

30 HSYST 08 RW HSYNC Rising Edge Delay (low 8 bits)

31 HSYEN 30 RW HSYNC Falling Edge Delay (low 8 bits)

HREF Control
Bit[7:6]: HREF edge offset to data output
32 HREF A4 RW
Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP)
Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART)

Array Current Control

33 CHLF 00 RW
• Range: [00] to [FF]

Array Reference Control

34 AREF1 3F RW
• Range: [00] to [FF]

Array Reference Control

35 AREF2 90 RW
• Range: [00] to [FF]

Array Reference Control

36 AREF3 F9 RW
• Range: [00] to [FF]

ADC Control 1
Bit[7:4]: Reserved
Bit[3]: ADC range adjustment
0: 1x range
37 ADC1 04 RW 1: 1.5x range
Bit[2:0]: ADC range adjustment
000: 0.8x
100: 1x
111: 1.2x

ADC Reference Control

38 ADC2 72 RW
• Range: [00] to [FF]

Analog Reference Control

39 AREF4 10 RW
• Range: [00] to [FF]

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Line Buffer Test Option

Bit[7:6]: PCLK output delay option
00: No delay
01: 2 ns
10: 4 ns
11: 6 ns
Bit[5]: Output bit-wise reverse
Bit[4]: UV output value
3A TSLB 0C RW 0: Use normal UV output
1: Use fixed UV value set in registers MANU and MANV
as UV output instead of chip output
Bit[3:2]: YUV output sequence
00: Y U Y V
01: Y V Y U
10: V Y U Y
11: U Y V Y
Bit[1]: 50/60 Hz banding filter auto detection
Bit[0]: Reserved

Common Control 11
Bit[7]: Night mode
0: Night mode disable
1: Night mode enable - Frame rate will adjust based on
COM11[6:5] before AGC gain increases more than 2.
Also, ADVFH and ADVFL will be automatically
3B COM11 80 RW updated.
Bit[6:5]: Night mode insert frame option
00: Normal frame rate
01: 1/2 frame rate
10: 1/4 frame rate
11: 1/8 frame rate
Bit[4:0]: Reserved

Common Control 12
Bit[7]: HREF option
0: No HREF when VREF is low
1: Always has HREF
Bit[6:5]: Reserved
Bit[4]: Night mode speed selection
3C COM12 40 RW 0: Normal
1: Fast
Bit[3]: Contrast expand center selection
0: Use manually entered value at CNST2 (0x57) as
center value
1: Use average value of last frame as center value
Bit[2:0]: Reserved

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 13
Bit[7]: Gamma selection for signal
0: No gamma function
1: Gamma used for Raw data before interpolation
Bit[6]: Reserved
Bit[5]: VSYNC shift option
3D COM13 99 RW 1: VSYNC will shift back 9 lines and width will change to
2 lines
Bit[4]: Reserved
Bit[3]: Enable Y channel delay option
0: Delay UV channel
1: Delay Y channel
Bit[2:0]: Output Y/UV delay

Common Control 14
Bit[7:4]: Reserved
Bit[3]: Black pixel correction ON/OFF selection
0: OFF
1: ON
Bit[2]: White pixel correction ON/OFF selection
3E COM14 0E RW
0: OFF
1: ON
Bit[1]: Zoom function ON/OFF selection
0: OFF
1: ON
Bit[0]: Reserved

Edge Enhancement Adjustment

3F EDGE 88 RW Bit[7:6]: Reserved
Bit[5:0]: Edge enhancement factor

Common Control 15
Bit[7:6]: Data format - output full range enable
00: Output range: [00] to [FF]
01: Output range: [01] to [FE]
1x: Output range: [10] to [F0]
40 COM15 C0 RW
Bit[5:4]: RGB 555/565 option (must set COM7[2] high)
x0: Normal RGB output
01: RGB 565
11: RGB 555
Bit[3:0]: Reserved

Common Control 16
Bit[7:2]: Reserved
Bit[1]: Color matrix coefficient double option
41 COM16 00 RW
Bit[0]: Scaling down ON/OFF selection
0: Normal
1: Scaling down

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 17
Bit[7]: De-noise option
0: De-noise strength fixed
1: De-noise strength auto adjust
Bit[6]: Edge enhancement option
0: Fixed
1: Edge enhancement strength auto adjust
42 COM17 08 RW Bit[5]: Reserved
Bit[4]: Auto digital gain enable
Bit[3]: Reserved
Bit[2]: Select single frame out
Bit[1]: Tri-state output after single frame out
Bit[0]: Banding filter selection
0: 60 Hz banding filter
1: 50 Hz banding filter

43-4E RSVD XX – Reserved

4F MTX1 58 RW Matrix Coefficient 1

50 MTX2 48 RW Matrix Coefficient 2

51 MTX3 10 RW Matrix Coefficient 3

52 MTX4 28 RW Matrix Coefficient 4

53 MTX5 48 RW Matrix Coefficient 5

54 MTX6 70 RW Matrix Coefficient 6

55 BRTN 00 RW Brightness Adjustment

56 CNST1 40 RW Contrast Control Coefficient

57 CNST2 80 RW Contrast Control Coefficient

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Matrix Coefficient Sign

Bit[7:6]: Reserved
Bit[5]: Matrix coefficient 6 sign
0: Plus
1: Minus
Bit[4]: Matrix coefficient 5 sign
0: Plus
1: Minus
Bit[3]: Matrix coefficient 4 sign
0: Plus
58 MTXS 1E RW
1: Minus
Bit[2]: Matrix coefficient 3 sign
0: Plus
1: Minus
Bit[1]: Matrix coefficient 2 sign
0: Plus
1: Minus
Bit[0]: Matrix coefficient 1 sign
0: Plus
1: Minus

59 AWBOP1 91 RW AWB Control Option 1

5A AWBOP2 94 RW AWB Control Option 2

5B AWBOP3 AA RW AWB Control Option 3

5C AWBOP4 71 RW AWB Control Option 4

5D AWBOP5 8D RW AWB Control Option 5

5E AWBOP6 0F RW AWB Control Option 6

5F BLMT F0 RW AWB Blue Component Gain Limit

60 RLMT F0 RW AWB Red Component Gain Limit

61 GLMT F0 RW AWB Green Component Gain Limit

62 LCC1 00 RW Lens Correction Option 1

63 LCC2 00 RW Lens Correction Option 2

64 LCC3 10 RW Lens Correction Option 3

65 LCC4 80 RW Lens Correction Option 4

Lens Correction Control

Bit[7:4]: Reserved
66 LCC5 00 RW
Bit[3:1]: Lens correction parameter output
Bit[0]: Lens correction enable

67 MANU 80 RW Manual U Value (effective only when register TSLB[4] is high)

68 MANV 80 RW Manual V Value (effective only when register TSLB[4] is high)

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

VarioPixel® Selection
Bit[7:4]: Reserved
Bit[3:1]: VarioPixel selection
69 VARO 82 RW
001: No VarioPixel
101: Use VarioPixel
Bit[0]: Reserved

6A BD50MAX 00 RW 50 Hz Banding Filter Maximum Step Setting

Band Gap Reference Adjustment

Bit[7:6]: PLL frequency selection
00: Bypass PLL
01: 4x
6B DBLV 0A RW 10: 6x
11: 8x
Bit[5]: Reserved
Bit[4]: Bypass internal regulator for DVDD
Bit[3:0]: Band gap reference adjustment

6C-6F RSVD XX – Reserved

70 DNSTH 02 RW De-noise Function Threshold Adjustment

71 RSVD XX – Reserved

Pixel Output Index

Bit[7]: Reserved
Bit[6]: Vertical pixel output option
0: Use pixel average data
1: Drop unused pixel data
Bit[5:4]: Vertical pixel output index
00: Normal
01: Output 1 line for every 2 lines
10: Output 1 line for every 4 lines
72 POIDX 00 RW 11: Output 1 line for every 8 lines
Bit[3]: Reserved
Bit[2]: Horizontal pixel output option
0: Use pixel average data
1: Drop unused pixel data
Bit[1:0]: Horizontal pixel output index
00: Normal
01: Output 1 line for every 2 pixels
10: Output 1 line for every 4 pixels
11: Output 1 line for every 8 pixels

Pixel Clock Output Selection

73 PCKDV 01 RW Bit[7:4]: Reserved
Bit[3:0]: Pixel clock output frequency adjustment

74 XINDX 3A RW Horizontal Scaling Down Coefficients

75 YINDX 35 RW Vertical Scaling Down Coefficients

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

76-79 RSVD XX – Reserved

Gamma Curve Highest Segment Slop - calculated as follows:

7A SLOP 18 RW
SLOP[7:0] = (FF - GAM15[7:0] + 1) x 40/30

7B GAM1 02 RW Gamma Curve 1st Segment Input End Point 0x010 Output Value

7C GAM2 07 RW Gamma Curve 2nd Segment Input End Point 0x020 Output Value

7D GAM3 1F RW Gamma Curve 3rd Segment Input End Point 0x040 Output Value

7E GAM4 49 RW Gamma Curve 4th Segment Input End Point 0x080 Output Value

7F GAM5 5A RW Gamma Curve 5th Segment Input End Point 0x0A0 Output Value

80 GAM6 6A RW Gamma Curve 6th Segment Input End Point 0x0C0 Output Value

81 GAM7 79 RW Gamma Curve 7th Segment Input End Point 0x0E0 Output Value

82 GAM8 87 RW Gamma Curve 8th Segment Input End Point 0x100 Output Value

83 GAM9 94 RW Gamma Curve 9th Segment Input End Point 0x120 Output Value

84 GAM10 9F RW Gamma Curve 10th Segment Input End Point 0x140 Output Value

85 GAM11 AF RW Gamma Curve 11th Segment Input End Point 0x180 Output Value

86 GAM12 BB RW Gamma Curve 12th Segment Input End Point 0x1C0 Output Value

87 GAM13 CF RW Gamma Curve 13th Segment Input End Point 0x240 Output Value

88 GAM14 EE RW Gamma Curve 14th Segment Input End Point 0x2C0 Output Value

89 GAM15 EE RW Gamma Curve 15th Segment Input End Point 0x340 Output Value

8A RSVD XX – Reserved

Common Control 18
Bit[7:4]: Reserved
8B COM18 04 RW
Bit[3]: Zoom mode under VGA timing
Bit[2:0]: Reserved

Common Control 19
Bit[7:4]: Reserved
8C COM19 0C RW Bit[3:2]: UV adjust option
Bit[1]: Reserved
Bit[0]: UV average ON/OFF

Common Control 20
Bit[7:5]: Reserved
8D COM20 00 RW
Bit[4]: Color bar test mode
Bit[3:0]: Reserved

8E-91 RSVD XX – Reserved

92 DMLNL 00 RW Frame Dummy Line LSBs

93 DMLNH 00 RW Frame Dummy Line MSBs

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

94-9C RSVD XX – Reserved

9D LCC6 00 RW Lens Correction Option 6

9E LCC7 00 RW Lens Correction Option 7

9F-A0 RSVD XX – Reserved

Exposure Value - AEC MSB 5 bits

Bit[7:6]: Reserved
A1 AECH 40 RW
Bit[5:0]: AEC[15:10] (see registers AEC for AEC[9:2] and COM1 for
AEC[1:0])

A2 BD50 9D RW 1/100s Exposure Setting for 50 Hz Banding Filter

A3 BD60 03 RW 1/120s Exposure Setting for 60 Hz Banding Filter

Common Control 21
A4 COM21 70 RW Bit[7:4]: Reserved
Bit[3:0]: Digital gain value

A5 RSVD 80 – Reserved

A6 GREEN 80 RW AWB Green Component Gain Setting

A7 VZST 10 RW VGA Zoom Mode Vertical Start Line

A8-B4 RSVD XX – Reserved

Common Control 22
Bit[7:6]: Reserved
B5 COM22 20 RW
Bit[5]: BLC ON/OFF selection
Bit[4:0]: Reserved

B6 RSVD XX – Reserved

B7 FRSTL EE RW One-Pin Frame Exposure Reset Time Control Low 8 Bits

B8 FRSTH EE RW One-Pin Frame Exposure Reset Time Control High 8 Bits

B9-BB RSVD XX – Reserved

BC ADBOFF 00 RW ADC B channel offset setting

BD ADROFF 00 RW ADC R channel offset setting

BE ADGbOFF 00 RW ADC Gb channel offset setting

BF ADGrOFF 00 RW ADC Gr channel offset setting

C0-C3 RSVD XX – Reserved

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 23
Bit[7]: Strobe enable
1: Start Strobe mode
Bit[6]: Strobe output pulse polarity control
Bit[5:4]: Reserved
Bit[3:2]: Xenon mode strobe pulse width
00: 1 line
01: 2 lines
10: 3 lines
11: 4 lines
C4 COM23 EE RW Bit[1:0]: Strobe mode
00: Xenon mode
01: LED1&2 mode
10: LED1&2 mode
11: LED3 mode

Notes:
1 When in LED1&2 mode, registers ADVFL (0x2D) and ADVFH (0x2E)
will serve as pulse width control
2 Only detect bit 7 rising edge to start sequence
3 Clear bit 7 after initiating

C5 BD60MAX 2E RW 60 Hz Banding Filter Maximum Step Setting

C6 RSVD XX – Reserved

Common Control 24
C7 COM24 80 RW Bit[7:3]: Reserved
Bit[2:0]: Pixel clock frequency selection

C8-CF RSVD XX – Reserved

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

24 Proprietary to OmniVision Technologies Version 1.3, December 15, 2005

Omni ision Package Specifications

Package Specifications
The OV9655 uses a 28-pin Chip Scale Package 2 (CSP2). Refer to Figure 10 for package information, Table 6 for package
dimensions and Figure 11 for the array center on the chip.

Note: For OVT devices that are lead-free, all part marking letters are
lower case. Underlining the last digit of the lot number indicates CSP2 is
used.

Figure 10 OV9655 Package Specifications

A S1 J1
1 2 3 4 5 5 4 3 2 1

S2

A A
J2
B B

abcd
wxyz
C C
B
D D

E E

F F

Top View (Bumps Down) Bottom View (Bumps Up)

Center of BGA (die) =
Glass Center of the package
Die Part Marking Code:
w - OVT Product Version
C3 x - Year the part is assembled
C2 C y - Month the part is assembled
z - Wafer number
C4 abcd - Last four digits of lot number
Side View
C1

Table 6 CSP Package Dimensions

Parameter Symbol Min Nominal Max Unit

Package Body Dimension X A 5120 5145 5170 µm
Package Body Dimension Y B 6120 6145 6170 µm
Package Height C 945 1005 1065 µm
Ball Height C1 150 180 210 µm
Package Body Thickness C2 780 825 870 µm
Cover Glass Thickness C3 475 500 525 µm
Airgap Between Cover Glass and Sensor C4 30 45 60 µm
Ball Diameter D 320 350 380 µm
Total Pin Count N 28 (2 NC)
Pin Count X-axis N1 5
Pin Count Y-axis N2 6
Pins Pitch X-axis J1 800 µm
Pins Pitch Y-axis J2 800 µm
Edge-to-Pin Center Distance Analog X S1 942.5 973 1002.5 µm
Edge-to-Pin Center Distance Analog Y S2 1042.5 1073 1102.5 µm

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Sensor Array Center

Figure 11 OV9655 Sensor Array Center

A1 A2 A3 A4 A5
4172 μm
A rray C enter
(-85.4 μm, 394.5 μm)
3288 μm

S ens or
P ac kage C enter
A rray
(0,0)

OV 9655

TOP V IE W

NOT E S : 1. T his drawing is not to s cale and is for reference only.

2. As mos t optical as s emblies invert and mirror the image, the chip is typically mounted
with pins A1 to A5 oriented down on the P C B .

26 Proprietary to OmniVision Technologies Version 1.3, December 15, 2005

Omni ision Package Specifications

IR Reflow Ramp Rate Requirements

OV9655 Lead-Free Packaged Devices

Note: For OVT devices that are lead-free, all part marking letters are
lower case

Figure 12 IR Reflow Ramp Rate Requirements

300.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
280.0

260.0

240.0

220.0

200.0

180.0
Temperature ( C )

160.0

140.0

120.0

100.0

80.0

60.0

40.0

20.0
0.0 0.6 1.1 1.6 2.2 2.8 3.3 3.9
0.0
-22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369
Time (sec)

-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)

Table 7 Reflow Conditions

Condition Exposure
Average Ramp-up Rate (30°C to 217°C) Less than 3°C per second
> 100°C Between 330 - 600 seconds
> 150°C At least 210 seconds
> 217°C At least 30 seconds (30 ~ 120 seconds)
Peak Temperature 245°C
Cool-down Rate (Peak to 50°C) Less than 6°C per second
Time from 30°C to 245°C No greater than 390 seconds

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OV9655 Color CMOS SXGA (1.3 MegaPixel) OmniPixel® CAMERACHIP™ Omni ision

Note:

• All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.

• OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).

• Reproduction of information in OmniVision product documentation and specifications is

permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

• This document is provided with no warranties whatsoever, including any warranty of

merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.

• ‘OmniVision’, ‘CameraChip’, and ’VarioPixel’ are trademarks of OmniVision Technologies, Inc.

All other trade, product or service names referenced in this release may be trademarks or
registered trademarks of their respective holders. Third-party brands, names, and trademarks are
the property of their respective owners.

For further information, please feel free to contact OmniVision at info@ovt.com.

OmniVision Technologies, Inc.

1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000

28 Proprietary to OmniVision Technologies Version 1.3, December 15, 2005

Omni ision TM

REVISION CHANGE LIST

Document Title: OV9655 Datasheet Version: 1.0

DESCRIPTION OF CHANGES
• Initial Release
Omni ision TM

REVISION CHANGE LIST

Document Title: OV9655 Datasheet Version: 1.1

DESCRIPTION OF CHANGES
The following changes were made to version 1.0:
• In Table 5 on page 11, changed description for register bit COM4[3] (0x0D) from
“Reserved” to “One-pin frame exposure option ON/OFF selection”
• In Table 5 on page 11, changed description for register bit COM5[7] (0x0E) from
“System clock selection. If the system...” to “Reserved”
• In Table 5 on page 12, changed description for register bit COM6[2] (0x0F) from
“Reserved” to “Output window setting auto/manual selection when mode is changed”
• In Table 5 on page 17, changed description for register bits TSLB[7:6] (0x3A) from
“Reserved” to “PCLK output delay option”
• In Table 5 on page 17, changed description for register bit COM11[0] (0x3B) from
“Manual banding filter mode” to “Reserved”
• In Table 5 on page 21, added name, description, and default value for register 0x69
(previously RSVD, now VARO)
• In Table 5 on page 21, changed name and description for register 0x6A from
“MBD” and “Manual Banding Filter Value (effective only when COM11[0] is high)” to
“BD50MAX” and “50 Hz Banding Filter Maximum Step Setting,” respectively
• In Table 5 on page 23, changed name of register 0x9D from “LCC5” to “LCC6”
• In Table 5 on page 23, changed description of register 0x9D from “Lens Correction
Option 5” to “Lens Correction Option 6”
• In Table 5 on page 23, changed name of register 0x9E from “LCC6” to “LCC7”
• In Table 5 on page 23, changed description of register 0x9E from “Lens Correction Option
6” to “Lens Correction Option 7”
• In Table 5 on page 23, added name, description, and default value for register 0xB7
(previously RSVD, now FRSTL)
• In Table 5 on page 23, added name, description, and default value for register 0xB8
(previously RSVD, now FRSTH)
• In Table 5 on page 23, changed register 0xC0 from COM23 to RSVD
• In Table 5 on page 24, changed name of register 0xC4 from “COM24” to “COM23”
Omni ision TM

DESCRIPTION OF CHANGES (CONTINUED)

• In Table 5 on page 24, changed description of register 0xC4 from “Common Control 24”
to “Common Control 23”
• In Table 5 on page 24, changed name and description for register 0xC5 from
“BDMAX” and “Banding Filter Max Step Setting” to “BD60MAX” and “60 Hz Banding
Filter Maximum Step Setting,” respectively
• In Table 5 on page 24, changed name of register 0xC7 from “COM25” to “COM24”
• In Table 5 on page 24, changed description of register 0xC7 from “Common Control 25”
to “Common Control 24”
• On page 2, changed Figure 2, Functional Block Diagram
Omni ision TM

REVISION CHANGE LIST

Document Title: OV9655 Datasheet Version: 1.2

DESCRIPTION OF CHANGES
The following changes were made to version 1.1:
• Under Features on page 1, changed bulleted item from “Supports image sizes: SXGA,
VGA, and any size scaling down from VGA to 40x30” to “Supports image sizes: SXGA,
VGA, CIF, and any size scaling down from CIF to 40x30”
• Under Key Specifications on page 1, added table footnote for I/O Power Supply that reads
“I/O power should be 2.45V or higher when using the internal regulator for Core (1.8V);
otherwise, it is necessary to provide an external 1.8V for the Core power supply.”
• Under Key Specifications on page 1, changed Chief Ray Angle from “TBD” to “25°”
• Under Key Specifications on page 1, changed Sensitivity from “TBD” to “1.1 V/Lux-sec”
• Under Key Specifications on page 1, changed S/N Ratio from “TBD” to “42 dB”
• Under Key Specifications on page 1, changed Dynamic Range from “TBD” to “50 dB”
• Under Key Specifications on page 1, changed Dark Current from “TBD” to
“15 mV/s at 60°C”
• Under Key Specifications on page 1, changed Well Capacity Range from “TBD” to
“10 K e”
• In Figure 13 on page 24, changed callout C3 to measure from thickness of glass and added
callout C4 to measure airgap from glass to die.
• In Table 6 on page 24, changed C3 parameter name from “Thickness of Glass Surface to
Wafer” to “Cover Glass Thickness”
• In Table 6 on page 24, changed C3 Minimum, Nominal, and Maximum specifications
from “505, 545, and 585” to “475, 500, and 525”
• In Table 6 on page 24, added C4 parameter, Airgap Between Cover Glass and Sensor, and
Minimum, Nominal, and Maximum specifications “30, 45, and 60”, respectively
Omni ision TM

REVISION CHANGE LIST

Document Title: OV9655 Datasheet Version: 1.3

DESCRIPTION OF CHANGES
The following changes were made to version 1.2:
• In Figure 1 on page 1, changed name for pin B1 to “RESET#”
• In Figure 2 on page 2, changed reference to reset from “RESET” to “RESET#”
• In Table 1 on page 4, changed pin name for pin B1 to “RESET#”, pin type from
“Function” to “Input”, and changed pin description to:
Clears all registers and resets them to their default values
0: Reset mode
1: Normal mode
NOTE: This is for REV5 of the OV9655 sensor. For previous REV of the
sensor, this pin is RESET (high for reset).
• Changed all references to RESET# pin from “RESET” to “RESET#”
• In Table 5 on page 11, changed default value for register VER (0x0B) from “55” to “57”