Twisted-Pair Interface

and
Manchester
Encoder/Decoder

• 83C694D

Data sheet
 83C694D

TABLE OF CONTENTS
1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 DOCUMENT SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 MANCHESTER ENCODER/DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 MANCHESTER DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 COLLISION TRANSLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 TP DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 TP DIFFERENTIAL RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.7 LOOPBACK FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.8 LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.9 AUI/TP AUTOSELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.10 JABBER AND SQE TEST FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.11 STATUS INDICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.12 TEST MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.0 DC ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

i
83C694D

LIST OF ILLUSTRATIONS
Figure Title Page
1-1 SYSTEM BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1-2 83C694C BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2-1 CRYSTAL CONNECTION DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2-2 AUI TRANSMIT PATH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2-3 AUI RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2-4 ZENER DIODE VOLTAGE REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-5 TWISTED PAIR TRANSMIT PATH AND TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2-6 TWISTED PAIR RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3-1 83C694C PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5-1 TRANSMIT TIMING - START OF TRANSMISSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5-2 TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 0) . . . . . . . . . . . . . . . . . 21
5-3 TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 1) . . . . . . . . . . . . . . . . . 22
5-4 TRANSMIT TIMING - LINK TEST PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5-5 RECEIVE TIMING - START OF PACKET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5-6 RECEIVE TIMING - END OF PACKET (LAST BIT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 23
5-7 RECEIVE TIMING - END OF PACKET (LAST BIT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 24
5-8 COLLISION TIMING (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5-9 COLLISION TIMING (TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5-10 SQE TEST TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5-11 LOOPBACK TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5-11 TEST LOADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6-1 44-PIN PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LIST OF TABLES
Table Title Page
3-1 PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4-1 DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5-1 AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5-2 83C694C TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ii
INTRODUCTION 83C694D

1.0 INTRODUCTION
1.1 DOCUMENT SCOPE 1.3 GENERAL DESCRIPTION
This document describes the function and opera- The 83C694D is used for applications where
tion of the 83C694D Twisted-Pair Interface and Twisted-Pair Interface (TPI) and/or Attachment Unit
Manchester Encoder/Decoder. It includes a de- Interface (AUI) functions are required. Its two main
scription of external logic necessary for the efficient functions are to:
use of this device and its proper role in the chip set
which includes the 83C690 and 83B692 as shown 1. Receive a digital data stream from a low-level
in Figure 1-1. Figure 1-2 provides a functional block input signal and
diagram of the 83C694D chip itself. 2. Convert a digital output data stream into an
analog high-current signal for transmission
1.2 FEATURES across a network cable.
Features of the 83C694D include: This means that the 83C694D serves as the logical
link between a network cable on one end and a
• Twisted-Pair interface solution for IEEE 802.3 digital controller chip (such as the 83C690) on the
10BaseT Standard other end.
• Compatible with Ethernet II (10BASE5) and To accomplish these two functions, the 83C694D
Cheapernet (10BASE2) IEEE 802.3 Stand- consists of these components: Manchester en-
ards coder/decoder, balanced drivers and receivers, on-
• Smart Squelch© digital noise filter at receive board crystal oscillator, signal translator, diagnostic
and collision inputs to reject noise and digital circuit, and protocol timers and state machines.
noise on twisted-pair receive inputs. The remainder of this data sheet contains the fol-
• Direct connection to the transceiver (AUI) ca- lowing information:
ble Section 2 discusses the system architecture in-
• 16V fault protection at the AUI transmitter in- cluding an explanation of all chip circuits.
terface
Section 3 provides pin descriptions.
• 10 Mbps Manchester encoding/ decoding with
Section 4 provides DC Operating Characteristics.
receive clock recovery
• Low power, 1.25µ CMOS technology Section 5 provides AC Operating Characteristics
including Interface Timing diagrams.
• TTL/MOS-compatible controller interface
Section 6 provides the PLCC package diagram of
• Externally-selectable half- or full-step modes this chip.
of operation at AUI TX± outputs
• Loopback capability for diagnostics
• Single station interface operation
• Link test generation and digital equalization for
twisted-pair transmitter
• Automatic phase detection
• AUI/TP autoselect
• Built-in LED drivers for transmit, receive, link
test and polarity status indicators

1
83C694D INTRODUCTION

ETHERNET
TX+/-

10Base5
RX+/-

AUI
CD+/-

TXE
TXD TX+/-

CHEAPERNET
83B692

10Base2
83C690
BUFFER RX+/- ETHERNET
MEMORY TRANSCEIVER
802.3
ETHERNET
LAN CRS CD+/-
CONTROLLER RXD 83C694C
RXC
COL MANCHESTER
TXC ENCODER/ TPX1+/-
DECODER TPX2+/-
Transmit

Twisted Pair
Filter

10BaseT
TPR+/-
PC BUS Receive
INTERFACE Filter

FIGURE 1-1. SYSTEM BLOCK DIAGRAM

2
INTRODUCTION 83C694D

AUI
COLLISION LNK
RECEIVER

CD+
COLLISION JABBER
CD-
DECODER

MODE1 MODE2
REPEATER
TP COL LOGIC LBK
RECEIVER
SMART COL
TPR+ SQUELCH COLLISION
DETECT MPE
TPR- LINK TEST LNK
RECEIVE

POLARITY RXC
CORRECT PLL CRS
DECODER
AUI
RECEIVER RXD

RX+

RX-
LBKCTL
LOOPBACK
FUNCTIONS

AUI CRYSTAL X1
DRIVER OSCILLATOR
TX+ X2
20 MHz
TX-

LNK LBK
SEL
MODE1
TXCTL
TXC
LINK ENCODER
TRANSMIT TXE
BEAT CONTROL
TXD

TP
DRIVER
LNK
2 JABBER
TPX+ DETECT LED TPOL
DRIVERS
TPX- RLED
2

JABBER XLED

DIGITAL EQUALIZATION

FIGURE 1-2. 83C694C BLOCK DIAGRAM

3
83C694D ARCHITECTURE

2.0 ARCHITECTURE
The 83C694D can be used as an AUI device or as • Jabber & SQE Test Functions
a twisted-pair interface device.
• Status Indications
When used in combination TPI/AUI applications, The rest of this section describes each of these
the 83C694D is part of a three-device set that circuits in more detail, including suggestions, where
implements the complete IEEE 802.3-compatible appropriate, for designing external circuits consis-
network node electronics (see Figure 1-1). tent with the 802.3 standard.
The 83C690 Ethernet LAN Controller (ELC) and the
83B692 Ethernet Transceiver (ET) comprise the 2.1 OSCILLATOR
other two devices in the set. The 83C690 provides Control is provided either by a 20 MHz, parallel
media access protocol functions and performs buff- resonant crystal connected between X1 and X2, or
er management tasks, while the 83B692 serves as by an external clock connected at X1. The oscilla-
a coaxial cable line driver/receiver and collision tor’s 20 MHz output is divided in half to generate
detector. the 10 MHz transmit clock for the Ethernet LAN
controller and to provide the internal clock signals
The 83C694D Twisted-Pair Interface provides the for the encoding and decoding circuits.
interface between the 83C690 ELC and the 83B692
ET. When transmitting, the device converts non-re- Figure 2-1 provides a diagram of this connection.
turn-to-zero (NRZ) data from the controller into
Manchester encoded data, then sends this data to
the transceiver.

When receiving, the device reverses the process X1

using an analog phase-locked loop that decodes 10
Mbit/sec signals with up to ±20 nsec of jitter.

When the 83C694D is used as a twisted-pair (TP)

20 MHz CL - CP
interface, its on-chip transmitter and receiver (sepa-
rate from the AUI inputs and outputs) connect to the
network through a transformer and filter. In this
application, the 83C694D is used with the 83C690
X2
providing controller and protocol functions, and the
83B692 is not used.

The 83C694D Twisted-Pair Interface is comprised

of these functional blocks:
• Oscillator CL = Load capacitance specified by crystal manufacturer

• Manchester Encoder and Differential Driver CP = Total parasitic capacitance including:

a) 83C694C input capacitance between X1 and X2
• Manchester Decoder (typically 5 pF)
• Collision Translator b) PC board traces, plated through holes, socket capacitances

• Loopback Capabilities
• TP Differential Driver FIGURE 2-1. CRYSTAL CONNECTION
DIAGRAM
• TP Differential Receiver
• Link Test Function
• AUI / TP Autoselect

4
ARCHITECTURE 83C694D

2.2 MANCHESTER ENCODER/ 2.3 MANCHESTER DECODER

DIFFERENTIAL DRIVER Decoding is accomplished by a differential input
Data encoding and transmission begins when the receiver circuit and an analog phase-locked loop
transmit enable input (TXE) goes high and contin- that separates the Manchester-encoded data
ues as long as the TXE remains high. It is essential stream into clock signals and NRZ data.
that the transmit enable and transmit data inputs
meet the setup and hold time requirements for the To prevent noise at the AUI RX+ or RX- input from
rising edge of the transmit clock. falsely triggering the decoder, a squelch circuit re-
jects signals with pulse widths less than 20 nsec
Transmission ends when the transmit enable input (negative going), or with levels less than -175 mV.
goes low. The last transition occurs at the center of When the input exceeds the squelch limits, the
the bit cell if the last bit is one, or at the boundary analog phase-locked loop locks onto the incoming
of the bit cell if the last bit is zero. signal and the 83C694D decodes a data frame.
The carrier sense (CRS) is activated, and the re-
The AUI differential line driver, which has the ability ceive data (RXD) and receive clock (RXC) become
to drive up to 50 meters of twisted-pair AUI/Ethernet available within five bit times. At the end of a frame,
transceiver cable, provides the emitter-coupled when the normal mid-bit transition on the differential
logic (ECL) level signals. input ceases, carrier sense is de-activated. The
receive clock remains active for an additional five
With the SEL input, select one of two modes, full-
bit times. Figures 5-4 through 5-6 illustrate the
step or half-step. When SEL is low, TX+ is positive
receive timing. An external interface circuit for RX+
in relation to TX- in the idle state. When SEL is high,
and RX- might be designed like Figure 2-3.
TX+ and TX- are equal in the idle state. Figures 5-1
through 5-3 illustrate AUI transmit timing. An exter- To avoid signal corruption caused by excessive
nal interface circuit utilizing these signals might voltage fluctuation on the power supply, it is desir-
resemble Figure 2-2. In such a configuration, the able to externally implement a voltage regulation
transmit interface circuit could utilize an isolation system consisting of a 5.1-volt zener diode. Typi-
transformer leading to the 83B692 which would cally, as shown in Figure 2-4, the diode’s cathode
then drive the coax signal to the network. Another is connected to pin 20, pin 23, the VCC side of the
option would use the AUI connector which would go OSR resistor, the VCC side of the BSR resistor, and
to external equipment. a 510Ω 1⁄4-Watt resistor which goes from the
zener’s cathode to the 12-volt power
supply.
AUI
CONNECTOR

RX+ or CD+
0.02µ F

+5V
39.2Ω 1%

TX+ 150Ω 1%
0.02µF
RX- or CD-
83B692
39.2Ω 1%
150Ω 1% ETHERNET COA
TRANSCEIVER CABL

TX-
0.1µF

FIGURE 2-2. AUI TRANSMIT PATH FIGURE 2-3. AUI RECEIVE PATH

5
83C694D ARCHITECTURE

+12V (circuit board)

510Ω (1/4 watt)

cathode
0.1 µ F 10ΚΩ 31.6ΚΩ
5.1V zener
anode

BSR OSR VCC VCC

ground (pin 32) (pin 35)
(circuit board)

83C694C

FIGURE 2-4. ZENER DIODE VOLTAGE REGULATION FOR 12 VOLTS

It is also helpful to place a decoupling capacitor at the start of the pulse; however, halfway through
between the diode’s cathode and ground as shown the pulse TPX2 turns off, thereby reducing the
in Figure 2-4. amplitude after 50 ns. A narrow pulse is transmitted
at the same amplitude as the first half of the wide
2.4 COLLISION TRANSLATOR pulses. The resistor ratio is calculated to produce
the best signal wave shape at the receiving end
When the 83C694D is used as an AUI device, a assuming a UTP cable length of 100 meters.
separate Ethernet transceiver detects collisions on
the coaxial cable and generates a 10 MHz signal, Figure 2-6 shows the basic twisted-pair transmit
which is monitored by the 83C694D through the path along with its timing and one possible external
collision detect pins. The presence of the signal transmit interface design. Typical values for resis-
activates the collision detect (CD) pin connected to tance on TPX2 pins are 261Ω, while TPX1 pins use
the 83C690 causing the controller to stop transmit- 65Ω. The 2.4KΩ parallel resistor is used to match
ting. The collision detect output is deactivated the output resistance of the transmitter to the
within 160 nsec. after the absence of the 10 MHz twisted-pair cable.
signal. Figure 5-7 illustrates the collision timing. An
external interface circuit for CD+ and CD- is de- At the receive end of the cable, a 100Ω termination
signed exactly like an external interface for RX+ resistor is commonly used. To verify the operation
and RX-. See Figure 2-3. of the circuit, measure the TPX signals differentially.

In designing the external circuits to connect the

2.5 TP DIFFERENTIAL DRIVER 83C694D transmit outputs to the cable, use a trans-
The TP driver can transmit through up to 100m of mit filter followed by an isolation transformer and, in
unshielded twisted-pair (UTP) cable. The driver the most practical applications, a common mode
includes a circuit for transmit equalization, which choke for FCC compliance. The common mode
attenuates low frequency components of the trans- choke may not always be needed in every applica-
mit waveform. This reduces the zero crossing jitter tion; however, the isolation transformer is always
of the received signal and avoids the use of a needed and the transmit filter is strongly recom-
receive equalizer. mended; without it, high frequency radiation may
exceed FCC limits.
There are two pulse widths transmitted: 50 nsec
and 100 nsec. When a pulse width of 100 nsec is
sent, both drivers (TPX1+ and TPX2+) turn on and 2.6 TP DIFFERENTIAL RECEIVER
drive a high level. This provides a greater amplitude

6
ARCHITECTURE 83C694D

261Ω

TPX2+
Common Mode
65Ω Choke
TPX+
TPX1+
Transmit
2.4ΚΩ Filter
TPX1-
65Ω TPX-
Isolation Twisted Pair
Transformer Cable
TPX2-
261Ω

100 nsec 50 nsec

FIGURE 2-6. TWISTED-PAIR TRANSMIT PATH AND TIMING

The signal received from the unshielded cable can An external interface circuit for TPR+ and TPR-
be noisy, so minimum voltage and timing limits must might be designed like Figure 2-5.
be met before the receiver logic is enabled. A
"smart squelch"© digital noise filter is used in addi- 2.7 LOOPBACK FUNCTION
tion to the analog squelch circuit in the receiver.
When the loopback input goes high it causes the
The smart squelch circuit provides extra protection
83C694D to send serial data from the transmit data
against false collisions and false link connections.
input through the encoder, and back through the
If the input polarity is reversed, it will be automat- phase-locked loop and decoder to the receive data
ically detected and corrected. When this happens, output. The transmit driver is in the idle state during
the TPOL output pin will go high to signal the loopback mode and the receiver circuitry and colli-
controller or to turn off the polarity indicator LED. sion detection are disabled. Loopback can be en-
abled during either AUI or TP (10BaseT) operation.
The phase-locked loop and Manchester decoder Transmit data is always looped back during TP
are the same circuits used by the AUI receiver. operation, simulating the physical broadcast char-
acteristic of 802.3 coaxial cable networks.

Common Mode
Choke
TP+ Receive TPR+
Filter 100Ω 1%
TP- TPR-
Twisted Pair Isolation
Cable Transformer

FIGURE 2-5. TWISTED-PAIR RECEIVE PATH

7
83C694D ARCHITECTURE

The 83C694D supports the IEEE 802.3 loopback 2.11 STATUS INDICATIONS
design (section 14.2.1.3) which provides for con- To assist in installation and management of the
tinuous loopback from transmit to receive in normal network, indicator LEDs can be driven by four out-
operation. This means that transmitted data is al- puts from the 83C694D. These show the result of
ways looped back during TP operation, simulating Link Test, polarity check, and transmit or receive
the physical broadcast characteristics of 802.3 co- activity.
axial cable networks.
An LED test feature is built into the 83C694D. All
2.8 LINK TEST FUNCTION LEDs turn on for 2/3 second after a reset to the
device.
Each TP driver transmits a short positive pulse
periodically when it is not sending data as shown in
Figure 5-4. These pulses are received at the other 2.12 TEST MODE
end of the TP cable, signalling that the link is Three test modes can be selected when the SEL
operating correctly. The time between link test pin is set to intermediate voltages. These modes
pulses is compared to the expected range at the and their corresponding voltages are:
receiver, to avoid false detection of noise pulses as • Internal counter speedup (1.75 V)
link test pulses.
• RXC and RXD enable (2.5 V)
If the link test fails (no pulses or data received in a
fixed time period), then the LNK pin is set high and • Output tristate (3.5 V)
data transmit and receive on the TP interface is Internal counter speedup is used for fast board-
disabled. level testing of timed functions such as LED power-
up blink and link test pulse period.
2.9 AUI/TP AUTOSELECT
RXC and RXD enable is used to test internal VCO
The 83C694D can automatically select which me-
functions without using a full data packet receive.
dia to transmit and receive on, based on the link test
state. If the link test fails, the AUI transmitter and Output tristate is used during board-level testing to
receiver are enabled while the TP transmitter, re- enable short/open testing. It is also used to test
ceiver, and loopback are disabled. If link test other devices resident on the board. This function
passes, the AUI operation is disabled and TP op- does not tristate transmit (pins 22-27) or X2 outputs.
eration is re-enabled. The only exception to this is
when MODE1 is set low and TP operation is en-
abled continuously.

2.10 JABBER AND SQE TEST FUNCTIONS

If TXE is high for greater than 46 ms, the TP
transmitter will be disabled and COL will go active
high. If TXE then goes low for more than 368 ms,
the TP transmitter will be re-enabled and COL will
go low.

In TP operation, a short pulse will be output on COL

after each packet is transmitted. This is required as
a test of the TP transmit/receive path, and is called
SQE Test or CD Heartbeat.

8
PIN DESCRIPTION 83C694D

3.0 PIN DESCRIPTION

Figure 3-1 illustrates the signal names and pin locations on the 44-pin PLCC 83C694D package. Table
3-1 lists the signal names and descriptions for the 83C694D.

TPR+

TPR-
RES

CRS

RXD

COL

RX+
RXC

CD+

CD-
NC
6 5 4 3 2 1 44 43 42 41 40
SEL 7 39 RX-

LNK 8 38 BSR

TPOL 9 37 TST

GND 10 36 NC

GND 11 35 VCC

GND 12 34 VCC

GND 13 33 VCC

RLED 14 32 VCC

XLED 15 31 MODE2

LBK 16 30 MODE1

X1 17 29 CAP
18 19 20 21 22 23 24 25 26 27 28
TPX1+

TPX2+
TXD

TX-
TPX1-
TPX2-
TXC

OSR
TX+
TXE
X2

FIGURE 3-1. 83C694C 44-PIN PLCC PACKAGE DRAWING

9
83C694D PIN DESCRIPTION

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

1 COL Collision Detect O A 10 MHz (+25%,-15%) signal at the CD

inputs (DTE mode) produces a logic high at
the COL output. When no signal is present at
the CD inputs, the COL output goes low. In
10BaseT operation, the COL output goes high
when TPR+ and TPR- are active while a
packet is being transmitted on TPX+/TPX-.

COL also goes high during SQE test or jabber

condition.

2 NC No Connect I Do not connect any circuitry to this pin.

3 RXD Receive Data O This is the NRZ data output from the on-chip
decoder and phase-locked loop. This signal
should be sampled by the controller at the
rising edge of receive clock. A high level is
binary "one", a low level is binary "zero".

4 CRS Carrier Sense O CRS (DTE mode) goes high when valid data
is presen t at the RX+/RX- inp uts or
TPR+/TPR- inputs. It goes low after the last
bit is received at the inputs.

5 RES Reset/Synch I When RES is low, all internal nodes are set to
a known state except for internal clock distri-
bution. This improves testing procedures.
Normal operation is enabled on the rising
edge of RES and while RES is high. The RES
pin includes an internal pull up resistor, so it
may be left open if unused.

6 RXC Receive Clock O When the phase-locked loop acquires a valid

receive signal, a 10MHz clock signal (recov-
ered from receive data) is output on RXC.
RXC is low during idle (5 bit times after re-
ceive activity stops).

7 SEL Mode Select I When SEL is high, TX+ and TX- outputs are
at the same voltage in idle state, providing a
"zero" differential. When SEL is low, TX+ is
positive with respect to TX- in idle state. Also,
three test modes may be selected by setting
the SEL pin to voltages between low and high
levels. Refer to section 2.13 for more on test
modes.

TABLE 3-1. PIN DESCRIPTION

10
PIN DESCRIPTION 83C694D

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

8 LNK TwPr Link Status O If valid data or Link Test pulses are received
on TPR+/TPR-, LNK is low (link status OK).
When no data or Link Test pulses are re-
ceived, LNK is high. The LNK pin can sink
10mA to drive an external LED.

9 TPOL TwPr Link Polarity O TPOL is low when positive polarity Link Test
pulses or data packets are received on
TPR+/TPR- (normal operation). TPOL is high
when negative polarity Link Test pulses or
data packets are received (link wiring polarity
reversed). When TPOL is low, it can sink
10mA to drive an external LED.

10 – 13 GND Negative Supply Pin 10 provides negative supply for analog

circuits. Pin 11 provides negative supply for
digital circuits. Pin 12 provides negative sup-
ply for digital/pad circuits. Pin 13 provides
negative supply for VCO circuits.

14 RLED Receive LED O When active low, RLED sinks 10 mA to drive

Driver an external LED. If no data is received, RLED
is high. If data is received, RLED will go low
for approximately 50ms longer than the re-
ceived packet length.

All LED current is controlled internally and

requires no external resistors between the
chip and an external LED.

The external LED must be connected from

+5V to the device pin. If LEDs are not used,
then the four pins can be used as logic out-
puts.

15 XLED Transmit LED O When active low, XLED sinks 10mA to drive
Driver an external LED. When there is no transmis-
sion (TXE inactive), XLED is high. When data
is transmitted, XLED goes active low for ap-
proximately 50ms longer than the transmitted
packet length. XLED does not go active low
for Link Test pulses.

TABLE 3-1. PIN DESCRIPTION cont.

11
83C694D PIN DESCRIPTION

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

16 LBK Loopback I A high level enables loopback of TXD to

RXD/RXC. A low level enables normal trans-
mit/receive operation. The LBK pin includes
an internal pull-down resistor, so it may be left
open if unused.

17 X1 Crystal/Ext. Input I X1 is driven by an external clock frequency

source or is connected to one terminal of the
20MHz crystal.

The IEEE 802.3 standard requires 0.01% ab-

solute accuracy on the transmitted signal fre-
quency. Stray capacitance can shift the
crystal’s frequency out of range, causing it to
exceed the 0.01% tolerance. To remedy this,
extra load capacitance may be added.

To determine the amount of capacitance to

add, measure the board capacitance and the
capacitance between the X1 and X2 pins.
Then add these values together, and subtract
them from the crystal’s required load capaci-
tance. (Refer to Figure 2-1.)

18 X2 Crystal Feedback O This output is connected to the other terminal

of the 20MHz crystal. If X1 is driven with an
external source, X2 must be left open.

19 TXD Transmit Data I TXD is sampled on the rising edge of TXC

when TXE is high. The NRZ data input here
is encoded and transmitted on TX+/TX- or
TPX+/TPX- as a differential signal.

20 TXC Transmit Clock O This is a 10MHz clock signal derived from the
internal 20MHz oscillator. It is enabled except
when RES is low and MPE is high.

21 TXE Transmit Enable I TXE enables encoding and transmission of

the data input via TXD. It is sampled on the
rising edge of TXC.

22 TPX2- TwPr Transmit O TPX2- is used for 10BaseT only. It is the low
current negative output pin. See TPX1+ for
details.

23 TPX1- TwPr Transmit O TPX1- is used for 10BaseT only. It is the high
current negative output pin. See TPX1+ for
details.

TABLE 3-1. PIN DESCRIPTION cont.

12
PIN DESCRIPTION 83C694D

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

24 TPX1+ TwPr Transmit O In 10BaseT operation, data input via TXD is

encoded and then transmitted on TPX pins.
When transmit and receive are idle, Link Test
pulses are periodically transmitted via TPX.

The TPX pins are connected to the twisted-

pair medium via a transformer and filter, and
use 5 external resistors for waveshaping as
shown in Figure 2-6. TPX1+ is the high cur-
rent positive output pin.

25 TPX2+ TwPr Transmit O TPX2+ is used for 10BaseT only. It is the low
current positive output pin. See TPX1+ for
details.

26 TX- AUI Transmit O In AUI mode, TX+ and TX- transmit Manches-
27 TX+ ter encoded data differentially to an external
transceiver. Each output requires an external
pull-up resistor of 150Ω 1% to +5V as shown
in Figure 2-2.

28 OSR VCO Bias Resistor I A resistor from OSR to +5V biases the internal
VCO current. Nominal value is 31.6 KΩ 1%.

29 CAP PLL Filter Cap I A capacitor (nominal value .02 µF) from CAP
to ground is used as part of the filter for the
internal phase-locked loop.

30 MODE1 Mode Select 1 I With MODE1 low, TP mode is always se-

lected. No Link Test pulses are transmitted or
required on RX+/-. When MODE1 is high, AUI
mode is selected at power on. When MODE1
is connected to RES, 10BaseT mode is se-
lected at power on. After power on, if MODE1
is not low, 10BaseT mode is automatically
selected if LNK goes low (otherwise AUI
mode is selected). The MODE1 pin includes
an internal pull-up resistor, so it can be left
open if not used.

31 MODE2 Mode Select 2 I When MODE2 is low, automatic link polarity

correction is disabled (TP mode only). Auto-
polarity correction is enabled when MODE2
is high. The MODE2 pin includes an internal
pull up resistor, so it may be left open if not
used.

TABLE 3-1. PIN DESCRIPTION cont.

13
83C694D PIN DESCRIPTION

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

32, 33, VCC Positive Supply Pin 32 is positive supply to the VCO. Pin 33
34, 35 is positive supply for digital and transmit cir-
cuits. Pin 34 is positive supply for digital cir-
cuits. Pin 35 is positive supply for receive
circuits.

36 NC Not Connected Do not connect to this pin.

37 TST Test Input I This pin must be tied low.

38 BSR Bias Resistor I A resistor from BSR to VCC sets the internal
bias levels. Nominal value is 10KΩ 1% resis-
tor connected externally to +5V. If BSR is tied
low, a low power mode is enabled and trans-
mit/receive is disabled.

39 RX- AUI Receive I In AUI mode, the Manchester encoded data

40 RX+ from an external transceiver is received on
RX+/RX-. After timing recovery and decoding,
it is output to the controller on RXD. With the
standard 78Ω transceiver AUI cable, the dif-
ferential input must be externally terminated.
This requirement can be satisfied by connect-
ing two 39.2Ω 1% resistors in series with an
optional 0.1 µF common mode bypass ca-
pacitor as shown in Figure 2-3. Matched ca-
pacitors can also be added to protect the
inputs from external faults.

41 CD- AUI Collision I In AUI mode, a 10 MHz collision presence

42 CD+ signal from an external transceiver is received
on CD+/CD-. The COL pin is then output high.
The collision differential inputs, CD+ and CD-,
must be terminated in the same manner as
the receive inputs, RX+ and RX-. See Figure
2-3 for information on this design.

TABLE 3-1. PIN DESCRIPTION cont.

14
PIN DESCRIPTION 83C694D

PIN MNEMONIC SIGNAL NAME I/O DESCRIPTION

NUMBER

43 TPR- Twisted-Pair I In 10BaseT mode, Manchester encoded data

44 TPR+ Receive is received via TPR+/TPR-. After timing re-
covery and decoding it is output to the con-
troller on RXD. TPR+/TPR- are connected to
the twisted-pair medium through a trans-
former and filter.

A 100Ω termination resistor is generally used

before the circuit connects to the receive sig-
nal lines, TPR+ and TPR- inputs. See Figure
2-5 for information on this design.

The 83C694D automatically corrects for a

misconnection of the + and - interface allow-
ing operation without having to correct the
wiring.

TABLE 3-1. PIN DESCRIPTION cont.

15
83C694D DC ELECTRICAL SPECIFICATIONS

4.0 DC ELECTRICAL SPECIFICATIONS

4.1 ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

TTL Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 – 5.5V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 – 5.5V

Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 – 16V

Differential Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 mA

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C (-85°F) to 150° (302°F)

Absolute maximum ratings indicate limits beyond which permanent damage may occur. Continuous
operation at these limits is not recommended; operation should be limited to conditions specified under DC
Operating Characteristics.

4.2 RECOMMENDED OPERATING CONDITIONS

Supply Voltage (Vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C (32°F) to 70°C (158°F)

4.3 DC OPERATING CHARACTERISTICS

Ta = 0°C (32°F) to 70°C (158°F)

Vcc = +5V ±5%

NOTE
All currents into device pins are positive. All currents out of device pins are negative. All voltages
are referenced to ground unless otherwise specified.

SYMBOL CHARACTERISTIC MIN MAX UNITS CONDITIONS

Vih Input High Voltage 2.0 – V –
(TTL and X1)1
Input High Voltage 4.5 – V –
(SEL)
Vil Input Low Voltage – 0.8 V –
(TTL, X1, SEL)
Iih Input High Current – 50 µA Vin = Vcc
(TTL, X1, SEL)
Input High Current – 500 µA
(RX± and CD± )
Iil Input Low Current – -50 µA Vin = 0.5V
(TTL, X1 and SEL)
Input Low Current – -500 µA
(RX± and CD± )
Vcl Input Clamp Voltage (TTL) – -1.2 V Iin = -12mA
Voh Output High Voltage 3.5 – V Ioh = -100µA
(RXD, RXC, CRS, TXC,
COL, X2 and LEDs)2

16
DC ELECTRICAL SPECIFICATIONS 83C694D

SYMBOL CHARACTERISTIC MIN MAX UNITS CONDITIONS

Vol Output Low Voltage – 0.5 V Iol = 8mA
(RXD, RXC, CRS, TXC, COL)
Output Low Voltage – 0.7 V
(X2)
Output Low Voltage – 0.5 V Iol = 2 mA
(LEDs)
Iol Output Low Current 10 25 mA 2V ≤ Vol ≤ 4V
(LEDs)
Ios Output Short Circuit -40 -200 mA –
Current
(RXD, RXC, CRS, TXC, COL)
Vod Differential Output Voltage ±500 ±1200 mV 78Ω termination and
(TX±) 150Ω from each output
to Vcc
Vob Differential Output Voltage – ±40 mV 78Ω termination and
Imbalance (TX±) 150Ω from each output
to Vcc
Voh Output High Voltage Vcc - 0.6 – V Ioh = -30mA
(TPX1±)
Output High Voltage Vcc - 0.75 – V Ioh = -14 mA
(TPX2±)
Vol Output Low Voltage – 0.6 V Ioh = 30 mA
(TPX1±)
Output Low Voltage 0.75 V Ioh = 14 mA
(TPX2±)
Vds Differential Squelch -175 -300 mV –
Threshold (RX±, CD±)
Differential Squelch 300 500 mV peak –
Threshold (TPR±)
Vcm Differential Input Common 0 5.25 V –
Mode Voltage (RX±, CD±)
Icc Power Supply Current – 100 mA loopback active at
10 Mbit/sec

TABLE 4-1. DC OPERATING CHARACTERISTICS

1
TTL inputs are TXE, TXD, LBK, MODE1, MODE2, and RES.
2
LED drivers are RLED, XLED, LNK, and TPOL.

17
83C694D AC OPERATING CHARACTERISTICS

5.0 AC OPERATING CHARACTERISTICS

Ta = 0°C (32°F) to 70°C (158°F)
Vcc = 5V ± 5%
NOTE
All typical values are given for Vcc = 5V and Ta = 25°C (77°F).

SYMBOL PARAMETER MIN TYP MAX UNITS

Oscillator Specification
tXTH X1 rising edge to Transmit Clock High 8 – 25 nsec
tXTL X1 rising edge to Transmit Clock Low 8 – 25 nsec
Transmit Specification
tTCD Transmit Clock Duty Cycle at 50% (10 MHz) 42 50 58 %
tTCR Transmit Clock Rise Time (20 to 80%) – – 8 nsec
tTCF Transmit Clock Fall Time (20 to 80%) – – 8 nsec
tTDS Transmit Data Setup Time to Transmit Clock Rising 20 – – nsec
Edge
tTDH Transmit Data Hold Time from Transmit Clock 0 – – nsec
Rising Edge
tTES Transmit Enable Setup Time to Transmit Clock 20 – – nsec
Rising Edge
tTEH Transmit Enable Hold Time from Transmit Clock 0 – – nsec
Rising Edge
tTOD Transmit Output Delay from Transmit Clock Rising – – 60 nsec
Edge
tTOR Transmit Output Rise Time (20% to 80%) (TX±) – – 8 nsec
Transmit Output Rise Time (TPX±) – 4.5 – nsec
tTOF Transmit Output Fall Time (80% to 20%) (TX±) – – 8 nsec
Transmit Output Fall Time (TPX±) – 4.5 – nsec
tTOJ Transmit Output Jitter (TX±) – ±0.25 – nsec
tTOH Transmit Output High before Idle in Half Step Mode 200 – – nsec
tTOI Transmit Output Idle Time in Half Step Mode – – 350 nsec
tLTPW Link Test Pulse Width 100 nsec
Receive Specification
tRCD Receive Clock Duty Cycle at 50% (10 MHz) 40 50 60 %
tRCR Receive Clock Rise Time (20% to 80%) – – 8 nsec
tRCF Receive Clock Fall Time (20% to 80%) – – 8 nsec
tRDR Receive Data Rise Time (20% to 80%) – – 8 nsec
tRDF Receive Data Fall Time (80% to 20%) – – 8 nsec
tRDS Receive Data Stable from Receive Clock ±40 – – nsec
Rising Edge
tCSON Carrier Sense Turn on Delay (AUI) – – 60 nsec
Carrier Sense Turn on Delay (TP) – – 300 nsec
tCSOFF Carrier Sense Turn off Delay (AUI) – – 160 nsec
Carrier Sense Turn off Delay (TP) – – 160 nsec

18
AC OPERATING CHARACTERISTICS 83C694D

SYMBOL PARAMETER MIN TYP MAX UNITS

tDAT Decoder Acquisition Time (AUI) – – 700 nsec
Decoder Acquisition Time (TP) – – 950 nsec
tDREJ Differential Inputs Rejection Pulse Width (AUI) 8 25 35 nsec
Differential Inputs Rejection Pulse Width (TP) 8 20 30 nsec
tRD Receive Throughput Delay – – 200 nsec
Collision Specification
tCOLON Collision Turn On Delay (AUI) – – 60 nsec
Collision Turn On Delay (TP) – – 900 nsec
tCOLOFF Collision Turn Off Delay (AUI) 100 – 160 nsec
Collision Turn Off Delay (TP) – – 160 nsec
tSQEON SQE Test Start Delay (TP) 0.6 1.0 1.6 usec
tSQED SQE Test Duration (TP) 0.5 1.0 1.5 usec
Loopback Specification
tLBS Loopback Setup Time 35 – – nsec
tLBH Loopback Hold Time 350 – – nsec
10BaseT Protocol Timers
Link Test Transmit Period 9.8 – 11.5 msec
Link Loss / Link Test Max. 78 – 92 msec
Link Test Min. 4.9 – 5.8 msec
Jabber On (transmit inhibit) 39 – 46 msec
Jabber Off (transmit re–enable) 314 – 368 msec

TABLE 5-1. AC OPERATING CHARACTERISTICS

19
83C694D AC OPERATING CHARACTERISTICS

5.1 TIMING DIAGRAMS

Figures 5–1 through 5–9 illustrate all timings. Table 5–2 lists all timing diagrams.

Figure Number Title

5–1 Transmit Timing – Start of Transmission
5–2 Transmit Timing – End of Transmission (last bit = 0)
5–3 Transmit Timing – End of Transmission (last bit = 1)
5–4 Transmit Timing – Link Test Pulse
5–5 Receive Timing – Start of Packet
5–6 Receive Timing – End of Packet (last bit = 0)
5–7 Receive Timing – End of Packet (last bit = 1)
5–8 Collision Timing (AUI)
5–9 Collision Timing (TP)
5–10 SQE Test Timing
5–11 Loopback Timing
5–12 Test Loads

TABLE 5–2. 83C694D TIMING DIAGRAMS

20
AC OPERATING CHARACTERISTICS 83C694D

TXC 1.5V

t TES

1.5V
TXE
tTDH
tTDS

1.5V 1.5V
TXD

t TOD

TX+
TX-

TPX2+

TPX1+

TPX1-

TPX2-

FIGURE 5-1. TX TIMING - START OF TRANSMISSION

FIGURE 5-2. TX TIMING - END OF TRANSMISSION (LAST BIT=0)

21
83C694D AC OPERATING CHARACTERISTICS

TXC 1.5V

t TEH

TXE 1.5V

1 1 0 1

TXD

t TOI

t TOH

TX+
TX-
1 1 1 0 1

TPX2+

TPX1+

TPX1-

TPX2-

1 1 1 0 1

FIGURE 5-3. TX TIMING - END OF TRANSMISSION (LAST BIT=1)

TXC

TPX2+

TPX1+

TPX1-

TPX2-

t LTP

FIGURE 5-4. TX TIMING - LINK TEST PULSE

22
AC OPERATING CHARACTERISTICS 83C694D

FIRST BIT DECODED

RX+/RX- 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

or
TPRX+/TPRX- t DREJ

CRS 1.5V

t CSON
1.5V
RXC

t DAT t RDS
t RDS

RXD
1.5V
1 0 1 0 1 0 1 0 1 0 1

FIGURE 5-5. RECEIVE TIMING - START OF PACKET

1 0 1 0 0
RX+/RX-

or
TPRX+/TPRX- t CSOFF

CRS 1.5V

t RD

RXC

5 EXTRA CLOCKS

RXD

1 0 1 0 0

FIGURE 5-6. RECEIVE TIMING - END OF PACKET (LAST BIT = 0)

23
83C694D AC OPERATING CHARACTERISTICS

1 0 1 0 1

RX+
RX-
t CSOFF

CRS

RXC

5 EXTRA CLOCKS

RXD

1 0 1 0 1

FIGURE 5-7. RECEIVE TIMING - END OF PACKET (LAST BIT = 1)

CD+
CD-
t COLOFF
t COLON

COL 1.5V 1.5V

FIGURE 5-8. COLLISION TIMING (AUI)

24
AC OPERATING CHARACTERISTICS 83C694D

TXE

TPRX+
TPRX-

t COLON t COLOFF

COL

FIGURE 5-9. COLLISION TIMING (TP)

TXE

t t SQED
SQEON

COL

FIGURE 5-10. SQE TEST TIMING

25
83C694D AC OPERATING CHARACTERISTICS

1.5V 1.5V
LBK
t LBS t LBH

1.5V 1.5V
TXE

FIGURE 5-11. LOOPBACK TIMING

+ 5V

150 Ohm

TTL/MOS OUTPUTS TX+

+ 5V
50 pF 27 µ H**
150 Ohm R*
+
_ 1%

TX-

* R = 73 Ohm + 1% and
R = 83 Ohm + 1%

** 27 µ H + 1% inductor is used for test purposes. 100 µH tranformers (Valor LT 1101, or Pulse
Engineering 64103) are recommended for application use.

TPX2+ 237 Ohm

59 Ohm
TPX1+

59 Ohm
TPX1-

TPX2- 237 Ohm

FIGURE 5-12. TEST LOADS

26
PACKAGE DESCRIPTION 83C694D

6.0 PACKAGE DESCRIPTION

Figure 6-1 illustrates the 44-pin PLCC package for the 83C694D. Refer to Table 6-1 for the dimensions
given in this figure.

FIGURE 6-1. 44-PIN PLCC PACKAGE DIAGRAM

27
83C694D PACKAGE DESCRIPTION

Table 6-1 provides acceptable ranges for the codes shown in Figure 6-1. All dimensions are in inches.

Code Dimension Ranges

A .160 – .188
A1 .090 – .120
B .013 – .021
B1 .026 – .032.
B2 .025 min
C .020 – .045
D/E .685 – .695
D1/E1 .650 – .656
D2/E2 .600 – .630
D3/E3 .500 REF
e .050 BSC
F .042 – .060
G .042 – .048
J .000 – .028
R .025 – .045

TABLE 6-1. PLCC PACKAGE DIMENSIONS

Notes:

1. Coplanarity is .004" maximum

2. Tolerance on the position of the leads is .007"maximum
3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion
is .010"

28
Index 83C694D

Index

! F P

83B692 Ethernet transceiver, 4 Features, 1 Phase-locked loop, 5, 7

83C690 Ethernet LAN controller, 4 PLCC/PQFP package, 9
83C694D G PLL filter cap, 13
functional blocks, 4 Positive supply, 14
General description, 1
as twisted-pair interface, 4 Prevention of voltage fluctuation, 5
GND, 11
pin package, 27 Pulse widths transmitted, 6
I
A R
Indicator LEDs, 8
Absolute maximum ratings, 16 Receive clock, 10
Internal counter speedup, 8
AC operating characteristics, 18 - Receive data, 10
Introduction, 1
20 Receive LED driver, 11
Architecture, 4 - 8 J RES, 10
AUI collision, 14 Reset/Synch, 10
AUI differential line driver, 5 Jabber, 8 RLED, 11
design notes, 5 RX-/RX+, 14
AUI receive, 14 L RXC, 10
AUI transmit, 13 LBK, 12 RXC & RXD enable, 8
AUI/TP autoselect, 8 RXD, 10
LED test functions, 8
Autoselect, 8 Link test function, 8 S
B LNK, 11
Loopback, 12 SEL, 10
Bias resistor, 14 Loopback function, 7 Smart squelch, 1, 7
BSR, 14 SQE test functions, 8
M Status indications, 8
C
Main functions, 1 T
CAP, 13 Manchester decoder, 5
Carrier sense, 10 Manchester encoder, 5 Test modes, 8
Carrier Sense (CRS), 5 Manchester encoding, 4 Timing diagrams, 20
CD-/CD+, 14 Mode select, 10 TP differential driver, 6
COL, 10 Mode select 1, 13 design notes, 6
Collision detect, 10 Mode select 2, 13 TP differential receiver, 7
Collision translator, 6 MODE1, 13 TPOL, 11
CRS, 10 MODE2, 13 TPR-/TPR+, 15
Crystal accuracy, 12 TPX1+, 13
Crystal feedback, 12 N TPX1-, 12
Crystal/ext. input, 12 TPX2+, 13
Negative supply, 11
NRZ data conversion, 4 TPX2-, 12
D Transmit clock, 12
O Transmit data, 12
DC electrical specifications, 16 - 17
Transmit enable, 12
recommended operating Oscillator, 4 Transmit LED driver, 11
conditions, 16 OSR, 13 TST, 14
DC operating characteristics, 16 Output tristate, 8 Twisted-pair interface, 4
Decoding, 5
Twisted-pair link polarity, 11
Differential driver, 5
Twisted-pair link status, 11

29
83C694D Index

Twisted-pair receive, 15
Twisted-pair transmit, 12 - 13
TX-/TX+, 13
TXC, 12
TXD, 12
TXE, 12
Typical TPX pin values, 6

UTP, 6

VCC, 14
VCO bias resistor, 13

X1, 12
X2O, 12
XLED, 11

Zener diode
5-volt supply, 5

30