9 kHz to 7 GHz, Bidirectional

RMS and VSWR Detector

Data Sheet ADL5920
FEATURES FUNCTIONAL BLOCK DIAGRAM

GND6

GND5

GND4

GND3

GND2

GND1
Wideband matched 9 kHz to 7 GHz operation
Forward and reverse power and return loss measurement 30 29 28 27 24 1
49 dB ±1.0 dB input range with −19 dBm minimum input level,
ADL5920
±1.0 dB at 1 GHz 31 26
RFOUT
RFIN
Linear in dB rms (crest factor insensitive) outputs 32 BIDIRECTIONAL BRIDGE 25

Insertion loss: 1.1 dB at 1 GHz and 1.9 dB at 6 GHz

VNEG1 2 23 VNEG2
Input and output return loss and VSWR
1 GHz: 22 dB/1.16:1 CHPR+ 3 21 CHPF+

3 GHz: 14 dB/1.5:1 CHPR– 4 REVERSE FORWARD 22 CHPF–

PATH PATH
6 GHz: 12 dB/1.7:1 CRMSR 9 RMS RMS 16 CRMSF
DETECTOR DETECTOR
Output IP3: 70.5 dBm at 1 GHz
Directivity
VRMSR 7 18 VRMSF
20 dB at 1 GHz
13 dB at 3 GHz 12 DECL

5 dB at 6 GHz 10 VOCM

Maximum input power VREF 19 VREF

VTEMP 6 TEMPERATURE 2.5V
SENSOR
30 dBm for open or shorted termination 15 VTGT
33 dBm for matched termination 20 TADJI

APPLICATIONS 5
PWDN/
TADJS
8 13 11 14 17
Industrial metering

VDIFF–

VDIFF+
VPOS1

VPOS2

VPOS3

16085-001
Broadband inline power and return loss measurement
Transmit power control and automatic level control in
Figure 1.
wireless transmitters, signal generators, network
analyzers, and wireless communications testers
Condition based monitoring of system modules, cables, and
connectors

GENERAL DESCRIPTION
The ADL5920 is an ultrawideband, bidirectional detector that (relative to the dc voltage at RFIN and RFOUT). The internal
simultaneously measures forward and reverse rms power levels detector circuitry is also dc-coupled to the bidirectional bridge
in a signal path, along with the return loss. to support measurements down to 9 kHz.
The forward and reverse power traveling through the The maximum input signal on each of the RF ports (RFIN and
integrated bidirectional bridge is measured using two 50 dB RFOOUT) is 30 dBm for open and shorted terminations and
linear in dB rms detectors. The detector output voltages, 33 dBm for a matched termination.
available at the VRMSF and VRMSR pins, are proportional to The ADL5920 draws 160 mA from a 5 V supply and has a low
the forward and reflected power in dBm. A third, differential, power, power-down mode controlled through the
output produces a voltage proportional to the return loss PWDN/TADJS pin.
(reflection coefficient) in dB, closely related to the voltage
standing wave ratio (VSWR). The common-mode level of this The device is supplied in a 32-lead, 5 mm × 5 mm LFCSP and is
output is externally adjustable through the VOCM pin. specified for ambient operating temperatures in the −40°C to
+85°C range.
The primary transmission line of the bidirectional bridge, from
RFIN to RFOUT (or vice versa) is dc-coupled and allows small Multifunction pin names may be referenced by their relevant
amounts of dc bias current through the bridge. When dc-coupled function only.
to source and load, the positive and negative supply pins of the
ADL5920 must be connected to +5 V and −2.5 V, respectively
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADL5920 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Basic Connections ...................................................................... 18
Applications ....................................................................................... 1 CHPR, CHPF Capacitors .......................................................... 18
Functional Block Diagram .............................................................. 1 VREF Interface ........................................................................... 19
General Description ......................................................................... 1 VDIFF Output Interface ............................................................ 19
Revision History ............................................................................... 2 Temperature Drift Compensation ........................................... 19
Specifications..................................................................................... 3 Setting VTGT.............................................................................. 19
Absolute Maximum Ratings ............................................................ 8 Choosing Values for CRMSF and CRMSR ............................. 20
Thermal Resistance ...................................................................... 8 RF Power and Return Loss Calculation .................................. 21
ESD Caution .................................................................................. 8 DC-Coupled Operation............................................................. 22
Pin Configuration and Function Descriptions ............................. 9 Evaluation Board ............................................................................ 23
Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 26
Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 26
Applications Information .............................................................. 18
REVISION HISTORY
12/2019—Rev. A to Rev. B 3/2019—Rev. 0 to Rev. A
Changes to Applications Section and Figure 1 ............................. 1 Changes to Ordering Guide .......................................................... 26
Changes to Figure 38 ...................................................................... 18
Changes to RF Power and Return Loss Calculation Section .... 21 1/2019—Revision 0: Initial Version
Changes to Figure 43 ...................................................................... 22

Rev. B | Page 2 of 26
Data Sheet ADL5920

SPECIFICATIONS
VPOS1, VPOS2, VPOS3 = 5 V, VNEG = 0 V, TA = 25°C, output impedance (ZO) = 50 Ω, unless otherwise noted (see Figure 38).

Table 1.
Parameter 1 Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 0.009 7000 MHz
Input and Output Impedance RFIN, RFOUT require 50 Ω terminations 50 Ω
Maximum Input Power (PIN) Open or short termination 30 dBm
Matched termination 33 dBm
10 MHz VRMSF, VRMSR, TADJI voltage (VTADJI) = 0 V, TADJS voltage
(VTADJS) = 0 V
Insertion Loss 0.9 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 43 dB
VSWR (RFIN, RFOUT) 1.02:1
Directivity 0.1 µF capacitors on CHPR+/CHPR− and CHPF+/CHPF− 43 dB
±1.0 dB Input Range VRMSF, VRMSR, continuous wave (CW) input 50 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 30 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −20 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = −10 dBm −0.46 dB
−40°C, PIN = 20 dBm −0.4 dB
85°C, PIN = −10 dBm −0.02 dB
85°C, PIN = 20 dBm 0.18 dB
70°C, PIN = −10 dBm −0.03 dB
70°C, PIN = 20 dBm 0.2 dB
Logarithmic Slope VRMSF, VRMSR 61 mV/dB
Logarithmic Intercept VRMSF, VRMSR −29.7 dBm
100 MHz VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0 V
Insertion Loss 0.9 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 37 dB
VSWR (RFIN, RFOUT) 1.03:1
Directivity 0.1 µF capacitors on CHPR+/CHPR− and CHPF+/CHPF− 43 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 49 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 30 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −19 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = −10 dBm −0.43 dB
−40°C, PIN = 20 dBm −0.46 dB
85°C, PIN = −10 dBm 0.04 dB
85°C, PIN = 20 dBm 0.26 dB
70°C, PIN = −10 dBm 0.04 dB
70°C, PIN = 20 dBm 0.28 dB
Logarithmic Slope VRMSF, VRMSR 61 mV/dB
Logarithmic Intercept VRMSF, VRMSR −29.8 dBm

Rev. B | Page 3 of 26
ADL5920 Data Sheet
Parameter 1 Test Conditions/Comments Min Typ Max Unit
1 GHz VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0 V
Insertion Loss 1.1 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 22 dB
VSWR (RFIN, RFOUT) 1.16:1
Directivity 0.1 µF capacitors on CHPR+/CHPR− and CHPF+/CHPF− 20 dB
Output Third-Order Intercept (IP3) 27 dBm per tone at RFIN, RFOUT terminated with 50 Ω, 70.5 dBm
1 MHz tone spacing
±1.0 dB Input Range VRMSF, VRMSR, CW input 49 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 30 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −19 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = −10 dBm −0.41 dB
−40°C, PIN = 20 dBm −0.32 dB
85°C, PIN = −10 dBm −0.5 dB
85°C, PIN = 20 dBm −0.11 dB
70°C, PIN = −10 dBm −0.24 dB
70°C, PIN = 20 dBm 0.15 dB
Logarithmic Slope VRMSF, VRMSR 61 mV/dB
Logarithmic Intercept VRMSF, VRMSR −27 dBm
2 GHz VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V
Insertion Loss 1.3 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 17 dB
VSWR (RFIN, RFOUT) 1.30:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 16 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 45 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 28 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −17 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = −10 dBm −0.44 dB
−40°C, PIN = 20 dBm −0.73 dB
85°C, PIN = −10 dBm −0.98 dB
85°C, PIN = 20 dBm −0.58 dB
70°C, PIN = −10 dBm −0.36 dB
70°C, PIN = 20 dBm 0.04 dB
Logarithmic Slope VRMSF, VRMSR 60.6 mV/dB
Logarithmic Intercept VRMSF, VRMSR −26 dBm
3 GHz VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V
Insertion Loss 1.5 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 14 dB
VSWR (RFIN, RFOUT) 1.5:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 13 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 43 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 26 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −17 dBm

Rev. B | Page 4 of 26
Data Sheet ADL5920
Parameter 1 Test Conditions/Comments Min Typ Max Unit
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = −10 dBm −0.38 dB
−40°C, PIN = 20 dBm −0.71 dB
85°C, PIN = −10 dBm −1.83 dB
85°C, PIN = 20 dBm −1.48 dB
70°C, PIN = −10 dBm −0.85 dB
70°C, PIN = 20 dBm −0.37 dB
Logarithmic Slope VRMSF, VRMSR 59.4 mV/dB
Logarithmic Intercept VRMSF, VRMSR −25.5 dBm
4 GHz VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V
Insertion Loss 1.7 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 12.5 dB
VSWR (RFIN, RFOUT) 1.7:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 7 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 41 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 25 dBm
from +30 dBm to −15 dBm
Minimum Input Level, ±1.0 dB −16 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = 0 dBm −0.07 dB
−40°C, PIN = 20 dBm −0.53 dB
85°C, PIN = 0 dBm −1.95 dB
85°C, PIN = 20 dBm −2.9 dB
70°C, PIN = 0 dBm −0.81 dB
70°C, PIN = 20 dBm −1.0 dB
Logarithmic Slope VRMSF, VRMSR 59 mV/dB
Logarithmic Intercept VRMSF, VRMSR −24.6 dBm
5 GHz VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0.2 V
Insertion Loss 1.7 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 11 dB
VSWR (RFIN, RFOUT) 1.9:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 6 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 37 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 24 dBm
from +15 dBm to −10 dBm
Minimum Input Level, ±1.0 dB −13 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = 0 dBm −0.86 dB
−40°C, PIN = 20 dBm −1.46 dB
85°C, PIN = 0 dBm −1.9 dB
85°C, PIN = 20 dBm −2.94 dB
70°C, PIN = 0 dBm −0.5 dB
70°C, PIN = 20 dBm −1.09 dB
Logarithmic Slope VRMSF, VRMSR 59.2 mV/dB
Logarithmic Intercept VRMSF, VRMSR −22.3 dBm

Rev. B | Page 5 of 26
ADL5920 Data Sheet
Parameter 1 Test Conditions/Comments Min Typ Max Unit
6 GHz VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0 V
Insertion Loss 1.9 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 12 dB
VSWR (RFIN, RFOUT) 1.7:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 5 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 33 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 22 dBm
from +20 dBm to −5 dBm
Minimum Input Level, ±1.0 dB −11 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = 0 dBm −0.74 dB
−40°C, PIN = 20 dBm −1.45 dB
85°C, PIN = 0 dBm −3.36 dB
85°C, PIN = 20 dBm −3.57 dB
70°C, PIN = 0 dBm −1.14 dB
70°C, PIN = 20 dBm −1.72 dB
Logarithmic Slope VRMSF, VRMSR 57.7 mV/dB
Logarithmic Intercept VRMSF, VRMSR −19.7 dBm
7 GHz VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0.8 V
Insertion Loss 2 dB
Return Loss (RFIN, RFOUT) 50 Ω load on RFOUT 14 dB
VSWR (RFIN, RFOUT) 1.5:1
Directivity No capacitors on CHPR+/CHPR− and CHPF+/CHPF− 7 dB
±1.0 dB Input Range VRMSF, VRMSR, CW input 31 dB
Maximum Input Level, ±1.0 dB Slope and intercept calculated using linear regression 21 dBm
from 20 dBm to 0 dBm
Minimum Input Level, ±1.0 dB −10 dBm
Deviation vs. Temperature Deviation from output at TA = 25°C
−40°C, PIN = 0 dBm −1.39 dB
−40°C, PIN = 20 dBm −2.75 dB
85°C, PIN = 0 dBm −3.77 dB
85°C, PIN = 20 dBm −3.11 dB
70°C, PIN = 0 dBm −1.55 dB
70°C, PIN = 20 dBm −1.15 dB
Logarithmic Slope VRMSF, VRMSR 57.4 mV/dB
Logarithmic Intercept VRMSF, VRMSR −17.7 dBm
OUTPUT INTERFACE VRMSF, VRMSR
Short-Circuit Current
Sourcing VRMSF and VRMSR = 3.5 V 73 mA
Sinking VRMSR and VRMSR = 100 mV, no RF Input 71 mA
Small Signal Output Impedance 0.4 Ω
Rise Time PIN = off to −10 dBm, 10% to 90%, 10 nF on CRMSF and 18 µs
CRMSR
Fall Time PIN = −10 dBm to off, 10% to 90%, 10 nF on CRMSF and 75 µs
CRMSR
OUTPUT INTERFACE VDIFF+, VDIFF−
Common-Mode Output Voltage VOCM 2.5 V
Small Signal Output Impedance 0.4 Ω
Current Capability
Source 69 mA
Sink 69 mA

Rev. B | Page 6 of 26
Data Sheet ADL5920
Parameter 1 Test Conditions/Comments Min Typ Max Unit
TEMPERATURE COMPENSATION TADJI
Input Voltage Range 0 1 V
Input Bias Current VTADJI = 1 V 14 µA
Input Resistance 70 kΩ
VOLTAGE REFERENCE VREF
Output Voltage TA = 25°C, load resistance (RL) = 10 kΩ 2.5 V
Small Signal Output Impedance 3.1 Ω
Current Capability
Source 9.8 mA
Sink 4.6 mA
TEMPERATURE REFERENCE VTEMP
Output Voltage TA = 25°C, RL ≥ 10 kΩ 1.38 V
Temperature Coefficient −40°C ≤ TA ≤ +85°C, RL ≥ 10 kΩ 4.5 mV/°C
POWER-DOWN INTERFACE AND Pin PWDN/TADJS
TEMPERATURE COMPENSATION
Voltage Level
To Enable 1.2 V
To Disable 1.5 V
Enable Time PIN = 10 dBm, PWDN/TADJS at 50% to output voltage at 10 µs
90%, 10 nF on CRMSF and CRMSR
Disable Time PIN = 10 dBm, PWDN/TADJS at 50% to output voltage at 5 µs
10%, 10 nF on CRMSF and CRMSR
Input Bias Current VTADJS = 2.5 V 36 µA
Input Resistance 70 kΩ
POWER SUPPLY VPOS1, VPOS2, VPOS3
Supply Voltage 4.9 5 5.1 V
Quiescent Current PWDN/TADJS low 130 160 200 mA
PWDN/TADJS high 1 3 mA
1
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

Rev. B | Page 7 of 26
ADL5920 Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 2.
Parameter Rating Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
Supply Voltage (VPOS1, VPOS2, and VPOS3) 5.5 V
PCB thermal design is required.
Negative Supply Voltage (VNEG1 and VNEG2) −3 V
Input Average Radio Frequency (RF) Power1 θJA is junction to ambient thermal impedance, and θJC is
50 Ω Load 33 dBm junction to case (exposed pad) thermal impedance.
Open or Shorted Load 30 dBm
Table 3. Thermal Resistance
Equivalent Voltage, Sine Wave Input 28.25 V p-p
PWDN/TADJS, TADJI, VOCM 0 V, VPOSx Package Type1 θJA θJC Unit
VTGT 4V CP-32-7 44.05 1.08 °C/W
Maximum Junction Temperature 150°C 1
No airflow with the exposed pad soldered to a 4-layer JEDEC board.
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C ESD CAUTION
1
Guaranteed by design based on extended duration bench testing at 85°C
case temperature
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. B | Page 8 of 26
Data Sheet ADL5920

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RFOUT
RFOUT
GND6
GND5
GND4
GND3
RFIN
RFIN
32
31
30
29
28
27
26
25
GND1 1 24 GND2
VNEG1 2 23 VNEG2
CHPR+ 3 22 CHPF–
CHPR– 4 ADL5920 21 CHPF+
5 TOP VIEW 20
PWDN/TADJS TADJI
(Not to Scale)
VTEMP 6 19 VREF
VRMSR 7 18 VRMSF
VPOS1 8 17 VPOS3

9
10
11
12
13
14
15
16
VDIFF+
DECL

VTGT
VDIFF–

VPOS2
VOCM

CRMSF
CRMSR

16085-002
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE
WITH LOW THERMAL AND ELECTRICAL IMPEDANCE.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1, 24, 27 to 30 GND1, GND2, GND3, RF Ground. Connect all ground pins to a low impedance ground plane.
GND4, GND5, GND6
2, 23 VNEG1, VNEG2 Negative Supply Pins. For normal single-supply operation, connect these pins to ground.
In applications where the RF input and output are dc-coupled, apply a −2.5 V supply
voltage to these pins along with a +5 V power supply on VPOS1, VPOS2, and VPOS3.
In this dc-coupled operating mode, Pin 12 (DECL) must be connected to ground.
8, 13, 17 VPOS1, VPOS2, VPOS3 Power Supply. Separately decouple each power supply pin using 100 pF and 0.1 µF
capacitors. The nominal supply voltage on these pins is 5 V.
3, 4, 21, 22 CHPR+, CHPR−, CHPF+, CHPF− Offset Compensation Loop Control. The capacitances on these pin pairs set the high-
pass corner frequency of the internal offset compensation loops, which in turn sets the
minimum operating frequency of the rms detectors in the forward and reverse paths.
For normal operation, add a capacitor from each pin to ground along with a capacitor
across the pins. To operate at input frequencies down to 9 kHz, capacitances in the 1 µF
range are required. To maintain the specified directivity, leave these pins open when
operating at frequencies above 2 GHz.
5 PWDN/TADJS Temperature Compensation and Shutdown. This pin is a dual function pin that controls
temperature slope compensation at voltages <1.0 V and/or shuts down the device at
voltages >1.4 V. The temperature compensation voltage is set by connecting this pin to
VREF through a resistor divider.
6 VTEMP Temperature Sensor Output of 1.38 V at TA = 25°C with a Coefficient of 4.5 mV/°C.
7, 18 VRMSR, VRMSF Reverse and Forward RMS Voltage Measurement. The voltages on these pins are
proportional to the decibel power of the incident signal to the RFOUT and RFIN pins.
9, 16 CRMSR, CRMSF RMS Averaging Capacitor for Reverse and Forward Path Detectors. Connect rms
averaging capacitors between CRMSR and ground and between CRMSF and ground to
set the averaging time constant of the forward and reverse rms detectors. For normal
operation, the values of these two capacitors must be equal.
10 VOCM Common-Mode Input Voltage for VDIFF+ and VDIFF−. The input voltage applied to
VOCM sets the common-mode voltage for the VDIFF+ and VDIFF− differential pair.
The nominal voltage on this pin is 2.5 V. However, this value can be reduced to as low as
1.5 V to accommodate the common-mode requirements of the ADC, which is driven by
VDIFF+ and VDIFF−. The VOCM input requires a bias current of ±1 mA and must be
driven from a low impedance source. VOCM can be driven from the VREF pin but the
connection must include a 1 kΩ resistor to ground.
11, 14 VDIFF−, VDIFF+ Return Loss and VSWR Output. The differential voltage on these pins is proportional to
the dB return loss of the load connected to the RFOUT port when the device is driven
through the RFIN port. This differential voltage has a bias level equal to the voltage
applied to VOCM, nominally 2.5 V.

Rev. B | Page 9 of 26
ADL5920 Data Sheet
Pin No. Mnemonic Description
12 DECL Internal Decoupling Node. Decouple this pin with a 0.1 µF capacitor to ground. Do not
use the voltage on this pin, nominally 3.2 V, externally to set any bias levels. In dc-coupled
applications where VNEGx is connected to −2.5 V, this pin must be connected directly to
ground.
15 VTGT RMS Target Voltage. The voltage applied to this pin sets the target RF level at the output
of the internal voltage controlled amplifiers that drive the internal squaring cells of the rms
detectors. The recommended voltage for VTGT is 1 V. Increasing VTGT above 1 V degrades
the rms accuracy of the ADL5920. Reducing VTGT below 1 V can improve the rms
accuracy for signals with high crest factors. The voltage on this pin can be derived from
a resistor divider circuit that is driven by the VREF pin (Pin 19).
19 VREF Reference Voltage Output. This voltage reference has a nominal value of 2.5 V. This
reference output voltage can set the voltage to the TADJI, TADJS, VTGT, and VOCM pins.
20 TADJI RMS Detector Temperature Compensation. Use this pin to fine tune the temperature
intercept stability of the rms detectors. The voltage applied to this pin can be derived
from VREF using a simple resistor divider.
25, 26, 31, 32 RFOUT, RFIN RF Inputs and Outputs. The two RFIN pins are common inputs that must always be
connected to each other. Likewise, the two RFOUT pins must always be connected to
each other. The power of the incident signal on RFIN is measured on the VRMSF pin, and
the power on the incident signal into RFOUT is measured on the VRMSR pin. The ratio of
the incident signals on RFIN and RFOUT is measured on the VDIFF+ and VDIFF− pins.
The RFIN and RFOUT pins are interchangeable, allowing the source signal to drive into
RFOUT with the load connected to RFIN. RFIN and RFOUT are normally ac-coupled to
the source and load. RFIN and RFOUT can be dc-coupled by connecting a −2.5 V supply
to the two VNEGx pins and by connecting the DECL pin to ground.
EPAD Exposed Pad. Connect the exposed pad to a ground plane with low thermal and
electrical impedance.

Rev. B | Page 10 of 26
Data Sheet ADL5920

TYPICAL PERFORMANCE CHARACTERISTICS

2 2
RFIN TO RFOUT
1 1
RFOUT TO RFIN
0 0
INSERTION LOSS (dB)

INSERTION LOSS (dB)

–1 –1

–2 –2

–3 –3

–4 –4
+85°C
–5 –5 +70°C
+25°C
–6 –6 0°C
–40°C
–7 –7

–8 –8

16085-003

16085-006
100k 1M 10M 100M 1G 10G 10M 100M 1G 10G
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 3. Forward and Reverse Insertion Loss vs. Frequency Figure 6. Forward Insertion Loss vs. Frequency at Various Temperatures

20 2.5
10MHz (CHPF,CHPR = 100nF)
10 100MHz (CHPF,CHPR = 100nF)
1GHz (CHPF,CHPR = 100nF)
0 2.0 2GHz (CHPF,CHPR = OPEN)
4GHz (CHPF,CHPR = OPEN)
VDIFF (VDIFF+ – VDIFF –) (V)
–10 6GHz (CHPF,CHPR = OPEN)
RETURN LOSS (dB)

–20 1.5

–30

–40 1.0

–50

–60 INPUT RETURN LOSS (RFIN) 0.5

OUTPUT RETURN LOSS (RFOUT)
–70

–80 0
16085-004

16085-007
0.1 1 10 100 1k 10k 0 5 10 15 20 25 30
FREQUENCY (MHz) APPLIED RETURN LOSS ON RFOUT (dB)

Figure 4. Return Loss vs. Frequency Figure 7. VDIFF (VDIFF+ − VDIFF−) vs. Applied Return Loss on RFOUT, Bridge Driven
from RFIN at 15 dBm and Variable Return Loss at RFOUT
50 4.0 2
VRMSF LTE (9MHz BW, PEP =10.39dB)
CHPF, CHPR = 100nF VRMSF QPSK (5MSPS, PEP = 3.8dB)
45 VRMSF 16 QAM (5MSPS, PEP = 6.3dB)
CHPF, CHPR = OPEN 3.5
VRMSF 64 QAM (5MSPS, PEP = 7.4dB)
40 V RMS CW PEP = 0dB
3.0 1
35
DIRECTIVITY (dB)

2.5
30 ERROR (dB)
VRMSF (V)

25 2.0 0

20
1.5
ERROR CW
15 ERROR LTE
1.0 ERROR QPSK –1
10 ERROR 16 QAM
ERROR 64 QAM
0.5
5

0 0 –2
16085-009
16085-007

10M 100M 1G 10G –40 –30 –20 –10 0 10 20 30 40

FREQUENCY (MHz) PIN (dBm)

Figure 5. Directivity vs. Frequency with Bridge Driven from RFIN at 20 dBm Figure 8. VRMSF Error from CW Linear Reference vs. Signal Modulation,
and RFOUT Terminated with 50 Ω Frequency = 1 GHz, CRMSF = 0.1 μF, Error Calculated Using Linear
Regression of Data From −15 dBm to +30 dBm (BW Stands for Bandwidth
and PEP Stands for Peak Envelope Power)

Rev. B | Page 11 of 26
ADL5920 Data Sheet
4.0 4.0 4
7GHz
3.5 6GHz 3.5 3
5GHz
1GHz
3.0 100MHz 3.0 2
10MHz
4GHz
2.5 2.5 1
VRMMSF (V)

ERROR (dB)
3GHz

VRMSF (V)
2GHz
2.0 2.0 0

+85°C VRMSF
1.5 1.5 –1
+70°C VRMSF
+25°C VRMSF
1.0 1.0 –40°C VRMSF –2
+85°C ERROR
+70°C ERROR
0.5 0.5 +25°C ERROR –3
–40°C ERROR
0 0 –4

16085-013
16085-010
–30 –20 –10 0 10 20 30 –40 –30 –20 –10 0 10 20 30
PIN (dBm) RF INPUT (dBm)

Figure 9. VRMSF Output Voltage vs. PIN at Various Frequencies, Forward Drive Figure 12. VRMSF Output Voltage and Error vs. RF Input and Temperature at
10 MHz, Error Calculated Using Linear Regression of Data Between +30 dBm
and −15 dBm, TADJS = 0 V, TADJI = 0 V, 0.1 µF Across CHPF+, CHPF−

4.0 4.0 4
+30dBm
3.5 +25dBm 3.5 3

+20dBm
3.0 3.0 2
+15dBm
+10dBm 2.5 1
2.5

ERROR (dB)
VRMSF (V)
VRMSF (V)

+5dBm
2.0 2.0 0
0dBm
–5dBm +85°C VRMSF
1.5 1.5 –1
+70°C VRMSF
–10dBm +25°C VRMSF
1.0 –15dBm 1.0 –40°C VRMSF –2
+85°C ERROR
–20dBm +70°C ERROR
0.5 –25dBm 0.5 +25°C ERROR –3
–30dBm –40°C ERROR
0 0 –4

16085-014
16085-011

0.01 0.1 1 10 –40 –30 –20 –10 0 10 20 30

FREQUENCY (GHz) RF INPUT (dBm)

Figure 10. VRMSF vs. Frequency at Various Input Power Levels, Forward Drive Figure 13. VRMSF and Error vs. RF Input and Temperature at 100 MHz, Error
Calculated Using Linear Regression of Data Between +30 dBm and −15 dBm,
TADJS = 0 V, TADJI = 0 V, 0.1 µF Across CHPF+, CHPF−

4.0 4.0 4
+30dBm
3.5 +25dBm 3.5 3

+20dBm
3.0 3.0 2
+15dBm
2.5 +10dBm 2.5 1
ERROR (dB)
VRMSF (V)
VRMSR (V)

+5dBm
2.0 2.0 0
0dBm
–5dBm +85°C VRMSF
1.5 1.5 –1
+70°C VRMSF
–10dBm +25°C VRMSF
1.0 –15dBm 1.0 –40°C VRMSF –2
+85°C ERROR
–20dBm
+70°C ERROR
0.5 –25dBm 0.5 +25°C ERROR –3
–30dBm –40°C ERROR
0 0 –4
16085-015
16085-012

0.01 0.1 1 10 –40 –30 –20 –10 0 10 20 30

FREQUENCY (GHz) RF INPUT (dBm)

Figure 11. VRMSR vs. Frequency at Various Input Power Levels, Reverse Drive Figure 14. VRMSF and Error vs. RF Input and Temperature at 1 GHz, Error
Calculated Using Linear Regression of Data Between +30 dBm and −15 dBm,
TADJS = 0 V, TADJI = 0 V, 0.1 µF Across CHPF+, CHPF−

Rev. B | Page 12 of 26
Data Sheet ADL5920
4.0 4 4.0 4
+85°C VRMSF
+70°C VRMSF
3.5 3 3.5 +25°C VRMSF 3
–40°C VRMSF
3.0 2 3.0 +85°C ERROR 2
+70°C ERROR
+25°C ERROR
2.5 1 2.5 –40°C ERROR 1

ERROR (dB)

ERROR (dB)
VRMSF (V)

VRMSF (V)
+85°C VRMSF
2.0 0 2.0 0
+70°C VRMSF
+25°C VRMSF
1.5 –40°C VRMSF –1 1.5 –1
+85°C ERROR
+70°C ERROR
1.0 +25°C ERROR –2 1.0 –2
–40°C ERROR
0.5 –3 0.5 –3

0 –4 0 –4

16085-016

16085-019
–40 –30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30
RF INPUT (dBm) RF INPUT (dBm)

Figure 15. VRMSF and Error vs. RF Input and Temperature at 2 GHz, Error Figure 18. VRMSF and Error vs. RF Input Level and Temperature at 5 GHz,
Calculated Using Linear Regression of Data Between +25 dBm and −15 dBm, Error Calculated Using Linear Regression of Data Between 15 dBm and
TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF− Open −10 dBm, TADJS = 0.2 V, TADJI = 0.2 V, CHPF+/CHPF− Open
4.0 4 3.00 6
+85°C VRMSF
2.75 +70°C VRMSF 5
3.5 3 +25°C VRMSF
2.50 –40°C VRMSF 4
+85°C ERROR
3.0 2 2.25 +70°C ERROR 3
2.00 +25°C ERROR 2
2.5 1 –40°C ERROR
ERROR (dB)

ERROR (dB)
VRMSF (V)

VRMSF (V)
1.75 1
+85°C VRMSF
2.0 +70°C VRMSF 0 1.50 0
+25°C VRMSF 1.25 –1
1.5 –40°C VRMSF –1
+85°C ERROR 1.00 –2
+70°C ERROR
1.0 +25°C ERROR –2 0.75 –3
–40°C ERROR
0.50 –4
0.5 –3
0.25 –5
0 –4 0 –6
16085-017

16085-020
–40 –30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30
RF INPUT (dBm) RF INPUT (dBm)

Figure 16. VRMSF and Error vs. RF Input and Temperature at 3 GHz, Error Figure 19. VRMSF and Error vs. RF Input Level and Temperature at 6 GHz,
Calculated Using Linear Regression of Data Between +25 dBm and −15 dBm, Error Calculated Using Linear Regression of Data Between 20 dBm and
TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF− Open −5 dBm, TADJS = 0 V, TADJI = 0.2 V, CHPF+/CHPF− Open
4.0 4 3.00 6
+85°C VRMSF +85°C VRMSF
+70°C VRMSF 2.75 +70°C VRMSF 5
3.5 +25°C VRMSF 3 +25°C VRMSF
2.50 –40°C VRMSF 4
–40°C VRMSF
3.0 +85°C ERROR 2 +85°C ERROR
2.25 3
+70°C ERROR +70°C ERROR
+25°C ERROR 2.00 +25°C ERROR 2
2.5 –40°C ERROR 1 –40°C ERROR
ERROR (dB)

ERROR (dB)
VRMSF (V)

VRMSF (V)

1.75 1
2.0 0 1.50 0
1.25 –1
1.5 –1
1.00 –2
1.0 –2 0.75 –3
0.50 –4
0.5 –3
0.25 –5
0 –4 0 –6
16085-018

16085-021

–30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30

RF INPUT (dBm) RF INPUT (dBm)

Figure 17. VRMSF and Error vs. RF Input Level and Temperature at 4 GHz, Figure 20. VRMSF and Error vs. RF Input and Temperature at 7 GHz, Error
Error Calculated Using Linear Regression of Data Between +20 dBm and Calculated Using Linear Regression of Data Between 20 dBm and 0 dBm,
−15 dBm, TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF− Open TADJS = 0.8 V, TADJI = 0.2 V, CHPF+/CHPF− Open

Rev. B | Page 13 of 26
ADL5920 Data Sheet
22 14

20
+85°C 12 +85°C
18
+25°C +25°C
16 10
–40°C –40°C
14
8
COUNT

COUNT
12

10
6
8

6 4

4
2
2

0 0

16085-022

16085-025
2.80 2.85 2.90 2.95 3.00 3.05 3.10 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
VRMSF (V) VRMSF

Figure 21. Distribution of VRMSF, PIN = 20 dBm, 1 GHz Figure 24. Distribution of VRMSF, PIN = 20 dBm, 6 GHz

18 14

16
12
+85°C +85°C
14
+25°C +25°C
10
12 –40°C –40°C

8
COUNT
COUNT

10

8 6

6
4
4
2
2

0 0
16085-023

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85
0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80

16085-026
VRMSF (V)
VRMSF (V)

Figure 22. Distribution of VRMSF, PIN = −20 dBm, 1 GHz Figure 25. Distribution of VRMSF, PIN = −10 dBm, 6 GHz

8 16

7 14

6 12

5 10
COUNT

COUNT

4 8

3 6

2 4

1 2

0 0
16085-030

16085-027

56.50 56.75 57.00 57.25 57.50 57.75 58.00 58.25 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0
SLOPE (mV/dB) SLOPE (mV/dB)

Figure 23. Distribution of Slope at 6 GHz Figure 26. Distribution of Slope at 1 GHz

Rev. B | Page 14 of 26
Data Sheet ADL5920
20 18

18 16

16 14
14
12
12

COUNT
10
COUNT

10
8
8
6
6
4
4

2 2

0 0

16085-028

16085-031
–31 –30 –29 –28 –27 –26 –25 –26 –25 –24 –23 –22 –21 –20 –19 –18 –17 –16
INTERCEPT (dBm) INTERCEPT (dBm)

Figure 27. Distribution of Intercept at 1 GHz Figure 30. Distribution of Intercept at 6 GHz

6.0 6.0
5.5 +15dBm 5.5 +15dBm
+10dBm +10dBm
5.0 0dBm 5.0 0dBm

VRMSF OUTPUT VOLTAGE (V)

VRMS OUTPUT VOLTAGE (V)

–10dBm –10dBm
4.5 RF ENABLE PULSE 4.5 RF ENABLE PULSE
4.0 4.0
3.5 3.5
3.0 3.0

2.5 2.5

2.0 2.0
1.5 1.5

1.0 1.0

0.5 0.5
0 0
16085-029

16085-033
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 40 80 120 160 200 240 280 320 360 400
TIME (ms) TIME (µs)

Figure 28. VRMSF Response to Various RF Input Burst Levels, Carrier Figure 31. VRMSF Response to Various RF Input Burst Levels, Carrier
Frequency = 1 GHz, CRMSF = 0.1 µF Frequency = 1 GHz, CRMSF = 0.01 µF
6.0 6.0
5.5 +20dBm 5.5 +20dBm
+10dBm +10dBm
5.0 0dBm 5.0 0dBm
VRMSF OUTPUT VOLTAGE (V)
VRMS OUTPUT VOLTAGE (V)

–10dBm –10dBm
4.5 PWDN/TADJS 4.5 PWDN/TADJS
4.0 4.0

3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0 0
16085-032

16085-036

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40
TIME (ms) TIME (ms)

Figure 29. VRMSF Response to PWDN/TADJS for Various RF Input Levels, Figure 32. VRMSF Response to PWDN/TADJS for Various RF Input Levels,
Carrier Frequency = 1 GHz, CRMSF = 0.1 µF Carrier Frequency = 1 GHz, CRMSF = 0.01 µF

Rev. B | Page 15 of 26
ADL5920 Data Sheet
0.22

0.20
100
SUPPLY CURRENT (mA)

SUPPLY CURRENT (A)

0.18

10 0.16

0.14

1
VPWDN/TADJS INCREASING 0.12
VPWDN/TADJS DECREASING

0 0.10

16085-038
16085-034
1.20 1.25 1.30 1.35 1.40 1.45 1.50 –60 –40 –20 0 20 40 60 80 100 120 140
VPWDN/TADJS (V) TEMPERATURE (°C)

Figure 33. Supply Current vs. PWDN/TADJS Voltage (VPWDN/TADJS) Figure 36. Supply Current vs. Temperature

60 50

50 40

40
30
COUNT
COUNT

30
20

20

10

0 0

16085-024
16085-035

1.26 1.29 1.32 1.35 1.38 1.41 1.44 1.47 1.50 2.44 2.46 2.48 2.50 2.52 2.54

VTEMP (V) VREF (V)

Figure 34. Distribution of VTEMP Voltage at TA = 25°C, No RF Input Figure 37. Distribution of VREF Voltage

1.9 5

1.8 4
VTEMP
1.7 3
ERROR (°C)
LINEARITY ERROR (°C)

1.6 2

1.5 1
VTEMP (V)

1.4 0

1.3 –1

1.2 –2

1.1 –3

1.0 –4

0.9 –5
16085-037

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 35. VTEMP and Linearity Error vs. Temperature

Rev. B | Page 16 of 26
Data Sheet ADL5920

THEORY OF OPERATION
The ADL5920 contains a symmetric and bidirectional resistive The two rms detectors are architecturally similar to the ADL5906
bridge plus two identical rms detectors that provide both but are internally dc-coupled to operate down to dc. The detectors
forward and reverse power indications at the VRMSF and provide linear in dB outputs and thereby give a direct indication in
VRMSR pins, respectively. A detailed description of the theory dBm of the applied forward and reverse signals. Due to their
of operation can be found in the Analog Dialogue article, An linear in dB response, the output voltages represent the coupled
Integrated Bidirectional Bridge with Dual RMS Detectors for and isolated port voltages in dB and thereby their difference
RF Power and Return Loss Measurement. directly indicates directivity or return loss, which is an
The device provides return loss and VSWR indication at the advantage over simple diode detectors that produce a linear in
VDIFF+ and VDIFF− outputs, where volt output. The detector slope of each detector output voltage
vs. PIN is approximately 60 mV/dB. Because both detectors are
VDIFF = (VDIFF+) – (VDIFF−) = VRMSF − VRMSR (1) identical, the difference in output voltage with a perfectly
The bridge has an insertion loss (IL) of 0.9 dB below about 1 GHz matched source and load (50 Ω RSOURCE and RLOAD) is the
when the source and load impedances are 50 Ω (the ADL5920 directivity of the bidirectional bridge and is calculated as
is only intended to be used in 50 Ω systems). The insertion loss follows:
increases with increasing frequency to 1.9 dB at 6 GHz. Note Directivity = ((VRMSF − VRMSR)/Slope) (dB) (3)
that insertion loss in dB is
Directivity is defined as follows:
IL = −20log10|S21| = −20log10|VRFOUT/VRFIN| (2)
Directivity (dB) = Coupling (dB) − Isolation (dB)
where: = 20log10(C/I) (4)
VRFOUT is the RFOUT voltage.
VRFIN is the RFIN voltage. Where the isolation (I) and coupling (C) factors are positive
numbers, and isolation is a smaller value than C.
As the source or load impedance deviates from 50 Ω, the
VRMSF and VRMSR outputs indicate this deviation via a In the default, single-supply and ac-coupled connection (see
reduction in the separation of these two voltages. For example, Figure 38), the ADL5920 device directivity is greater than 30 dB
with a fixed signal level applied to the RFIN port, as the load for frequencies below 400 MHz, as shown in Figure 5, which
resistance on the RFOUT port varies from a short-circuit shows as a constant difference voltage for the largest input
condition to an open circuit condition, only the VRMSR signal powers. When the signal is applied to the RFIN port (by definition
changes. The VRMSF output stays constant. The voltage in the forward direction), the resulting VDIFF, VRMSF – VRMSR,
difference indicates the return loss and reflection coefficient of is approximately constant at frequencies less than 100 MHz.
the load and indicates the directivity of the structure when However, as the input signal level reduces, eventually, the
RLOAD = RSOURCE = 50 Ω. rejected side limits at the noise and offset floor, and the VRMSR
output stays constant while the VRMSF output keeps decreasing
until this output also reaches the noise and offset floor. To
determine the inherent directivity of the ADL5920 measurement
system, apply a large enough input signal level to reliably
determine the isolated port voltage, which is best achieved
through a PIN sweep of around 100 MHz.

Rev. B | Page 17 of 26
ADL5920 Data Sheet

APPLICATIONS INFORMATION
BASIC CONNECTIONS frequency. For example, for a minimum input frequency of
For ac-coupled operation, the ADL5920 requires a single supply 1 MHz, the high-pass corner frequency must be set to 1 kHz to
of 5 V. The supply is connected to the VPOS1, VPOS2, and ensure that the offset compensation loop does not interfere with
VPOS3 supply pins. Decouple each of these pins using two the input signal being measured.
capacitors with values equal or similar to those shown in Figure 38. Capacitors connected between CHPF+ and CHPF− and between
Place these capacitors as close as possible to the VPOS pins. CHPR+ and CHPR− can reduce the corner frequency (f3dB) of
The RF input and output pins are ac-coupled using broadband the offset compensation loops for each detector. The following
0.01 µF capacitors, which allow operation down to approximately equation sets the corner frequency of the offset compensation
600 kHz. Larger value capacitors can reduce the minimum input loop:
frequency further. f3dB = 1/(2π × 2000 × (190 pF + CHPx±)) (5)
CHPR± AND CHPF± CAPACITORS For example, setting the CHPx± capacitors values to 0.1 µF
results in a high-pass corner of approximately 800 Hz, ensuring
Each rms detector contains an offset compensation loop that
reliable operation for input frequencies down to 800 kHz.
eliminates internal offset voltages and ensures optimal detector
sensitivity. The offset compensation loop works like a high-pass At input frequencies above 2 GHz, the presence of capacitors or
filter so that all input frequencies (and dc) below a certain stray capacitance on the CHPx± nodes adversely affects directivity.
corner frequency are nulled by the servo action of the loop. As a result, it is recommended to leave these nodes open with
An internal 190 pF capacitor and an internal 2 kΩ resistor sets no stray capacitance present for operation from 2 GHz to 7 GHz.
the nominal corner frequency of this loop. This configuration For broadband operation (for example, from 1 MHz to 7 GHz),
results in a high-pass corner frequency of approximately 400 kHz. it is recommended to use 0201 size capacitors and to mount the
For operation at a specific input frequency, the high-pass corner capacitors as close the pins as possible.
must be set two to three decades lower than this corner

EPAD GND6 GND5 GND4 GND3 GND2 GND1

30 29 28 27 24 1

ADL5920
31 26
RFIP C2 RFIN RFOUT C19
RFOP
32 BIDIRECTIONAL BRIDGE 25
0.01µF 0.01µF
VNEG1 VNEG2
2 23

CHPR+ CHPF+
3 21
C7 C13
(SEE TEXT) CHPR– CHPF– (SEE TEXT)
4 REVERSE FORWARD 22
C8 CRMSR PATH PATH CRMSF C12
9 RMS RMS 16
0.1µF DETECTOR DETECTOR 0.1µF

VREV
VRMSR VRMSF VFWD
7 18
DECL C10
12
4.7µF VOCM
VTEMP 6 VOCM 1kΩ
TEMPERATURE 10
SENSOR ×1 R1
VREF 19
VREF
1.4V 2.5V
VREF 3.6kΩ VTGT
VTGT
15
R1
(SEE TEXT) PWDN/TADJS TADJI VREF R2
5 20 2.43kΩ
R2 R9
(SEE TEXT) (SEE TEXT)
8 13 11 14 17
VPOS1 VPOS2 VDIFF– VDIFF+ VPOS3 R10
(SEE TEXT)
5V
C1 C6 C9 C11 C18 C14
0.1µF 100pF 0.1µF 100pF 0.1µF 100pF
16085-039

VDIFF
OUTPUT

Figure 38. Basic Connections for Single-Supply AC-Coupled Operation

Rev. B | Page 18 of 26
Data Sheet ADL5920
VREF INTERFACE TEMPERATURE DRIFT COMPENSATION
The VREF pin provides an internally generated voltage reference The TADJI and TADJS pins provide the option to optimize the
for the user. The VREF voltage is temperature stable and is temperature drift of the output voltages of ADL5920. The voltage
capable of sourcing 4 mA and sinking 50 µA maximum. To on TADJI provides compensation of intercept temperature drift
provide additional current sink capability, connect an external and the voltage on TADJS compensates for temperature drift of
resistor from VREF to GNDx. The voltage on this pin can drive the slope.
the PWDN/TADJS, TADJI, VTGT, and VOCM pins. Table 5 shows the recommended voltages for VTADJI and VTADJS to
VPOSx
minimize temperature drift over the intended temperature range
INTERNAL
VOLTAGE
(−40°C < TA < +85°C).
VREF
Table 5. Recommended VTADJI and VTADJS Values for Selected
Frequencies
18kΩ
16085-040
Frequency (GHz) VTADJI (V) VTADJS (V)
GNDx 0.01 0 0
Figure 39. VREF Interface Simplified Schematic 0.1 0 0
1 0 0
VDIFF OUTPUT INTERFACE 2 0 0.2
The ADL5920 contains a differential output stage (see Figure 40) 3 0 0.2
that converts the detector output voltages of VRMSF and VRMSR 4 0 0.2
to a differential voltage (VDIFF+ − VDIFF−) with two differential 5 0.2 0.2
amplifiers that each have a gain of one half. The differential gain 6 0.2 0
from VRMSF minus VRMSR to VDIFF+ − VDIFF− is therefore 7 0.2 0.8
equal to one, that is,
The TADI and TADJS pins have a high input impedance and
VDIFF+ − VDIFF− = VRMSF – VRMSR (6) can be conveniently driven from an external source or from an
The VOCM pin sets the output common-mode voltage of VDIFF. attenuated value of VREF using a resistor divider.
Because the difference voltage can be as large as 2 V to 2.5 V SETTING VTGT
depending on directivity and frequency, VOCM must be high
The voltage on the VTGT pin determines the settling point of
enough (at least 1.25 V for |VRMSF − VRMSR| = 2.5 V) such
internal automatic level control (ALC) loops that are part of the
that the negative swinging output voltage is not limited at ground.
rms computation core. The recommended value for VTGT is
A voltage of midsupply (2.5 V) is optimal for VOCM. The
1 V, which represents a compromise between achieving excellent
VOCM pin must be driven by a low impedance because the
rms accuracy and maximizing dynamic range. The voltage on
current flowing in and out of this pin can be up to ±2 mA,
VTGT can be derived from the VREF pin using a resistor
depending on the voltage applied to the VOCM pin and the
divider, as shown in Figure 38. Like the resistors chosen to set
voltages present on VRMSF and VRMSR. VOCM can connect
the voltage on TADJI and TADJS, the resistors setting VTGT
directly to VREF. However, the connection must include a 1 kΩ
must have reasonable values that do not pull too much current
resistor to ground, as shown in Figure 38.
from VREF or cause bias current errors. In addition, note the
VRMSF VRMSR
combined current that VREF must deliver to generate the voltages
on TADJI, TADJS and VTGT (which cannot exceed 4 mA).

2kΩ 2kΩ 2kΩ

1kΩ 1kΩ 1kΩ

16085-041

VDIFF– VOCM VDIFF+

Figure 40. Differential Output Stage

Rev. B | Page 19 of 26
ADL5920 Data Sheet
CHOOSING VALUES FOR CRMSF AND CRMSR Figure 41 also shows how the response time is affected by the
CRMSF and CRMSR provide the averaging function for the value of CRMSF and CRMSR. To measure this response time, an
rms computation in the forward path and reverse path rms RF burst at 2.14 GHz at 0 dBm is applied to the ADL5920. The
detectors, respectively. Using the minimum value for these 10% to 90% rise time and 90% to 10% fall time are then
capacitances allows the quickest response time to a pulsed measured.
waveform but leaves significant output noise on the output Table 6 shows the recommended minimum values of CRMSF and
voltage signal, especially with input signals that are modulated. CRMSR for popular modulation schemes. Using lower capacitor
Similarly, a large filter capacitor reduces output noise at the values results in rms measurement errors. Output response time
expense of response time. is also shown. If the output noise shown in Table 6 is too high,
In applications where response time is not critical, place a increase the CRMSF and CRMSR values to reduce the noise.
relatively large capacitor on the CRMSF and CRMSR pins. In However, increasing the CRMSF and CRMSR values results in
Figure 38, a 0.1 μF capacitor was used on these pins. For most slower rise and fall times.
signal modulation schemes, this value ensures excellent rms The values in Table 6 are experimentally determined as the
measurement compliance and low residual output noise. There minimum capacitance that ensures achieving the specified rms
is no maximum capacitance limit for CRMSF and CRMSR. accuracy for that particular signal type. This test is carried out
Figure 41 shows how output noise varies with CRMSF when by starting out with a large capacitance value on the CRMSF pin
the ADL5920 is driven by a single-carrier W-CDMA signal (for example, 10 μF). The VRMSF value is noted for a fixed
(Test Model TM1-64, peak envelope power = 10.56 dB, input power level (for example, 10 dBm). The CRMSF value is
bandwidth = 3.84 MHz). The response for the reverse path then progressively reduced (with press down capacitors) until
is identical. the value of VRMSF starts to deviate from its original value.
350 1000000
This deviation indicates that the accuracy of the rms computation
OUTPUT NOISE (mV p-p)
RISE TIME (µs) is degrading and that CRMSF is becoming too small).
FALL TIME (µs)
300 100000
In general, the minimum required rms averaging capacitance
increases as the peak to average ratio of the carrier increases. The
RISE TIME/FALL TIME (µs)
OUTPUT NOISE (mV p-p)

250 10000
minimum required CRMSF and CRMSR values also tend to
200 1000 increase as the bandwidth of the carrier decreases. With
narrow-band carriers, the noise spectrum of the VRMSF and
150 100
VRMSR outputs tend to have a correspondingly narrow profile.
100 10
The relatively narrow spectral profile demands larger CRMSF
and CRMSR values to reduce the low-pass corner frequency of
50 1 the averaging function and to ensure a valid rms computation.

0 0.1
16085-042

1 10 100 1000 10000

CRMS (nF)

Figure 41. Output Noise, Rise and Fall Times vs. CRMS Capacitance,
Single-Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm

Table 6. Recommended Minimum Capacitor Values on CRMSF and CRMSR for Various Modulation Schemes
Peak Envelope Carrier CRMSF and Output Noise Rise/Fall
Modulation/Standard Power Ratio (dB) Bandwidth (MHz) CRMSR (nF) (mV p-p) Time (μs)
QPSK, 5 MSPS (SQR COS Filter,  = 0.35) 3.8 5 1 84 0.2/10
QPSK ,15 MSPS (SQR COS Filter,  = 0.35) 3.8 15 1 42 0.2/10
64 QAM, 1 MSPS (SQR COS Filter,  = 0.35) 7.4 1 10 265 3/85
64 QAM, 5 MSPS (SQR COS Filter,  = 0.35) 7.4 5 1 380 0.2/10
64 QAM, 13 MSPS (SQR COS Filter,  = 0.35) 7.4 13 1 205 0.2/10
W-CDMA, One Carrier, TM1-64 10.56 3.84 1 820 0.2/10
W-CDMA Four Carrier, TM1-64, TM1-32, TM1-16, TM1-8 12.08 18.84 1 640 0.2/10
LTE, TM1, One Carrier, 20 MHz (2048 QPSK Subcarriers) 11.58 20 1 140 0.2/10

Rev. B | Page 20 of 26
Data Sheet ADL5920
RF POWER AND RETURN LOSS CALCULATION Where PINR is the power level in dBm applied to the RFOUT pin
Figure 42 shows the voltage measured on VRMSF and VRMSR with the RFIN pin terminated with 50 Ω.
when RFIN is swept across its power range at various frequencies Because slope and intercept vary from device to device and vs.
with a 50 Ω termination on RFOUT. frequency, calibration must be performed to achieve high
The VRMSR output ideally only responds to power reflected accuracy.
from the load. However, because of the finite directivity of the In general, calibration is performed by applying two or more
bridge circuit of the ADL5920, the VRMSR voltage starts to known signal levels (PIN1 and PIN2 in this case) to the input of
increase as the RF power at RFIN increases. Thereafter, the the ADL5920 and measuring the corresponding output voltages
VRMSR voltage follows a similar linear in dB response as (VRMSF1 and VRMSF2). The calibration points must be within the
VRMSF, although at a much lower level. At a particular linear operating range of the device.
frequency, the difference in output voltage between VRMSF and With a two-point calibration, calculate the slope and intercept
VRMSR, where both voltages are following this linear in as follows:
dB characteristic, is proportional to the directivity in dB of the
bridge circuit when the load is 50 Ω. As frequency increases, the Slope = (VRMSF1 − VRMSF2)/(PRFIN1 − PRFIN2) (9)
vertical difference between the VRMSF and VRMSR traces Intercept = PRFIN1 − (VRMSF1/Slope) (10)
decreases, indicating a decrease in directivity. After the slope and intercept are calculated and stored in
4.0
nonvolatile memory during equipment calibration, use the
5GHz VRMSF
following equation to calculate the unknown input power based
VRMSF, VRMSR OUTPUT VOLTAGE (V)

3.5 3GHz VRMSF

7GHz VRMSF on the output voltage of the detector:
3.0 1GHz VRMSF
10MHz VRMSF
5GHz VRMSR PRFIN (Unknown) = (VRMSF(MEASURED)/Slope) + Intercept (11)
2.5 3GHz VRMSR
7GHz VRMSR Perform a separate calibration to establish the slope and intercept
2.0
1GHz VRMSR
10MHz VRMSR of the reverse path. Alternatively, because the forward and
reverse path bridge circuits and rms detectors are matched
1.5
closely, use the slope and intercept from the forward path
1.0 calibration to convert the VRMSR voltage to the equivalent
0.5
dBm RF power. Using this methodology, use the following
equations to calculate forward power (PFWD), reverse power
0 (PREV), and return loss.
16085-043

–40 –30 –20 –10 0 10 20 30

RF INPUT (dBm) PFWD (dBm) = (VRMSF/Slope) + Intercept (12)
Figure 42. VRMSF, VRMSR Output Voltage vs. RF Input at Various Frequencies
When Bridge Driven from RFIN and RFOUT Terminated with 50 Ω PREV (dBm) = (VRMSR/Slope) + Intercept (13)

Use the following equation to calculate the idealized output Return Loss (dB) = (PFWD − PREV) + Insertion Loss (dB) (14)
voltage on VRMSF (VRMSF(IDEAL)): Note that insertion loss has a negative sign for a passive load.
VRMSF(IDEAL) = Slope × (PINF − Intercept) (7) Return loss can also be calculated by using the VDIFF+ and VDIFF−
differential outputs.
where:
Slope is the change in output voltage divided by the dB change Return Loss (dB) = (VDIFF+ − VDIFF−)/Slope +
in input power. Insertion Loss (dB) (15)
PINF is the power level in dBm applied to the RFIN pin. To calculate the directivity of the bridge circuit, place a 50 Ω
Intercept is the calculated input power level (in dBm) at which load on RFOUT and measure VDIFF+ and VDIFF−. Directivity in
the output voltage is equal to 0 V. Note that Intercept is an dB is then given by the following equation:
extrapolated theoretical value, not a measured value.
Directivity (dB) = (VDIFF+ − VDIFF−)/Slope (16)
The equation for VRMSR(IDEAL) is similar with the exception that
PINR substitutes in for PINF.
VRMSR(IDEAL) = Slope × (PINR − Intercept) (8)

Rev. B | Page 21 of 26
ADL5920 Data Sheet
DC-COUPLED OPERATION connect capacitors to the CHPF and CHPR pins to reduce the
The ADL5920 RFIN and RFOUT pins can be dc-coupled as corner frequency of the offset compensation loops as previously
shown in Figure 43. However, to drive the inputs with signals detailed. In addition, connect the DECL pin (Pin 12) to ground
that are biased at 0 V, apply a negative supply of −2.5 V to the to ensure that the specified directivity is achieved at low
two VNEG pins as shown in Figure 43. If dc-coupled operation frequencies.
is required for the sake of applying low input frequencies,

EPAD GND6 GND5 GND4 GND3 GND2 GND1

30 29 28 27 24 1

ADL5920
31 26
RFIP RFIN RFOUT RFOP
32 BIDIRECTIONAL BRIDGE 25

–2.5V VNEG1 VNEG2 –2.5V

2 23
C5 C16 C15 C17
0.1µF 100pF CHPR+ CHPF+ 0.1µF 100pF
3 21
C7 C13
1µF CHPR– CHPF– 1µF
4 REVERSE FORWARD 22
C8 CRMSR PATH PATH CRMSF C12
9 RMS RMS 16
0.1µF DETECTOR DETECTOR 0.1µF

VREV
VRMSR VRMSF VFWD
7 18
DECL
12

VTEMP VOCM 1kΩ VOCM

6 TEMPERATURE 10
SENSOR ×1 R1
VREF VREF
1.4V 2.5V
19
3.6kΩ VTGT
VTGT
15
PWDN/TADJS TADJI
55 20

8 13 11 14 17
VPOS1 VPOS2 VDIFF– VDIFF+ VPOS3

+5V
C1 C6 C9 C11 C18 C14
0.1µF 100pF 0.1µF 100pF 0.1µF 100pF

16085-044
VDIFF
OUTPUT

Figure 43. Basic Connections for DC-Coupled Operation

Rev. B | Page 22 of 26
Data Sheet ADL5920

EVALUATION BOARD
The ADL5920-EVALZ is a fully populated, 4-layer, FR4-based with the load on RFIN). The output voltages are available on the
evaluation board. For normal operation, the board requires a VRMSR, VRMSF, VDIFF+, and VDIFF− SMA connectors or
5 V, 200 mA power supply. The 5 V power supply must be on the adjacent test loops. Configuration options for the
connected to the VPOS and GND test loops. The RF input and evaluation board are listed in Table 7. Note that an Arduino/
load must be applied to the RFIN and RFOUT 2.92 mm Linduino based evaluation platform for the ADL5920 is also
connectors, respectively (because the ADL5920 is fully available (Part Number DC2847A-Kit). For more information,
bidirectional, the input signal can also be applied to RFOUT go to www.analog.com/ADL5920.
GND1 GND2
J1 C20 C21 J2

0.01µF 0.01µF

GND GND
RFIN C2 GND C19 RFOUT
P1
0.01µF 0.01µF TADJS
1
VNEG VRSMR 2
3
VPOS GND GND VTEMP 4
C5 R3 R8 C15 5
VPOS 6
0.1µF 0Ω 0Ω 0.1µF
GND 7
S1 3 GND VOCM 8
1 GND GND GND
9
2 VDIFF+
PAD

VTEMP 10
C7
32
31
30
29
28
27
26
25

VDIFF– 11
0.1µF 12
RFIN
RFIN

RFOUT
RFOUT
EPAD

GND6
GND5
GND4
GND3

VTGT 13
14
1 24 C13 VREF 15
R1 R2 GND1 GND2
0Ω 2 23 0.1µF 16
100Ω VNEG1 VNEG2 VRSMF 17
DNI 3
CHPR+ ADL5920 CHPF–
22
4 21 18
VREF CHPR– CHPF+ TADJI 19
5 20 R9
GND PWDN/TADJS TADJI R10 20
6 19 0Ω VNEG
VTEMP VREF DNI 100Ω GND
7 18
VRMSR VRMSF
8 VREF VRMSF
VRMSR VPOS1 VPOS3 GND
CRMSR

CRMSF
VDIFF+
VDIFF–

VPOS2
VOCM

DECL

VTGT

GND 543 2
2345 GND C14 C18
100pF 0.1µF VRMS_F
9
10
11
12
13
14
15
16

VRMS_R C1 C6
GND
0.1µF 100pF C8 GND GND
0.1µF
GND GND GND C12
GND C10
0.1µF
4.7µF
VREF GND
GND
R4 VOCM C9 C11
0Ω 0.1µF 100pF VREF

R5 GND GND VTGT

R6
VDIFFN 1kΩ 3.6kΩ

VDIFF– GND
R7
2.43kΩ

2 3 4 5 VDIFF+ GND
VDIFFP
GND
2345
16085-045

GND

Figure 44. Evaluation Board Schematic

Rev. B | Page 23 of 26
ADL5920 Data Sheet

16085-046

Figure 45. Evaluation Board Layout, Component Side

Table 7. Evaluation Board Configuration and Operation

Component Function Description/Comments Default Value
VPOS, GND1, GND2, C1, C6, C9, C11, C14, C18 Power supply interface and decoupling. Apply a 5 V power VPOS = 5 V,
supply from the evaluation board to the VPOS and GND1/GND2 GND1 = GND2 = 0 V,
test loops (GND1 and GND2 are connected to a common ground). C1, C9, C18 = 0.1 µF (0402),
The nominal supply decoupling on the VPOS1, VPOS2, and C6, C11, C14 = 100 pF
VPOS3 pins consist of a 100 pF capacitor and a 0.1 µF capacitor (0402)
on each power supply pin, with the 100 pF capacitor placed
closer to the pin.
RFIN, RFOUT, C2, C19 RF inputs and outputs to bridge circuit. The main signal path is C2 = C19 = 0.01 µF (0201),
ac-coupled by 0.01 µF, 0201 capacitors, setting the input corner RFIN, RFOUT = 2.92 mm
frequency to approximately 600 kHz. For operation at lower end launch connector
frequencies, larger capacitor values can be installed. The RFIN
and RFOUT connectors are interchangeable, allowing the source
signal driven into RFOUT with the load connected to RFIN. The
RFIN and RFOUT connectors are 2.92 mm. Take care when
attaching to these connectors because of mechanical fragility.
J1, J2, C20, C21 Calibration path. This path can calibrate out the insertion loss C20 = C21 = 0.01 µF
of the RFIN and RFOUT traces. This signal path is ac-coupled by (0201), J1, J2 = 2.92 mm
0.01 µF, 0201 capacitors. The J1 and J2 connectors are 2.92 mm. end launch connector
Take care when connecting to these connectors because of
mechanical fragility.

Rev. B | Page 24 of 26
Data Sheet ADL5920
Component Function Description/Comments Default Value
VNEG, C5, C15, R3, R8, C10 Negative supply. The main signal path from RFIN and RFOUT VNEG = 0 V,
can be dc-coupled by connecting a −2.5 V supply to the VNEG R3 = R8 = 0 Ω (0603),
test loop and replacing ac coupling capacitors, C2 and C19, C15 = C5 = 0.1 µF (0402),
with 0 Ω resistors. R3 and R8 must be removed and replaced C10 = 4.7 µF (0402)
with 100 pF capacitors pins. Connect the DECL pin to ground
by removing C10 and replacing it with a 0 Ω resistor. In this
mode, the voltage on VPOS must remain at 5 V.
R6, R7 VTGT interface. R7 and R6 are driven from VREF (2.5 V) and R7 = 2.43 kΩ, R6 = 3.6 kΩ,
provide 1 V to VTGT. If R6 and R7 are removed, an external VTGT = 1 V
voltage can be applied on the VTGT test point.
C7, C13 RMS detector offset compensation loop. The capacitances on C7, C13 = 0.1 µF (0201)
these pins set the corner frequency of internal offset
compensation loops of the two rms detectors. These loops
limit the minimum input frequency that can be sensed by the
ADL5920. The default values for these capacitors set minimum
input frequencies that are well below the frequency corner set
by the ac-coupling capacitors in the main signal path. These
capacitors are deliberately located as close as possible to Pin 3
and Pin 4 and Pin 21 and Pin 22. To achieve the specified
directivity when operating above 2 GHz, remove these
capacitors (see Figure 5).
S1, R1, R2, PWDN/TADJS Device enable and slope temperature compensation. S1 is S1 = open position,
used to disable the ADL5920 by connecting the PWDN/TADJS R1 = 0 Ω DNI,
pin to VPOS. In its other position, S1 is open and the voltage R2 = 100 Ω,
on PWDN/TADJS is set by VREF (2.5 V) and the R1, R2 resistor PWDN/TADJS = 0 V
divider. This voltage is used to fine tune the temperature
stability of the slope of the rms detectors.
VTEMP Temperature sensor output. This yellow test loop is connected Not applicable
directly to Pin 6 of the ADL5920 (VTEMP).
VRMSF, RMSR, VRMS_F, RMS_R Reverse and forward rms voltage measurement. The voltages VRMSF, VRMSR = SMA
on these connectors are proportional to the dB power of the end launch connector,
forward and reverse signals in the bridge circuit. VRMS_F, VRMS_R =
yellow test loops
C8, C12 RMS averaging capacitors. The value of the rms averaging C8 = C12 = 0.1 µF (0402)
capacitor must be set based on the peak to average ratio of
the input signal and based on the desired output response
time and residual output noise on the rms detector outputs.
VOCM, R4, R5 Common-mode voltage for VDIFF+ and VDIFF−. The voltage R4 = 0 Ω (0402),
on VOCM pin (Pin 10) sets the common-mode level for the R5 = 1 kΩ (0402),
VDIFF+ and VDIFF− differential pair. The nominal voltage on VOCM = 2.5 V
this pin must be 2.5 V. This input requires a bias current of
±1 mA and must be driven from a low impedance source. The
nominal biasing method for VOCM is to connect it to VREF and
connecting a 1 kΩ resistor from VOCM to ground. An external
voltage can be applied VOCM through Pin 8 of the P1 connector.
VDIFF+, VDIFF−, VDIFFN, VDIFFP Return loss measurement. The output voltage from this VDIFF+, VDIFF− = SMA
differential pair is proportion to the ratio of the forward and end launch connector,
reverse power in the bridge circuit. The common-mode level is VDIFFN, VDIFFP = yellow
set by the voltage on VOCM. test loops
R9, R10, TADJI TADJI interface. R9 and R10 set the voltage on the TADJI pin R9 = 0 Ω DNI,
that is derived from VREF. This voltage is used to fine tune the R10 = 100 Ω (0402),
temperature stability of the Intercept of the rms detectors. TADJI = 0 V
P1 P1 header. The P1 header can access all of the dc levels on the Not applicable
evaluation board.

Rev. B | Page 25 of 26
ADL5920 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10 0.30
5.00 SQ 0.25
PIN 1
INDICATOR 4.90 0.18
AREA
25 32 P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
24 1

0.50
BSC
3.25
EXPOSED 3.10 SQ
PAD
2.95

17 8

0.50 16 9
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF

09-12-2018-A
PKG-003898

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD

Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Ordering Quantity
ADL5920ACPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 490
ADL5920ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 250
ADL5920ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 1500
ADL5920-EVALZ Evaluation Board with Voltage Outputs
DC2847A-Kit ADL5920 Linduino Demo Kit
1
Z = RoHS Compliant Part.

©2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D16085-0-12/19(B)

Rev. B | Page 26 of 26