Scribd
Upload
28 views20 pages

Aeld'25 Project Ieee 802 11 A

The document outlines the design and development of an IEEE 802.11a architecture on a Zedboard, focusing on the evolution of OFDM and its implementation. It details the signal parameters, modulation techniques, frame design, channel modeling, and various estimation methods such as CFO and channel estimation. The deliverables include implementing a transceiver, calculating EVM and BER for different SNRs, and designing various IPs for modulation and detection processes.

Uploaded by

mintu22296
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
28 views20 pages

Aeld'25 Project Ieee 802 11 A

The document outlines the design and development of an IEEE 802.11a architecture on a Zedboard, focusing on the evolution of OFDM and its implementation. It details the signal parameters, modulation techniques, frame design, channel modeling, and various estimation methods such as CFO and channel estimation. The deliverables include implementing a transceiver, calculating EVM and BER for different SNRs, and designing various IPs for modulation and detection processes.

Uploaded by

mintu22296
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 20

Design & Development of IEEE

802.11a Architecture on Zedboard


Jai Mangal
PhD Scholar, ECE
IIIT Delhi
AELD Project 2025
Why This Project (Evolution of OFDM)

Cooley, J. W., & Tukey, J. W. (1965). "An algorithm for the machine calculation
of complex Fourier series." Mathematics of Computation, 19(90), 297-301.
OFDM Block Design

Channel
Modulation

Insert CP & Packet


S/P IFFT P/S DAC & ADC
Preamble Detection
Noise
Demodulation

Remove Channel Fine CFO Coarse CFO


P/S FFT S/P
CP Estimation Estimation Estimation
Signal Parameters

Signal Parameters Value

Centre Frequency 5 GHz

Bandwidth 20 MHz

Sample Time 50 ns

FFT Size 64
Short Preamble
Virtual Virtual
S_k Short_preamble_slot_Frequency
Subcarrier Subcarrier
[1x53] [1x64]
[1x6] [1x5]

IFFT
Short_preamble_slot_Frequency Short_preamble_slot_Time
[1x64] [1x64]

Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot
[1x16] [1x16] [1x16] [1x16] [1x16] [1x16] [1x16] [1x16] [1x16] [1x16]

16 Slots repeated 10 times = 160 samples


Long Preamble
Virtual Virtual
L_k Long_preamble_slot_Frequency
Subcarrier Subcarrier
[1x53] [1x64]
[1x6] [1x5]

Long_preamble_slot_Frequency IFFT Long_preamble_slot_Time


[1x64] [1x64]

CP Slot Slot
[1x32] [1x64] [1x64] 32 + 64 + 64 = 160 samples
Payload
VS Data Pilot Data Pilot Data 0 Data Pilot Data Pilot Data VS
[1x6] [1x6] [1x1] [1x13] [1x1] [1x6] [1x1] [1x6] [1x1] [1x13] [1x1] [1x6] [1x6]

Payload_Frequency IFFT
Payload_Time
[1x64]
[1x64]

CP Payload_time
16 + 64 = 80 samples
[1x16] [1x64]
QPSK Modulation & Demodulation

Bits Symbols Constellation Points

00 0 0.707 + i 0.707

01 1 - 0.707 + i 0.707

10 2 -0.707 - i 0.707

11 3 0.707 - i 0.707
Frame Designing / Transmit Signal
Short Long Short Long
Payload 1 Payload 2 Payload 1 Payload 2
Preamble Preamble Preamble Preamble
[1x80] [1x80] [1x160] [1x160]
[1x160] [1x160] [1x320] [1x320]

160 + 160 + 80 + 80 = 480 samples Oversample by 2 320 + 320 + 160 + 160 = 960 samples

Apply RRC Filter

Short Long
RRC Filter Payload 1 Payload 2 RRC Filter
Preamble Preamble
[1x10] [1x160] [1x160] [1x10]
[1x320] [1x320]

10 + 320 + 320 + 160 + 160 + 10 = 980 samples


Channel Model

Transmit Signal Received Signal


[980 x 10 = 9800] [Catches only 3000 Samples]

AWGN Noise (Add Noise Based on Desired SNR)


Received Signal

Apply RRC Filter Catch Rx


Catch Rx RRC Filter RRC Filter
Samples
Samples [1x10] [1x10]
[1x3000]
[1x3000]

10 + 3000 + 10 = 3020 samples


Packet Detection (Delay & Correlate)

1. Perform Correlation

2. Find Power

3. Normalize
Coarse / Fine CFO Estimation
1. Calculation of Complex Conjugate 1. Calculation of Complex Conjugate

2. Coarse CFO Estimation 2. Fine CFO Estimation

3. Apply Coarse CFO to Rx Frame 3. Apply Fine CFO to Rx Frame


Channel Estimation & Equalizer
1. Extract sections of fine CFO

2. Perform FFT

3. Average the FFT of both Long preamble sections and taking the conjugate of the Short preamble.

4. Perform IFFT to get the channel estimate in the time domain

5. Divide the received frame with the channel estimates.


Automatic Gain Control (AGC)
1. If real part of received signal as well as imaginary part > 0, then map to 0.707 + i 0.707

2. If real part < 0 and imaginary part > 0, then map to -0.707 + i 0.707

3. If real part < 0 and imaginary part < 0, then map to -0.707 - i 0.707

4. If real part > 0 and imaginary part < 0, then map to 0.707 - i 0.707
Error Vector Magnitude (EVM)
1. Error = QPSK_MODULATED_Data_Rx - QPSK_Modulated_Data_Tx (Calculate Error)

2. Calculate RMS value of the error magnitude normalized by RMS value of transmitted symbols

3. Perform 20*log10(ans) to convert to dB scale.


Bit Error Rate (BER)
1. Bit_Error = Data_Rx - Data_Tx (Calculate Error)

2. Divide the number of bits in error with total number of bits.


Deliverables (Till Midsem)

1. Implement the IEEE 802.11a transceiver on processor

2. Calculate EVM for different SNRs

3. Calculate BER for different SNRs

4. Calculate the PS execution time


Deliverables (Till Endsem)
1. Design the IP for QPSK modulation

2. Design the IP for packet detection (Correlation)

3. Design the IP for Coarse CFO estimation (Angle calculation)

4. Design the IP for Fine CFO estimation (Angle calculation)

5. Design the IP for channel estimation & equalization

6. Design the IP for QPSK demodulation

7. Calculate EVM for different SNRs

8. Calculate SNR for different SNRs

9. Calculate & compare the PS & PL execution time


Thank You

You might also like