Digital Logic Design

Online Lecture
Exclusive OR/ Exclusive NOR
▪ The eXclusive OR (XOR) function is an important Boolean
function used extensively in logic circuits.
▪ The XOR function may be;
• implemented directly as an electronic circuit (truly a gate) or
• implemented by interconnecting other gate types (used as a convenient
representation)
▪ The eXclusive NOR function is the complement of the XOR
function
▪ By definition, XOR and XNOR gates are complex gates.
Exclusive OR/ Exclusive NOR
▪ Uses for the XOR and XNORs gate include:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
▪ Definitions
• The XOR function is: XY = XY+XY
• The eXclusive NOR (XNOR) function, otherwise
known as equivalence is: XY = XY+XY
▪ Strictly speaking, XOR and XNOR gates do no exist for more
than two inputs. Instead, they are replaced by odd and even
functions.
Truth Tables for XOR/XNOR
▪ Operator Rules: XOR XNOR
X Y XY X Y (XY)
or X Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
▪ The XOR function means:
X OR Y, but NOT BOTH
▪ Why is the XNOR function also known as the
equivalence function, denoted by the operator ?
XOR/XNOR (Continued)
▪ The XOR function can be extended to 3 or more variables. For more than 2
variables, it is called an odd function or modulo 2 sum (Mod 2 sum), not an
XOR:
X  Y Z = XYZ+ XYZ+ XYZ+ XYZ
▪ The complement of the odd function is the even function.
▪ The XOR identities:

X0 X = X 1 X =
XX =0 XX =1
XY = YX
( X  Y)  Z = X  ( Y  Z ) = X  Y  Z
Symbols For XOR and XNOR
▪ XOR symbol:

▪ XNOR symbol:

▪ Shaped symbols exist only for two inputs

XOR Implementations
▪ The simple SOP implementation uses the following structure:
X

X Y

▪ A NAND only implementation is:

X

X Y

Y
Odd and Even Functions
▪ The odd and even functions on a K-map form “checkerboard”
patterns.
▪ The 1s of an odd function correspond to minterms having an
index with an odd number of 1s.
▪ The 1s of an even function correspond to minterms having an
index with an even number of 1s.
▪ Implementation of odd and even functions for greater than four
variables as a two-level circuit is difficult, so we use “trees” made
up of :
• 2-input XOR or XNORs
• 3- or 4-input odd or even functions
 Example: Odd Function Implementation
▪ Design a 3-input odd function F = X + Y + Z
with 2-input XOR gates
▪ Factoring, F = (X + Y) + Z
▪ The circuit:

X
Y
F
Z
Example: Even Function Implementation
▪ Design a 4-input odd function F = W + X + Y + Z
with 2-input XOR and XNOR gates
▪ Factoring, F = (W + X) + (Y + Z)
▪ Implementation of even function using odd inputs
▪ The circuit:

W
X
F
Y
Z
Parity Generators/ Checkers
• In Chapter 1, a parity bit added to n-bit code to produce an n + 1 bit code:
➢ Add odd parity bit to generate code words with even parity
➢ Add even parity bit to generate code words with odd parity
➢ Use odd parity circuit to check code words with even parity
➢ Use even parity circuit to check code words with odd parity
• Example: n = 3. Generate even X
parity code words of length four Y
with odd parity generator: P
Z
• Check even parity code words of length four with
X
odd parity checker: Y
• Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) E
and E = 0. If Y changes from 0 to 1 between Z
generator and checker, then E = 1 indicates an error. P
Combinational Circuits
• A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
• A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

Design Procedure
Example: Design a circuit diagram
A circuit that generates square of a 3 bit number

1 0 0
BC
A
K-map for S0: 0 1 1 0
S0 = C
0 1 1 0
 BC
A
K-map for S2: 0 0 0 1
S2 = BC’
0 0 0 1

BC
A
K-map for S3: 0 0 1 0
S3 = AB’C + A’BC
0 1 0 0

BC
A
K-map for S4: 0 0 0 0
S4 = AB’ + AC
1 1 1 0

BC
A
K-map for S5: 0 0 0 0
S5 = AB
0 0 1 1
Analysis Procedure
• Boolean Expression Approach
A
B
F1
C T2=ABC
T1=A+B+C
A T3=AB'C'+A'BC'+A'B'C
B
C
A F’2=(A’+B’)(A’+C’)(B’+C’)
B

A
F2
C
F2=AB+AC+BC
B
C F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Analysis Procedure
• Truth Table Approach
A =0
0 0
A B C F1 F2
B =0
F1 0 0 0 0 0
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1 0 0 1
B =1 0 1 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0
1 1 0 0
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0
0 1 0 0 1 0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0
Analysis Procedure
• Truth Table Approach A B C F1 F2
A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
Design Procedure:

Given a problem statement:

▪ Determine the number of inputs and outputs
▪ Derive the truth table
▪ Simplify the Boolean expression for each output
▪ Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

➢ 4-bits ➢ 4-bits
? ➢ Value+3
➢ 0-9 values
• BCD-to-Excess 3 Converter

C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A x x
A x x
1 0 1 1 x x x x 1 1
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
• BCD-to-Excess 3 Converter

A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
Gray to Binary Code

• Design a circuit to Gray Binary

ABC xyz
convert a 3-bit Gray
000 000
code to a binary code 10 0 001
• The formulation gives 110 010
the truth table on the 010 011
right 01 1 100
111 101
• It is obvious from this 101 110
table that X = C and the 001 111
Y and Z are more complex
Seven-Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111
1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...