UC1841

UC2841
UC3841
Programmable, Off-Line, PWM Controller
FEATURES DESCRIPTION
• All Control, Driving, Monitoring, and The UC1841 family of PWM controllers has been designed to increase
Protection Functions Included the level of versatility while retaining all of the performance features of
• Low-current, Off-line Start Circuit the earlier UC1840 devices. While still optimized for highly-efficient boot-
strapped primary-side operation in forward or flyback power converters,
• Voltage Feed Forward or Current the UC1841 is equally adept in implementing both low and high voltage
Mode Control input DC to DC converters. Important performance features include a
• Guaranteed Duty Cycle Clamp low-current starting circuit, linear feed-forward for constant volt-second
operation, and compatibility with either voltage or current mode topologies.
• PWM Latch for Single Pulse per Period
In addition to start-up and normal regulating PWM functions, these de-
• Pulse-by-Pulse Current Limiting Plus vices include built in protection from over-voltage, under-voltage, and
Shutdown for Over-Current Fault over-current fault conditions with the option for either latch-off or automat-
ic restart.
• No Start-up or Shutdown Transients
While pin compatible with the UC1840 in all respects except that the po-
• Slow Turn-on Both Initially and After
larity of the External Stop has been reversed, the UC1841 offers the fol-
Fault Shutdown
lowing improvements:
• Shutdown Upon Over- or 1. Fault latch reset is accomplished with slow start discharge rather
Under-Voltage Sensing
than recycling the input voltage to the chip.
• Latch Off or Continuous Retry After 2. The External Stop input can be used for a fault delay to resist
Fault
shutdown from short duration transients.
• PWM Output Switch Usable to 1A 3. The duty-cycle clamping function has been characterized and
Peak Current specified.
• 1% Reference Accuracy The UC1841 is characterized for -55°C to +125°C operation while the
• 500kHz Operation UC2841 and UC3841 are designed for -25°C to +85°C and 0°to +70°C,
respectively.
• 18 Pin DIL Package
BLOCK DIAGRAM

Note: Positive true logic, latch outputs high with set, reset has priority.
6/93
 UC1841
UC2841
UC3841
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, +VIN (Pin 15) (Note 2) Operating Junction Temperature . . . . . . . . . . -55°C to +150°C
Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C
Current Driven, 100mA maximum . . . . . . . . . . . . Self-limiting Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V Note 1: All voltages are with respect to ground, Pin 13.
PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA Currents are positive-into, negative-out of the specified
PWM Output Peak Energy Discharge . . . . . . . . . . . . 20µJoules terminal.
Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA Note 2: All pin numbers are referenced to DIL-18 package.
Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA Note 3: Consult Packaging Section of Databook for thermal
Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA limitations and considerations of package.
VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA
Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V
Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V
Comparator Inputs
PLCC-20, LCC-20
PACKAGE PIN FUNCTIONS
(Pins 1, 7, 9-11, 16) . . . . . . . . . . . . Internally clamped at 12V
(TOP VIEW)
FUNCTION PIN
Power Dissipation at TA = 25°C (Note 3) . . . . . . . . . . . 1000mW Q or L Package
Comp 1
Power Dissipation at TC = 25°C (Note 3) . . . . . . . . . . . 2000mW Start/UV 2
CONNECTION DIAGRAMS OV Sense 3
Stop 4
DIL-18, SOIC-18 (TOP VIEW)
Reset 5
J or N, DW Package
CUR Thresh 7
CUR Sense 8
Slow Start 9
RT/CT 10
Ramp 11
VIN Sense 12
PWM Out 13
Ground 14
Drive Bias 15
+VIN Supply 17
5.0V REF 18
Inv. Input 19
N.I. Input 20

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20kΩ, CT = .001mfd, RR = 10kΩ,
CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ.
UC1841 / UC2841 UC3841 UNITS
PARAMETER TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
Power Inputs
Start-Up Current VIN = 30V, Pin 2 = 2.5V 4.5 6 4.5 6 mA
Operating Current VIN = 30V, Pin 2 = 3.5V 10 14 10 14 mA
Supply OV Clamp IIN = 20mA 33 40 45 33 40 45 V
Reference Section
Reference Voltage TJ = 25°C 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation VIN = 8 to 30V 10 15 10 20 mV
Load Regulation IL = 0 to 10mA 10 20 10 30 mV
Temperature Stability Over Operating Temperature Range 4.9 5.1 4.85 5.15 V
Short Circuit Current VREF = 0, TJ = 25°C -80 -100 -80 -100 mA
Oscillator
Nominal Frequency TJ = 25°C 47 50 53 45 50 55 kHz
Voltage Stability VIN = 8 to 30V 0.5 1 0.5 1 %
Temperature Stability Over Operating Temperature Range 45 55 43 57 kHz
Maximum Frequency RT = 2kΩ, CT = 330pF 500 500 kHz

2
 UC1841
UC2841
UC3841
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20kΩ, CT = .001mfd, RR = 10kΩ,
CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ.
PARAMETER TEST CONDITIONS UC1841 / UC2841 UC3841 UNITS
MIN TYP MAX MIN TYP MAX
Ramp Generator
Ramp Current, Minimum ISENSE = -10µA -11 -14 -11 -14 µA
Ramp Current, Maximum ISENSE = 1.0mA -0.9 -.95 -0.9 -.95 mA
Ramp Valley 0.3 0.4 0.6 0.3 0.4 0.6 V
Ramp Peak Clamping Level 3.9 4.2 4.5 3.9 4.2 4.5 V
Error Amplifier
Input Offset Voltage VCM = 5.0V 0.5 5 2 10 mV
Input Bias Current 0.5 2 1 5 µA
Input Offset Current 0.5 0.5 µA
Open Loop Gain ∆VO= 1 to 3V 60 66 60 66 dB
Output Swing (Max. Output ≤ Minimum Total Range 0.3 3.5 0.3 3.5 V
Ramp Peak - 100mV)
CMRR VCM = 1.5 to 5.5V 70 80 70 80 dB
PSRR VIN = 8 to 30V 70 80 70 80 dB
Short Circuit Current VCOMP = 0V -4 -10 -4 -10 mA
Gain Bandwidth* TJ = 25°C, AVOL = 0dB 1 2 1 2 MHz
Slew Rate* TJ = 25°C, AVCL = 0dB 0.8 0.8 V/µs
PWM Section
Continuous Duty Cycle Minimum Total Continuous Range, 4 95 4 95 %
Range* (other than zero) Ramp Peak < 4.2V
50% Duty Cycle Clamp RSENSE to VREF = 10k 42 47 52 42 47 52 %
Output Saturation IOUT = 20mA 0.2 0.4 0.2 0.4 V
IOUT = 200mA 1.7 2.2 1.7 2.2 V
Output Leakage VOUT = 40V 0.1 10 0.1 10 µA
Comparator Delay* Pin 8 to Pin 12, TJ = 25°C, RL = 1kΩ 300 500 300 500 ns
Sequencing Functions
Comparator Thresholds Pins 2, 3, 5 2.8 3.0 3.2 2.8 3.0 3.2 V
Input Bias Current Pins 3, 5 = 0V -1.0 -4.0 -1.0 -4.0 µA
Input Leakage Pins 3, 5 = 10V 0.1 2.0 0.1 2.0 µA
Start/UV Hysteresis Current Pin 2 = 2.5V 170 200 220 170 200 230 µA
Ext. Stop Threshold Pin 4 0.8 1.6 2.4 0.8 1.6 2.4 V
Error Latch Activate Current Pin 4 = 0V, Pin 3 > 3V -120 -200 -120 -200 µA
Driver Bias Saturation Voltage, IB = -50mA 2 3 2 3 V
VIN - VOH
Driver Bias Leakage VB = 0V -0.1 -10 -0.1 -10 µA
Slow-Start Saturation IS = 10mA 0.2 0.5 0.2 0.5 V
Slow-Start Leakage VS = 4.5V 0.1 2.0 0.1 2.0 µA
Current Control
Current Limit Offset 0 5 0 10 mV
Current Shutdown Offset 370 400 430 360 400 440 mV
Input Bias Current Pin 7 = 0V -2 -5 -2 -5 µA
Common Mode Range* -0.4 3.0 -0.4 3.0 V
Current Limit Delay* TJ = 25°C, Pin 7 to 12, RL = 1k 200 400 200 400 ns
* These parameters are guaranteed by design but not 100% tested in production.

3
 UC1841
UC2841
UC3841
FUNCTIONAL DESCRIPTION

PWM CONTROL
1. Oscillator Generates a fixed-frequency internal clock from an external RT and CT.
KC
Frequency = where KC is a first order correction factor ≈ 0.3 log (CT X 1012).
RTCT
2. Ramp Generator
dv sense voltage
Develops a linear ramp with a slope defined externally by =
dt RRCR
CR is normally selected ≤ CT and its value will have some effect upon valley voltage.
Limiting the minimum value for ISENSE will establish a maximum duty cycle clamp.
CR terminal can be used as an input port for current mode control.
3. Error Amplifier Conventional operational amplifier for closed-loop gain and phase compensation.
Low output impedance; unity-gain stable.
The output is held low by the slow start voltage at turn on in order to minimize overshoot.
4. Reference Generator Precision 5.0V for internal and external usage to 50mA.
Tracking 3.0V reference for internal usage only with nominal accuracy of ± 2%.
40V clamp zener for chip OV protection, 100mA maximum current.
5. PWM Comparator Generates output pulse which starts at termination of clock pulse and ends when the ramp
input crosses the lowest of two positive inputs.
6. PWM Latch Terminates the PWM output pulse when set by inputs from either the PWM comparator, the
pulse-by-pulse current limit comparator, or the error latch. Resets with each internal clock
pulse.
7. PWM Output Switch Transistor capable of sinking current to ground which is off during the PWM on-time and turns
on to terminate the power pulse. Current capacity is 400mA saturated with peak
capacitance discharge in excess of one amp.
SEQUENCING FUNCTIONS
1. Start/UV Sense With an increasing voltage, it generates a turn-on signal and releases the slow-start clamp at
a start threshold.
With a decreasing voltage, it generates a turn-off command at a lower level separated by a
200µA hysteresis current.
2. Drive Switch Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until
input voltage reaches start threshold.
3. Driver Bias Supplies drive current to external power switch to provide turn-on bias.
4. Slow Start Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RSCS for slow
increase of output pulse width.
Can also be used as an alternate maximum duty cycle clamp with an external voltage divider.
PROTECTION FUNCTIONS
1. Error Latch When set by momentary input, this latch insures immediate PWM shutdown and hold off until
reset. Inputs to Error Latch are:
a. OV > 3.2V (typically 3V)
b. Stop > 2.4V (typically 1.6V)
c. Current Sense 400mV over threshold (typical).
Error Latch resets when slow start voltage falls to 0.4V if Reset Pin 5 < 2.8V. With Pin 5 >
3.2V, Error Latch will remain set.
2. Current Limiting Differential input comparator terminates individual output pulses each time sense voltage
rises above threshold.
When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to
Error Latch.
3. External Stop A voltage over 1.2V will set the Error Latch and hold the output off.
A voltage less than 0.8V will defeat the error latch and prevent shutdown.
A capacitor here will slow the action of the error latch for transient protection by providing a
typical delay of 13ms/µF.

4
 UC1841
UC2841
UC3841
Start/UV Hysteresis PWM Output-Saturation Voltage

Oscillator Frequency PWM Output Minimum Pulse Width

Error Amplifier Open Loop Gain and Phase Shutdown Timing

5
 UC1841
UC2841
UC3841
OPEN-LOOP TEST CIRCUIT

1  R1 + R2 + R3  Current Limit = 200mV

Nominal Frequency = = 50 kHz UV Fault Voltage = 3   = 8V
 R2 + R3 
RTCT
Current Fault Voltage = 600mV
 R1 + R2 + R3   R1 + R2 + R3  Duty Cycle Clamp = 50%
Start Voltage = 3   +0.2R1 = 12V OV Fault Voltage = 3   = 32V
 R2 + R3   R3 

FLYBACK APPLICATION (A) Not shown, are protective snubbers or additional interface
In this application (see Figure A, next page), complete circuitry which may be required by the choice of the high-
control is maintained on the primary side. Control power voltage switch, Qs, or the application; however, one ex-
is provided by RIN and CIN during start-up, and by a pri- ample of power transistor interfacing is provided on the
mary-referenced low voltage winding, N2, for efficient op- following page.
eration after start. The error amplifier loop is closed to
regulate the DC voltage from N2 with other outputs fol-
REGULATOR APPLICATION (B)
lowing through their magnetic coupling − a task made
even easier with the UC1841’s feed−forward line regula- With the addition of a level shifting transistor, Q1, the
tion. UC1841 is an ideal control circuit for DC to DC converters
such as the buck regulator shown in Figure B opposite. In
An extension to this application for more precise regula- addition to providing constant current drive pulses to the
tion would be the use of the UC1901 Isolated Feedback PIC661 power switch, this circuit has full fault protection
Generator for direct closed-loop control to an output. and high speed dynamic line regulation due to its feed-
forward capability. An additional feature is the ability to

6
 UC1841
UC2841
UC3841

Figure A. UC1841 Programmable PWM Controller In A Simplified Flyback Regulator

Figure B. Overall Schematic For A 300 Watt, Off-line Power Converter Using The UC3841 For Control

7
 UC1841
UC2841
UC3841

ERROR LATCH INTERNAL CIRCUITRY PROGRAMMABLE SOFT START AND

RESTART DELAY CIRCUIT

The Error Latch consists of Q5 and Q6 which, when both on,

turns off the PWM Output and pulls the Slow-Start pin low. This
latch is set by either the Over-Voltage or Current Shutdown
comparators, or by a high signal on Pin 4. Reset is accom-
plished by either the Reset comparator or a low signal on Pin
4. An activation time delay can be provided with an external
capacitor on Pin 4 in conjunction with the ≈ 100µA collector
current from Q4.

CURRENT MODE CONTROL VOLTAGE FEED-FORWARD COMBINED WITH

MAXIMUM DUTY-CYCLE CLAMP

In this circuit, R1 is used in conjunction with CR (not shown) to

establish a minimum ramp charging current such that the ramp
voltage reaches 4.2V at the required maximum output pulse
width.
The purpose of Q1 is to provide an increasing ramp current
above a threshold established by R2 and R3 such that the duty
cycle is further reduced with increasing VIN.
Since Pin 10 is a direct input to the PWM comparator, this
point can also serve as a current sense port for current mode The minimum ramp current is:
control. In this application, current sensing is ground refer- VREF − VIN SENSE 4V
enced through RCS. Resistor R1 sets a 400mV offset across lR(MIN) = ≈
R1 R1
R2 (assuming R2 > RCS) so that both the Error Amplifier and
Fault Shutdown can force the current completely to zero. R2 is The threshold where VIN begins to add extra ramp current is:
also used along with CF as a small filter to attenuate leading-  R2 + R3 
edge spikes on the load current waveform. In this mode, VIN ≈ 5.6V  
current limiting can be accomplished by divider R3/R4 which  R3 
forms a clamp overriding the output of the Error Amplifier. Above the threshold, the ramp current will be:
4 VIN − 5.6 5.6
l R (VARIAB ) ≈ + −
R1 R2 R3

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

8
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UC2841DW ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 85 UC2841DW

UC2841N ACTIVE PDIP N 18 20 RoHS & Green NIPDAU N / A for Pkg Type -20 to 85 UC2841N

UC3841N ACTIVE PDIP N 18 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3841N

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UC2841DW DW SOIC 18 40 507 12.83 5080 6.6
UC2841N N PDIP 18 20 506 13.97 11230 4.32
UC3841N N PDIP 18 20 506 13.97 11230 4.32

Pack Materials-Page 1
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