SN65175, SN75175

QUADRUPLE DIFFERENTIAL LINE RECEIVERS

SLLS145B – OCTOBER 1990 – REVISED MAY 1995

D Meet or Exceed the Requirements of ANSI D OR N PACKAGE

Standard EIA/TIA-422-B, RS-423-B, and (TOP VIEW)
RS-485
D Meet ITU Recommendations V.10, V.11,
1B 1 16 VCC
4B
1A 2 15
X.26, and X.27
4A
D 1Y 3 14
Designed for Multipoint Bus Transmission 4 13 4Y
1, 2EN
on Long Bus Lines in Noisy Environments
2Y 5 12 3, 4EN
D 3-State Outputs 2A 6 11 3Y
D Common-Mode Input Voltage Range 2B 7 10 3A
– 12 V to 12 V GND 8 9 3B
D Input Sensitivity . . . ± 200 mV
D Input Hysteresis . . . 50 mV Typ
D High Input Impedance . . . 12 kΩ Min
D Operate From Single 5-V Supply
D Low-Power Requirements
D Plug-In Replacement for MC3486

description
The SN65175 and SN75175 are monolithic quadruple differential line receivers with 3-state outputs. They are
designed to meet the requirements of ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485, and several ITU
recommendations. These standards are for balanced multipoint bus transmission at rates up to 10 megabits
per second. Each of the two pairs of receivers has a common active-high enable.
The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity
of ± 200 mV over a common-mode input voltage range of ± 12 V. The SN65175 and SN75175 are designed for
optimum performance when used with the SN75172 or SN75174 quadruple differential line drivers.
The SN65175 is characterized for operation from – 40°C to 85°C. The SN75175 is characterized for operation
from 0°C to 70°C.

FUNCTION TABLE
(each receiver)
DIFFERENTIAL OUTPUT
ENABLE
A–B Y
VID ≥ 0.2 V H H
– 0.2 V < VID < 0.2 V H ?
VID ≥ – 0.2 V H L
X L Z
Open circuit H ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

logic symbol† logic diagram (positive logic)

4 4
1, 2EN EN 1, 2EN

2
1A 3 2
1 1Y 1A 3
1B 1 1Y
6 1B
2A 5
7 2Y
2B 6
2A 5
7 2Y
12 2B
3, 4EN EN

10
3A 11
9 3Y 12
3B 3, 4EN
14
4A 13
15 4Y
4B 10
3A 11
9 3Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and 3B
IEC Publication 617-12.
14
4A 13
15 4Y
4B

schematics of inputs and outputs

EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF EACH ENABLE INPUT TYPICAL OF ALL OUTPUTS

VCC VCC VCC

8.3 kΩ 85 Ω
NOM NOM

16.8 kΩ 960 Ω Input

NOM NOM
Input Output
960 Ω
NOM

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 SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage VI, (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Enable input voltage, VI, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: SN65175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
SN75175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING TA = 70°C TA = 85°C
PACKAGE
POWER RATING FACTOR POWER RATING POWER RATING
D 950 mW 7.6 mW/°C 608 mW 494 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Common-mode input voltage, VIC ± 12 V
Differential input voltage, VID ± 12 V
High-level enable-input voltage, VIH 2 V
Low-level enable-input voltage, VIL 0.8 V
High-level output current, IOH – 400 µA
Low-level output current, IOL 16 mA
SN65175 – 40 85
free air temperature,
Operating free-air temperature TA °C
SN75175 0 70

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage and operating free-air temperature
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 16 mA – 0.2‡ V
Vhys Hysteresis voltage (VIT+ – VIT–) See Figure 4 50 mV
VIK Enable-input clamp voltage II = – 18 mA – 1.5 V
VOH High-level output voltage VID = 200 mV, IOH = – 400 µA, See Figure 1 2.7 V
IOL = 8 mA 0.45
VOL Low level output voltage
Low-level mV
VID = – 200 mV, See Figure 1 V
IOL = 16 mA 0.5
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ± 20 µA
VI = 12 V 1
II Line input current Other input at 0 V
V, See Note 3 mA
VI = – 7 V – 0.8
IIH High-level enable-input current VIH = 2.7 V 20 µA
IIL Low-level enable-input current VIL = 0.4 V – 100 µA
ri Input resistance 12 kΩ
IOS Short-circuit output current§ – 15 – 85 mA
ICC Supply current Outputs disabled 70 mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage
levels only.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 3: Refer to ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485 for exact conditions.

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 22 35 ns
See Figure 2
tPHL Propagation delay time, high- to low-level output 25 35 ns
tPZH Output enable time to high level 13 30 ns
See Figure 3
tPZL Output enable time to low level 19 30 ns
tPHZ Output disable time from high level 26 35 ns
See Figure 3
tPLZ Output disable time from low level 25 35 ns

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

VID

VOH S

IOL IOH
VOL (+) (–)
2V

Figure 1. VOH, VOL

Output 3V
Generator
50 Ω Input 1.5 V 1.5 V
(see Note A)
0V
tPLH tPHL
1.5 V CL = 15 pF VOH
(see Note B)
Output 1.3 V 1.3 V
VOL
2V
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf
≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance.

Figure 2. Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

SW1 Output
1.5 V
2 kΩ SW2
–1.5 V 5V

See Note C
CL 5 kΩ
(see Note B)

Generator SW3
(see Note A) 51 Ω

TEST CIRCUIT

3V 3V
Input 1.5 V Input 1.5 V
0V 0V SW1 to –1.5 V
SW1 to 1.5 V
tPZH SW2 Open tPZL SW2 Closed
SW3 Closed SW3 Open
VOH 4.5 V
Output 1.5 V Output 1.5 V
0V VOL
tPZH tPZL

3V 3V 3V
Input 1.5 V Input 1.5 V
0 V SW1 to 1.5 V 0V SW1 to –1.5 V
SW2 Closed tPLZ SW2 Closed
tPHZ SW3 Closed SW3 Closed
VOH 1.4 V
Output 0.5 V Output 0.5 V
1.4 V VOL

tPHZ tPLZ

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tf ≤ 6 ns,
tr ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or equivalent.

Figure 3. Test Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

vs vs
DIFFERENTIAL INPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT
5 5
VCC = 5 V IO = 0 TA = 25°C VID = 0.2 V
4.5 4.5 TA = 25°C

VOH – High-Level Output Voltage – V

4 4
VIC = VIC = VIC =
VO – Output Voltage – V

3.5 –12 V 0 12 V 3.5

3 3
VIT– VIT– VIT– VCC = 5.25 V
2.5 2.5
VCC = 5 V
VIT+ VIT+ VIT+
2 2

1.5 1.5

1 1 VCC = 4.75 V

0.5 0.5

0 0
–125 –100 –75 – 50 – 25 0 25 50 75 100 125 0 – 5 –10 –15 – 20 – 25 – 30 – 35 – 40 – 45 – 50
VID – Differential Input Voltage – mV IOH – High-Level Output Current – mA

Figure 4 Figure 5

HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs
FREE-AIR TEMPERATURE LOW-LEVEL OUTPUT CURRENT
5 0.6
VCC = 5 V VCC = 5 V
4.5 VID = 0.2 V TA = 25°C
IOH = – 400 µA
VOH – High-Level Output Voltage – V

0.5 VID = – 0.2 V

VOL – Low-Level Output Voltage – V

3.5
0.4
3 SN65175 Only

2.5 0.3

2
0.2
1.5

1
0.1
0.5

0 0
0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30
TA – Free-Air Temperature – °C IOL – Low-Level Output Current – mA

Figure 6 Figure 7

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SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs
FREE-AIR TEMPERATURE ENABLE G VOLTAGE
0.5 5
VCC = 5 V VID = 0.2 V
VID = – 0.2 V Load = 8 kΩ to GND
IOL = 8 mA TA = 25°C
VOL – Low-Level Output Voltage – V

0.4 4 VCC = 5.25 V

VO – Output Voltage – V
0.3 VCC = 4.75 V
3
VCC = 5 V

SN65175 Only
0.2 2

0.1 1

0 0
0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3
TA – Free-Air Temperature – °C Enable G Voltage – V
Figure 8 Figure 9

OUTPUT VOLTAGE SUPPLY CURRENT (ALL RECEIVERS)

vs vs
ENABLE G VOLTAGE SUPPLY VOLTAGE
6 100
VCC = 5.25 V VID = –0.2 V No Load
90
Load = 1 kΩ to VCC Inputs Open
5 TA = 25°C
80 TA = 25°C
I CC – Supply Current – mA
VO – Output Voltage – V

VCC = 4.75 V
70 Outputs Disabled
4
VCC = 5 V
60

3 50

40 Outputs Enabled
2
30

20
1
10

0 0
0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 7 8
Enable G Voltage – V VCC – Supply Voltage – V

Figure 10 Figure 11

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 SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995

TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
1
VCC = 5 V
0.75 TA = 25°C

0.5
I I – Input Current – mA
0.25

– 0.25

The Unshaded Area

– 0.5
Conforms to
Figure 3.2 of
– 0.75 EIA RS-485

–1
–8 –6 –4 –2 0 2 4 6 8 10 12
VI – Input Voltage – V

Figure 12

APPLICATION INFORMATION

1/4 SN75172 1/4 SN75174

RT RT

1/4 SN75173 Up to 32 1/4 SN75175

Driver/Receiver
Pairs

1/4 SN75172 1/4 SN75173 1/4 SN75173 1/4 SN75174

NOTE A: The line should be terminated at both ends in its characteristicc impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.

Figure 13. Typical Application Circuit

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