RTUIF-11

Power Supply Bypass Capacitors—Myths and Realities

William B. Kuhn 1, Andrew D. Fund 2
Department of Electrical and Computer Engineering, Kansas State University, USA
1
wkuhn@ksu.edu, 2 andyfund@ksu.edu

Abstract— Power supply bypass capacitors are critical to ground impedance low and the power/signal integrity of
the operation of high-frequency analog and digital circuits, our designs high. This issue has recently gathered
yet are seldom considered in the depth they deserve. This attention, especially when dealing with digital designs [1],
paper investigates their use and the resulting power integrity but must be recognized by IC designers of analog and RF
effects as seen from an RFIC bondpad looking out to a host
circuits as well.
PCB. We show how designs can be either successful or
unsuccessful depending on the capacitor values selected and Unfortunately, at GHz frequencies even the short
the frequencies involved. In particular, the common practice interconnect distance from an IC bondpad through the
of placing two or three graduated-size capacitors in an bondwire and package, onto the board, and through the
attempt to create a broadband AC ground may actually be bypass capacitor and its ground-via can lead to problems.
counterproductive and potentially damaging to circuit
operation. The associated problem of placing partial
bypassing on-chip with larger bypass capacitors off-chip is
also studied and guidance for avoiding hidden dangers is
given.
Index Terms—RFIC, IC, Supply, Bypass, Capacitor,
Power Integrity.

I. INTRODUCTION
As every practicing circuit-designer knows, high-speed
devices require local bypass near each IC to avoid
problems with “noise” on Vdd. In school, we learn to
model Vdd lines as AC grounds and indeed our simulators
implicitly AC ground supply lines due to the underlying
ideal voltage sources to which they are connected. Many
students graduate knowing only this, as popular Fig. 1. Impedance to ground versus frequency for various
electronics textbooks may not even mention bypass interconnect lengths and widths on FR4 PCB.
capacitors outside of the source-to-ground device in
common-source amplifiers. At best, “noise” on a supply As an example, a SOIC packaged die with an off-chip
line is a fabled threat used to justify bypass capacitors and 0402 ceramic capacitor may have a total path length of 0.1
is often linked in the students’ mind to concerns about inches, resulting in 20 to 30 Ohms at 3 GHz. Common
supply-line ripple. In the real-world however, we know wisdom then directs us to consider using a small value
that a voltage source (e.g. regulator output) physically capacitor as close to the package as possible in an attempt
displaced from an IC's supply pin results in significant to exploit series-resonance, with larger values added
interconnect inductance (or transmission-line behaviour in nearby to provide a sufficient "reservoir of charge". The
general). This presents a small, moderate, or even high added larger caps may also be considered to provide
impedance between the IC and the distant supply ground, additional series resonances that “flatten out" the
depending on interconnect length and frequency as impedance dip and provide a broadband ground [2]. The
illustrated in Fig. 1. This impedance produces associated same strategy may be found in microstrip designs of
voltage perturbations if the supply-line current waveform power amps but with the graduated capacitors placed a
contains high frequency Fourier-domain components. quarter wavelength from the amp to create a /4 supply-
Moreover, the operation of the RFIC and system may be line choke [3]. However, as shown as early as 1992 by
compromised by a lack of the assumed low impedance to Paul [4], but insufficiently recognized, the common
ground for the supply node, creating circuit instability, wisdom of paralleling capacitors is (partially) wrong and
lowered gain, and a host of other potential problems. actually creates unintended parallel resonances. As shown
Hence, we recognize that a local supply bypass capacitor in Fig. 2, between the series-resonant impedance dips
is fundamentally needed to keep the supply-line AC there is a peak which can reach several hundred Ohms.

978-1-4799-7642-3/15/$31.00 © 2015 IEEE 405 2015 IEEE Radio Frequency Integrated Circuits Symposium
 the PCB leading back to a regulator and its associated
output bypass capacitor C4. This circuit model produces
the impedance behaviour seen in Fig. 4 depending on the
number of capacitors used and their values.

Fig. 2. Bypass capacitor impedance behaviour for paralleled 100

pF and 0.01 F (after [4], Fig. 7).
Obviously the thousands of products and systems Fig. 3. Model of paralleled capacitors and associated inductively
designed using the conventional wisdom do function and modelled interconnects.
the problem cannot be that bad. Two mitigating factors in
practice are the capacitors’ Q and the PCB material's loss
tangent. Both lead to somewhat subdued peaks as shown
in measurements later in this paper. But impedance
bumps of up to several 10s of Ohms or higher may still
exist. Thus, upon further reflection we realize that
common wisdom leads to a form of electronic-design
inverse-roulette. If our number (frequency of concern)
does not fall into a narrow parallel resonance frequency
range, we have no problem and no reason to change
course. Conversely, if our number does come up, we may
battle issues for weeks and never realize why. This paper
looks at this game in some depth, illuminating the known
(but not widely recognized) parallel resonance problem
discussed in [4, 5]. We then provide guidance on how to Fig. 4. Simulated impedance versus frequency for a) single 1 F
model the problem of bypass circuit impedance to avoid ceramic capacitor, b) three paralleled 1 F ceramic capacitors,
losing the inverse-roulette game, both when bypass is fully and c) graduated size 100pF, 3nF, and 1 F ceramic capacitors.
off-chip and when a combination of on-chip and off-chip All cases include L34 and C4.
capacitance is used (for example, with single-ended GHz-
range RF designs). Example measurements are also Comparing the results, we see that the case of three
provided to demonstrate the degree to which the parallel graduated-size capacitors shows the behaviour of concern
resonance issue occurs in real RFIC bypassing situations. at parallel resonant frequencies, fp, of 25 MHz and 160
MHz, while the single capacitor does not. Interestingly,
the best choice appears to be that of three paralleled 1 F
II. OFF-CHIP BYPASS IMPEDANCE AS SEEN FROM WITHIN capacitors, which provides the benefits of more
THE RFIC capacitance at low frequencies and reduced inductance at
Fig. 3 shows a moderately detailed model for the off- high-frequencies without the hazard created by the
chip bypass case. L0 models the lead inductance from the conventional graduated sizing.
RFIC bondpad to the positive terminal of the closest off- We note of course that none of these cases is sufficient
chip capacitor. C1 is the ideal capacitor model, while L1 for use at GHz frequencies if a good AC ground is needed.
represents it’s series inductance due to its non-zero All cases suffer from the limiting factor of inductive
dimension, together with traces on the board to and impedance in the bondwire/package/board interconnect.
through the ground-plane via. R is its nominal equivalent To address this, one may be forced to consider use of on-
series resistance (ESR). The next capacitor C2 is chip capacitive bypass. However, such a case will
represented by similar modelling, separated from C1 by necessarily result in the return of the parallel resonance
2nH of PCB interconnect (L12) determined from the problem. Understanding this and how fp relates to the
physical distances involved. A third capacitor C3 can be capacitance values chosen can be critical to the success of
considered similarly. Finally, L34 represents a trace on the RFIC/PCB system design.

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 III. CASES INVOLVING TRANSMISSION LINES AND MULTI- frequency dependent losses which were not fully captured
LAYER PCBS in the model. Nevertheless, the destructive nature of the
Fig. 3 and Fig. 4 represent a somewhat simplified case, parallel resonance in the graduated-size capacitor case is
valid for a small two-layer PCB design at lower clearly present, as is the advantage of using either three
frequencies. A somewhat more involved problem will 1 F capacitors, or the lower-cost alternative of a single
need to model transmission-line effects at higher 1 F capacitor. Similar observations were made with the
frequencies and a multi-layer layout with internal power more involved right-hand test structure. Local bypassing
and ground planes. This can be expected to produce more with one 100 pF and one 1 F capacitor to form a
complex behaviour and resonances. For example, if an graduated size “solution” created a strong resonance near
internal power plane caries the supply interconnects and a 300 MHz that is not present when two 1 F capacitors are
star topology from the regulator is employed as used instead. The additional resonances above 1 GHz on
recommended in [6], the inductor L34 should be replaced the 4-layer PCB case are believed to be due to
by a transmission-line model of an appropriate length and transmission-line effects in the complex power-plane
width. The simulation result for a 2 inch, 50 mil wide geometry.
power line replacing L34 is shown in Fig. 5. The results
are similar to the simpler case of Fig. 3 and Fig. 4, but
show additional peaks with the single 1 F bypass case
due to its interaction with the supply-interconnect’s
transmission-line behaviour. Interestingly, the case of
three 1 F capacitors remains relatively stable and is still
the best solution.

Fig. 6. Example test structures measured with 8720 VNA. Left:

coplanar-waveguide (CPW). Right: 4 layer PCB.

Fig. 5. Simulated impedance for cases from Fig. 4, but including

a 2 inch by 50 mil trace to regulator output.

IV. EXPERIMENTAL VALIDATION

To validate the observations from Fig. 4 and Fig. 5, we
used test structures on FR4 PCBs. A co-planar line Fig. 7. Measured impedance for graduated size 100pF, 3nF, and
terminated at its far end with a 1 F capacitor was used as 1 F versus single or triple 1 F ceramic capacitors on Fig. 6 left
shown in Fig. 6 (left) to emulate ideal star-routing from a structure, and for 100pF plus 1 F case versus two 1 F ceramic
regulator. Additional measurements were made with a 4- capacitors on Fig. 6 right structure.
layer PCB that contained the power plane geometries
shown in Fig. 6 (right). The PCB contains a ground-plane V. USE OF ON-AND-OFF-CHIP BYPASS CAPACITORS FOR
flood on the internal layer immediately above the power MICROWAVE FREQUENCY OPERATION
layer and caps were placed on the outer layer(s) in the The parallel resonances seen in the basic case of Fig. 3
positions shown. Measurements were made on an Agilent and Fig. 4 are easily predicted to a first-order by noting
8720 VNA with ground-signal probing for both structures. that once the frequency exceeds the series self-resonance
From measurements on the CPW line (Fig. 7), we note of a capacitor, that capacitor can be considered an inductor
that simulated results qualitatively match the measured defined by its physical length along with the length of its
behaviour, although the resonant frequencies and interconnects. Hence, starting at the right-hand side of Fig.
impedance magnitudes vary. This is expected since the 3, we can collapse C3 and C4 into a single inductance of
model was not fine-tuned to the exact inductances present, 4.9 nH. Ultimately the entire off-chip capacitor array
and because the PCB material and capacitors used have collapses into a single 4.5 nH inductance formed by the

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path from the RFIC bondpad, through the nearest still be large enough to be of concern. If so, they could be
capacitor to ground – in parallel with the remaining moved, possibly by decreasing the on-chip capacitance to
inductances which slightly lower the net L value. It is this a lower 10 pF value (moving fp from 240 MHz to 760
inductance value which will parallel-resonate with the on- MHz). Alternatively, for lower frequency circuits, one
chip bypass capacitance. As an example, if an on-chip may decide to omit the on-chip bypass capacitance
capacitance of 1 pF is used, a parallel resonance at 2.4 entirely and use a single 1 F off-chip capacitor to
GHz would result as shown in the simulation of Fig. 8. implement a low-cost nearly resonance-free solution (but
with increasing impedance versus frequency).

VI. CONCLUSIONS
Power supply bypass capacitors are needed at supply
pins of ICs to provide a low-impedance path to AC ground.
Unfortunately the common practice of paralleling
graduated-size bypass capacitors is found to be one of the
worst solutions possible. This solution introduces
unnecessary parallel resonances, especially when small
values are used. In the case of off-chip-only bypass, the
best solution has been shown to be multiple high-value
ceramics such as three paralleled 1 F capacitors. For
Fig. 8. Simulated impedance as seen from on-chip circuits for
case of 1 pF on-chip high-Q (e.g. MiM) supply bypass capacitor lower cost, even a single 1 F capacitor may outperform
attached to off-chip bypass capacitors modelled as in Fig. 3. the traditional graduated capacitor configuration,
especially for frequencies in the VHF frequency range.
If the intended frequency of operation is 2.4 GHz, this When an on-chip capacitor is considered necessary for
choice of on-chip capacitance is clearly problematic. The GHz frequency ICs, a designer must still pay attention to
solution is to increase the on-chip capacitance to lower the the formation of parallel resonances created by the off-
resonance sufficiently that it does not impact the intended chip interconnect and capacitors acting together with the
frequency. For example, if sufficient on-die real-estate is on-chip bypass. Having a realistic model to predict the
available for 100 pF, the impedance of the supply line as inevitable resonances is critical. This should be done first
seen by on-chip circuits becomes that shown in Fig. 9. Of with calculation and thought to estimate the effects on the
course, the RFIC should be studied to understand if the circuit and system, and then through simulation with
new resonances in the VHF range will be a problem. appropriate inductance or transmission-line models added.
2.5D or 3D EM simulators should also be considered to
verify predictions for complex power plane geometries.

REFERENCES
[1] Masahiro Terasaki, Sho Kiyosige, Wataru Ichimura, Ryota
Kobayashi, Genki Kubo, Hiroki Otsuka, and Toshio Sudo,
"Power Integrity Behavior for Various Packaging
Environments," IEEE 3rd CPMT Symposium Japan (ICSJ),
pp 1-4, 2013.
[2] Tamara Schmitz and Mike Wong, “Choosing and Using
Bypass Capacitors,” Intersil Application Note 1325, Oct 10,
2011.
Fig. 9. Simulated impedance as seen from on-chip circuits for [3] Nitronex, NPT2010 Datasheet application example circuits,
case of 100 pF on-chip high-Q supply bypass capacitor attached NDS-034 Rev. 1, 052413, last accessed Dec 22, 2014 at:
to off-chip bypass capacitors modelled as in Fig. 3. http://cdn.macom.com/datasheets/NDS-
034r1%20NPT2010%20Datasheet.pdf .
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