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MM58248 High Voltage Display Driver

March 1991

MM58248 High Voltage Display Driver

General Description Features
The MM58248 is a monolithic MOS integrated circuit utiliz- Y Direct interface to high voltage display
ing CMOS metal gate low threshold P- and N-channel devic- Y Serial data input
es. It is available both in 40-pin molded dual-in-line pack- Y No external resistors required
ages or as dice. The MM58248 is particularly suited for driv- Y Wide display power supply operation
ing high voltage (60V max) vacuum fluorescent (VF) dis- Y LSTTL compatible inputs
plays (e.g., a 5 x 7 dot matrix display). Y Software compatible with NS display driver family
Y Compatible with alphanumeric or dot matrix displays
Applications Y No load signal required
Y COPSTM or microprocessor-driven display
Y Instrumentation readouts
Y Industrial control indicator
Y Digital clock, thermostat, counter, voltmeter
Y Word processor text displays
Y Automotive dashboards

Block Diagram

TL/F/5599 – 1
FIGURE 1

COPSTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/F/5599 RRD-B30M105/Printed in U. S. A.

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Absolute Maximum Ratings

If Military/Aerospace specified devices are required, Junction Temperature 130§ C
please contact the National Semiconductor Sales Lead Temperature
Office/Distributors for availability and specifications. (Soldering, 10 seconds) 260§ C
Voltage at Any Input Pin VDD a 0.3V to VSS b 0.3V
Voltage at Any Display Pin VDD to VDD b 62.5V Operating Conditions
VDD a lVDISl 62.5V Min Max Units
Supply Voltage (VDD)
Storage Temperature b 65§ C to a 150§ C
VSS e 0V 4.5 5.5 V
Power Dissipation at a 25§ C
Molded DIP Package, Board Mount 2.28W* Display Voltage (VDIS) b 55 b 25 V
Molded DIP Package, Socket Mount 2.05W** Temperature Range b 40 a 85 §C
*Molded DIP Package, Board Mount iJA e 46§ C/W,
Derate 21.7 mW/§ C above a 25§ C.
**Molded DIP Package, Socket Mount, iJA e 51§ C/W,
Derate 19.6 mW/§ C above a 25§ C.

DC Electrical Characteristics
TA e b40§ C to a 85§ C, VDD e 5V g 0.5V, VSS e 0V unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

IDD Power Supply Currents VIN e VSS or VDD, VSS e 0V,
150 mA
VDIS Disconnected
IDIS VDD e 5.5V, VSS e 0V,
10 mA
VDIS e b55V, All Outputs Low
VIL Input Logic Levels
0.8 V
DATA IN, CLOCK Logic ‘0’
VIH Input Logic Levels (Note 1)
2.4 V
DATA IN, CLOCK Logic ‘1’
IIN Input Currents, DATA IN, CLOCK VIN e 0V or VDD b 10 10 mA
CIN Input Capacitance, DATA IN, CLOCK 15 pF
ROFF Display Output Impedances VDD e 5.5V, VSS e 0V
Output Off (Figure 3a) VDIS e b25V 60 400 kX
VDIS e b40V 70 550 kX
VDIS e b55V 80 650 kX
RON Display Output Impedances VDD e 5.5V, VSS e 0V
Output on (Figure 3b) VDIS e b25V 3.0 4.0 kX
VDIS e b40V 2.6 3.7 kX
VDIS e b55V 2.3 3.4 kX
VDOL Display Output VDD e 5.5V, IOUT e Open Circuit,
VDIS VDIS a 4 V
Low Voltage b 55V s VDIS s b 25V
Note 1: 74LSTTL VOH e 2.7V @ IOUT e b 400 mA, TTL VOH e 2.4V @ IOUT e b 400 mA.

AC Electrical Characteristics TA e b40§ C to a 85§ C, VDD e 5V g 0.5V

Symbol Parameter Conditions Min Typ Max Units
fC Clock Input Frequency (Notes 2, 3) 1.0 MHz
tH Clock Input High Time 300 ns
tL Clock Input Low Time 300 ns
tDS Data Input Setup Time CL e 50 pF 100 ns
tDH Data Input Hold Time 100 ns
Note 2: AC input waveform specification for test purposes: tr, tf s 20 ns, f e 1 MHz, 50% g 10% duty cycle.
Note 3: Clock input rise and fall times must not exceed 5 ms.

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Connection Diagrams
Dual-In-Line Package Plastic Chip Carrier

TL/F/5599 – 2
Top View
TL/F/5599 – 8
Order Number MM58248N
See NS Package Number N40A Top View
Order Number MM58248V
See NS Package Number V44A
FIGURE 2

Functional Description
This product is specifically designed to drive multiplexed or In Figure 5, a start bit of logic ‘1’ precedes the 35 bits of
non-multiplexed high voltage alphanumeric or dot matrix data, each bit being accepted on the rising edge of CLOCK,
vacuum fluorescent (VF) displays. Character generation is i.e., a ‘0’ – ‘1’ transition. At the 36th clock, a LOAD signal is
done externally in the microprocessor, with a serial data generated synchronously with the high state of the clock,
path to the display driver. The MM58248 uses two signals, thus loading the 35 bits of the shift register into the latches.
DATA IN and CLOCK, with a format of a leading ‘1’ followed At the low state of the clock, a RESET signal is generated,
by the 35 data bits, hence allowing data transfer without an clearing all bits of the shift register for the next set of data.
additional signal. A block diagram of the MM58248 is shown Hence, a complete set of 36 clock pulses is needed for the
in Figure 1. MM58248, or the shift register will not clear. To clear (reset)
Figure 2 shows the pinout of the MM58248 device, where the display driver at ‘power on’ or any time, the following
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of data flushing routine may be used. Clock in 36 ‘‘zeroes’’, fol-
to be loaded into the shift register following the start bit. A lowed by a ‘‘one’’ (start bit), followed by 35 ‘‘zeroes’’. This
logic ‘1’ at the input will turn on the corresponding display procedure will completely blank the display. It is recom-
digit/segment/dot output. mended to clear the driver at power on.
A significant reduction in discrete board components can be Figure 6 shows a schematic diagram of a microprocessor-
achieved by the use of the MM58248, because external based system where the MM58248 is used to provide the
pull-down resistors are not required. Due to the nature of anode drive for a 32-digit 5 x 7 dot matrix vacuum fluores-
the output stage, both its on and off impedance values vary cent (VF) display. The grid drive in this example is provided
as a function of the display voltage applied. However, Fig- by another member of the high voltage display driver family,
ures 3a and 3b show that this output impedance will remain namely the MM58241, which has the additional features of
constant for a fixed value of display voltage. a BLANKING CONTROL pin, a DATA OUT pin, and an
ENABLE (external load signal) pin.
Figure 4 demonstrates the critical timing requirements be-
tween CLOCK and DATA IN for the MM58248.

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Functional Description (Continued)

TL/F/5599 – 3
FIGURE 3a. Output Impedance Off

TL/F/5599 – 4
FIGURE 3b. Output Impedance On

Timing Diagrams

TL/F/5599 – 5
For the purposes of AC measurement, VIH e 2.4V, VIL e 0.8V.

FIGURE 4. Clock and Data Timings

TL/F/5599 – 6
FIGURE 5. MM58248 Timings (Data Format)

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Typical Applications

TL/F/5599 – 7
FIGURE 6. Microprocessor-Controlled Word Processor

Physical Dimensions inches (millimeters)

Molded Dual-In-Line Package (N)

Order Number MM58248N
NS Package Number N40A

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MM58248 High Voltage Display Driver

Physical Dimensions inches (millimeters) (Continued)

Plastic Chip Carrier (V)

Order Number MM58248V
NS Package Number V44A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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