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CG2027 - Assign4 - Solution

The document provides solutions for an assignment on transistor-level digital circuits, focusing on the propagation delay of ripple-carry and carry-select adders. It details the conditions for achieving worst-case delays in a ripple-carry adder and compares the delays of 16-bit carry-select and ripple-carry adders, concluding that the carry-select adder is faster under certain conditions. Additionally, it calculates the minimum number of bits required for the carry-select adder to outperform the ripple-carry adder, determining that N should be at least 10 or 11 depending on the implementation.

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18 views2 pages

CG2027 - Assign4 - Solution

The document provides solutions for an assignment on transistor-level digital circuits, focusing on the propagation delay of ripple-carry and carry-select adders. It details the conditions for achieving worst-case delays in a ripple-carry adder and compares the delays of 16-bit carry-select and ripple-carry adders, concluding that the carry-select adder is faster under certain conditions. Additionally, it calculates the minimum number of bits required for the carry-select adder to outperform the ripple-carry adder, determining that N should be at least 10 or 11 depending on the implementation.

Uploaded by

tan.jiaqi.0711
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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National University of Singapore

Electrical and Computer Engineering

CG2027 (Transistor-Level Digital Circuits)


Assignment #4 Solution
AY20/21 Semester 2
Issued: Feb. 2, 2021 Due: Feb. 9, 2021 (09:00)

Problem 1: Propagation delay of ripple-carry adder

A0 B0 A1 B1 Ak-1 Bk-1 Ak Bk

Co,0 Co,1 Co,k-1 Co,k


Ci,0 FA FA FA FA
(=Ci,1) (=Ci,2) (=Ci,k)

S0 S1 Sk-1 Sk
Derive the values of Ak and Bk (k=0… N-1) so that the worst case delay is obtained for the ripple-carry
adder shown above.

➔ Observing the figure, the worst case delay occurs when the carry is generated from the Least
Significant Bit (LSB) Co,0, then it ripples through all bit stages, from which finally Co,k is generated.

➔ If we assume Ci,0 is 0, and initial value of SN-1 is 0, A0 and B0 must be 1. All the other stages must
be in propagate mode. Hence, either Ai or Bi must be 1. Since the initial value of SN-1 is 0, we should
also arrange a 0→1 transition in SUM as well. This is achieved by setting both AN-1 and BN-1 to 0 (or
1), which yields a high sum bit given the incoming carry Co,k-1 of 1.

➔ If we assume Ci,0 is 1, then one of (but not both) A0 and B0 must be 1.

➔ For example, {A, B}={ 00000001, 01111111 } is one of such combination. Note any {A, B}
combination that satisfies aforementioned criteria yields the worst case delay.

Problem 2: Ripple carry vs. Carry select adder

(a) Determine the worst-case delay of a 16-bit carry select adder. Assume 𝒕𝒔𝒆𝒕𝒖𝒑 = 𝒕𝒔𝒖𝒎 =
2, and 𝒕𝒄𝒂𝒓𝒓𝒚 = 𝒕𝒎𝒖𝒙 = 1. Compare this with the worst-case delay of a 16-bit ripple carry adder.

➔ From the lecture, we note the delay of an N-bit linear carry-select adder with M-bits per stage is:

, so tadd = 2+M+(16/M)+2 = 4+M+16/M


We also note that the N-bit ripple carry adder is:

, so tadd,ripple-carry = 17.

Comparing both, we can find that under given circumstances, if M ≥ 2, the carry select adder has less
propagation delay than that of the ripple-carry adder.

(b) If each stage has 4 bits, what is minimum number of bits (N) do we need to have, in order for the
carry-select adder to start showing less delay (when compared to a ripple-carry adder)? Assume
𝒕𝒔𝒆𝒕𝒖𝒑 = 𝒕𝒔𝒖𝒎 = 2, and 𝒕𝒄𝒂𝒓𝒓𝒚 = 𝒕𝒎𝒖𝒙 = 1.

➔ From the equations in (a), we let M=4.


Tadd,carry-select = 2+4*1+(N/4)*1+2 = (N/4) + 8
Tadd,ripple-carry = (N-1)*1 + 2 = N + 1
We let Tadd,carry-select ≤ Tadd,ripple-carry. (N/4) + 8 ≤ N+1. Therefore, N≥ 9.3333… . ➔ If N ≥ 10, then
the carry-select adder has less delay. Therefore, N=10.

Note, in an actual adder implementation, in case N is not multiples of M (such as N=10, M=4 shown
above), then the number of muxes in a carry-select adder should be rounded up from (N/M). When we
input N=10 and M=4, we will need 3 muxes; in such case the delay of ripple carry and carry select
adder delay to be 11. Therefore, more accurate answer will be N ≥ 11.

We will consider both N=10 and N=11 as correct answers.

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