National University of Singapore
Electrical and Computer Engineering
CG2027 (Transistor-Level Digital Circuits)
Assignment #5
AY20/21 Semester 2
Issued: Feb. 9, 2021 Due: Feb. 16, 2021 (09:00)
Problem 1: SRAM memory cell
In a SRAM cell shown in Fig. 1, assume all the transistors (M1 – M6) have the same unknown length (L), and
M5, M6 have the width WM5 = WM6= 1μm. Both BL and /BL are precharged to VDD. Assume the on resistance
(Ron) of a PMOS and a NMOS of the same width and length, are identical, Vth,NMOS = |Vth,PMOS| = 0.4(V) and
VDD=1(V).
Figure 1. A SRAM cell
a) If Q = 1 and /Q =0 is currently stored in the SRAM cell, and we would like to read the data so that
BL=1 and /BL=0 when WL is applied with “H”, what should be the requirement (width) of M1 and
M3? Why?
When Q=1 and /Q=0, M2 and M3 are off. When WL= “H” to read the data from the cell, then M5
and M1 form a voltage ladder, where /BL = VDD (precharged). Hence, /Q voltage at this point
𝑅𝑀1
will be given as 𝑉𝐷𝐷 ∗ (𝑅 , and we need to ensure this does NOT exceed the Vth of M3
𝑀5 +𝑅𝑀1 )
(otherwise, M3 will accidently turn on).
𝑅𝑀1 2
Hence 1 ∗ (𝑅 < 0.4, 6𝑅𝑀1 < 4𝑅𝑀5 , therefore, 𝑅𝑀1 < 3 𝑅𝑀5 . Since WM5=1μm, WM1
𝑀5 +𝑅𝑀1 )
must be larger than 3/2 = 1.5μm. Also, WM1 and WM3 should have identical size (both widths
should be larger 1.5 μm).
b) Now that W1 and W3 are determined from a). If Q = 1 and /Q =0 is currently stored in the SRAM cell,
and we would like to write “Q=0, /Q=1” into the cell, then what is the requirement (width) of M2 and
M4?
When Q=1 and /Q=0, M2 and M3 are off. From part a), we sized M1 and M5 so that the /Q will
not exceed 0.4V, so writing /Q= “1” cannot be done by M1 and M5, but rather should be done by
M4-M6 pairs.
When WL= “H” to write data into the cell, then M4 and M6 form a voltage ladder, where BL =
GND (because we are to write “0” into the cell). Hence, Q voltage at this point will be given as
𝑅𝑀6
𝑉𝐷𝐷 ∗ (𝑅 , and we need to ensure this does NOT exceed the Vth of M1 (otherwise, M1 will
𝑀4 +𝑅𝑀6 )
accidently turn on, causing /Q to be pulled down).
𝑅𝑀6 2
Hence, 1 ∗ (𝑅 < 0.4, 6𝑅𝑀6 < 4𝑅𝑀4 , therefore, 𝑅𝑀6 < 3 𝑅𝑀4 . Since WM6=1μm, WM4
𝑀4 +𝑅𝑀6 )
must be smaller than 2/3 μm. Also, WM2 and WM4 should have identical size (both widths should
be smaller than 2/3 μm).
Problem 2: DRAM operation
In a 1T DRAM cell shown in Fig. 2, BL is precharged to VBL = VccA/2 = 1 V, and CS is initially discharged to
GND. Assume CS = 20fF, and CBL=80fF and Vth,M1 = 0.4V. There is NO sense amplifier attached to the BL.
Figure 2. A 1T DRAM cell
(a) When WL is applied with VccA=2V, the access transistor M1 will turn on. At this point, will the final
BL voltage (VFinal) increase or drop, compared with the precharge voltage? By how much (in mV)?
As an analogy, we can think of CBL and CS as large and small water buckets, respectively. Voltage
represents the water level at each bucket. When the M1 is on, the charge from bitline will be
shared with the storage capacitor CS (Which is initially empty), so the voltage level will drop.
Q (charge)= CV, and overall charge of the DRAM cell remains constant (charge conservation).
Therefore, QOverall(Final) = QBL(initial) + QS(initial), where QBL(initial) =CBL *VBL (precharge) and QS (initial) = CS*
VS = 0. Note QOverall(Final) = (CBL+CS)*VFinal.
Hence, (80fF + 20fF) *VFinal = 80fF*1(V) ➔ VFinal=0.8(V), therefore the dropping amount is 1V -
0.8V = 0.2(V).
(b) We now want to write data “1” into CS, by applying BL with VccA=2(V). If we apply WL with VccA
(2V) to initiate the writing operation, is there any potential issue? If so, what is it? How can we avoid
such issue?
Yes, there will be a threshold drop issue from M1. When both BL and WL is applied with 2V, then
the top plate of CS, which is connected to the source of M1, can only reach up to M1’s VGS-Vth= 2
-0.4 = 1.6 (V).
To prevent such voltage drop (and to fully charge the CS to the full VccA), M1’s gate (WL voltage)
needs to have at least Vth,M1 higher than the BL voltage, i.e., 2.0 + 0.4 = 2.4(V) or higher. This
is called bootstrapping of the WL voltage.
