ADS1675

www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

4MSPS, 24-Bit Analog-to-Digital Converter

Check for Samples: ADS1675
1

FEATURES
AC Performance: 103dB of Dynamic Range at 4MSPS 111dB of Dynamic Range at 125kSPS 107dB THD DC Accuracy: 3ppm INL 4mV/C Offset Drift 4ppm/C Gain Drift Programmable Digital Filter with User-Selectable Path: Low-Latency: Completely settles in 2.65ms Wide-Bandwidth: 1.7MHz BW with flat passband Flexible Read-Only Serial Interface: Standard CMOS Serialized LVDS Easy Conversion Control with START Pin Out-of-Range Detection Supply: Analog +5V, Digital +3V Power: 575mW

DESCRIPTION
The ADS1675 is a high-speed, high-precision analog-to-digital converter (ADC). Using an advanced delta-sigma () architecture, it operates at speeds up to 4MSPS with outstanding ac performance and dc accuracy. The ADS1675 ADC is comprised of a low-drift modulator with out-of-range detection and a dual-path programmable digital filter. The dual filter path allows the user to select between two post-processing filters: Low-Latency or Wide-Bandwidth. The Low-Latency filter settles quickly (as fast as 2.65ms) for applications with large instantaneous changes, such as a multiplexer. The Wide-Bandwidth path provides an optimized frequency response for ac measurements with a passband ripple of less than 0.00002dB, stop band attenuation of 86dB, and a bandwidth of 1.7MHz. The device offers two speed modes with distinct interface, resolution, and feature set. In the high-speed mode the device can be set to operate at either 4MSPS or 2MSPS. In the low-speed mode, it can be set to operate at either 1MSPS, 500KSPS, 250KSPS or 125KSPS. The ADS1675 is controlled through I/O pinsthere are no registers to program. A dedicated START pin allows for direct control of conversions: toggle the START pin to begin a conversion, and then retrieve the output data. The flexible serial interface supports data readback with either standard CMOS and LVDS logic levels, allowing the ADS1675 to directly connect to a wide range of microcontrollers, digital signal processors (DSPs), or field-programmable grid arrays (FPGAs). The ADS1675 operates from an analog supply of 5V and digital supply of 3V, and dissipates 575mW of power. When not in use, the PDWN pin can be used to power down all device circuitry. The device is fully specified over the industrial temperature range and is offered in a TQFP-64 package.

APPLICATIONS
Automated Test Equipment Medical Imaging Scientific Instrumentation Test and Measurement
VREFP VREFN CLK AVDD DVDD 3x CMOS and LVDS Compatible Serial Interface Data Ready Data Output Serial Shift Clock Chip Select Interface Configuration Master Clock Filter Path Data Rate Start Conversion Power Down Out-of-Range AGND DGND

PLL

Dual Filter Path AINP AINN DS Modulator Low-Latency Filter Wide-Bandwidth Filter

Control

ADS1675

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
Copyright 20082010, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.
PARAMETER AVDD to AGND DVDD to DGND AGND to DGND Input current Analog I/O to AGND Digital I/O to DGND Maximum junction temperature Operating temperature range Storage temperature range (1) Momentary Continuous ADS1675 0.3 to +5.5 0.3 to +3.6 0.3 to +0.3 100 10 0.3 to AVDD +0.3 0.3 to DVDD +0.3 +150 40 to +85 60 to +150 UNIT V V V mA mA V V C C C

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

ELECTRICAL CHARACTERISTICS
All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
ADS1675 PARAMETER ANALOG INPUTS Full-scale input voltage Common-mode input voltage AC PERFORMANCE Data rate (fDATA) Inputs shorted together, Low-Latency path, fDATA = 4MSPS Dynamic range Inputs shorted together, Low-Latency path, fDATA =2MSPS Inputs shorted together, Low-Latency path, fDATA = 125kSPS fIN = 10kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 4MSPS Signal-to-noise ratio (SNR) fIN = 10kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 2MSPS fIN = 1kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 125kSPS fIN = 10kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 4MSPS Total harmonic distortion (THD) fIN = 10kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 2MSPS fIN = 1kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 125kSPS fIN = 1kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 4MSPS, signal harmonics excluded fIN = 10kHz, 0.5dBFS, Wide-Bandwidth path, fDATA = 4MSPS, signal harmonics excluded Low-speed mode (DRATE = 000 to 011) High-speed mode (DRATE = 100, 101) Low-speed mode (DRATE = 000 to 011) Differential nonlinearity High-speed mode (DRATE = 100, 101) Integral nonlinearity Offset error Offset error drift Gain error Gain error drift Noise Common-mode rejection At dc TA = +25C 4 See Noise Performance table (Table 1) 71 dB TA = +25C 5 4 1 24 23 24 (monotonic) 23 (monotonic) 3 15 5 100 100.5 108 See Table 1 103 103.5 111 92 97 107 103 103 107 120 dB 120 dB dB dB kSPS VIN = (AINP AINN) VCM = (AINP + AINN)/2 VREF 2.5 V V TEST CONDITIONS MIN TYP MAX UNIT

Spurious-free dynamic range (SFDR)

DC PRECISION Resolution Bits Bits Bits Bits ppm of FSR mV mV/C % ppm/C

DIGITAL FILTER CHARACTERISTICS (WIDE-BANDWIDTH PATH) Passband Passband ripple Passband transition Stop band Stop band attenuation Group delay Settling time 0.1dB attenuation 3dB attenuation 0.576fDATA 86 28 See the Wide-Bandwidth Filter section 0.432fDATA 0.488fDATA fCLK 0.576fDATA 0 0.424fDATA 0.00002dB Hz dB Hz Hz Hz dB tDRDY

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
ADS1675 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL FILTER CHARACTERISTICS (LOW-LATENCY PATH) Bandwidth Settling time VOLTAGE REFERENCE INPUTS Reference input voltage (VREF) VREFP VREFN CLOCK (CLK) VIH VIL DIGITAL INPUTS VIH VIL Input leakage CMOS OUTPUTS VOH VOL LVDS OUTPUTS |VOD(SS)| |VOD(SS)| VOC(SS) |VOC(SS)| VOC(pp) Short-circuit output current (IOS) High-impedance output current (IOZ) Load POWER-SUPPLY REQUIREMENTS AVDD DVDD AVDD current DVDD current CMOS outputs, DVDD = 3V, DRATE = 011 LVDS outputs, DVDD = 3V, DRATE = 101 CMOS outputs, DRATE = 011, AVDD = 5V, DVDD = 3V Power dissipation LVDS outputs, DRATE = 101, AVDD = 5V, DVDD = 3V Power-down 4.75 2.85 5.0 3.0 70 53 70 510 575 5 5.25 3.15 74 59 74 545 600 V V mA mA mA mW mW mW Steady-state differential output voltage magnitude Change in steady-state differential output voltage magnitude between logic states Steady-state common-mode voltage output Change in steady-state common-mode output voltage between logic states Peak-to-peak change in common-mode output voltage VOY or VOZ = 0V VOD = 0V VO = 0V or +DVDD 340 50 1.2 50 50 3 3 5 5 150 mV mV V mV mV mA mA mA pF IOH = 2mA IOL = 2mA 0.8DVDD 0.2DVDD V V DGND < VIN < DVDD 0.7DVDD DGND DVDD 0.3DVDD 10 V V mA 0.7AVDD AGND AVDD 0.3AVDD V V VREF = (VREFP VREFN) 2.75 2.75 3.0 3.0 Short to AGND 3.5 3.5 V V V 3dB attenuation Complete settling See the Low-Latency Filter section See Table 5

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

DEVICE INFORMATION
TQFP PACKAGE TQFP-64 (TOP VIEW)
VREFN VREFP VREFN VREFP AGND AGND AGND DGND DGND
50

AVDD

DVDD

64 AVDD AGND AGND AINN AINP AGND AVDD RBIAS AGND 1 2 3 4 5 6 7 8

63

62

61

60

59

58

57

56

55

54

53

52

51

49 48 DVDD 47 DGND 46 DRDY 45 DRDY 44 DOUT 43 DOUT 42 SCLK 41 SCLK

ADS1675
9 40 OTRA 39 OTRD 38 CS 37 START 36 DRATE[0] 35 DRATE[1] 34 DRATE[2] 33 FPATH 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND 10 AVDD 11

AVDD 12 VCM 13 DGND 14 DGND 15 DGND 16

RSV2

DGND

DVDD

RSV1

DGND

DGND

DGND

DVDD

DGND

DGND

DVDD

TERMINAL FUNCTIONS
PIN NAME AVDD AGND AINN AINP RBIAS VCM DGND RSV2 RSV1 DVDD PDWN SCLK_SEL NO. 1, 7, 11, 12, 53, 58 2, 3, 6, 9, 10, 54, 56, 57 4 5 8 13 14-20, 25, 26, 31, 47, 50, 51 21 22 23, 24, 27, 48, 49, 52 28 29 FUNCTION Analog Analog Analog input Analog input Analog Analog Digital Reserved Reserved Digital Digital input Digital input Analog supply Analog ground Negative analog input Positive analog input Analog bias setting resistor Terminal for external bypass capacitor connection to internal common-mode voltage Digital ground Short pin to digital ground Short pin to digital supply Digital supply Power-down control, active low Shift-clock source select. (1) If SCLK_SEL = '0', then SCLK is internally generated. If SCLK_SEL = '1', then SCLK must be externally generated. Serial interface select. (1) If LVDS = '0', then interface is LVDS-compatible. If LVDS = '1', then interface is CMOS-compatible. DESCRIPTION

LVDS

30

Digital input

(1)

Option not available in high-speed mode. Submit Documentation Feedback Product Folder Link(s): ADS1675 5

Copyright 20082010, Texas Instruments Incorporated

LL_CONFIG

LVDS

SCLK _SEL

PDWN

DGND

DVDD

CAP1

CLK

AVDD

CAP2

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

TERMINAL FUNCTIONS (continued)

PIN NAME LL_CONFIG NO. 32 FUNCTION Digital input DESCRIPTION Configure Low-Latency digital filter. (1) If LL_CONFIG = '0', then single-cycle settling is selected. If LL_CONFIG = '1', then fast-response is selected. Digital filter path selection. If FPATH = '0', then path is Wide-Bandwidth. If FPATH = '1', then path is Low-Latency. Data rate selection Start convert, reset, and synchronization control input Chip select; active low Digital filter out-of-range indicator Analog input out-of-range indicator Negative shift clock output. If SCLK_SEL = '0', then SCLK is the complementary shift clock output. If SCLK_SEL = '1', then SCLK always output is 3-state. Positive shift clock output. If SCLK_SEL = '0', then SCLK is an output. If SCLK_SEL = '1', then SCLK is an input. Negative LVDS serial data output Positive LVDS serial data output Negative data ready output Positive data ready output Master clock input Terminal for 1mF external bypass capacitor Negative reference voltage. Short to analog ground Terminal for 1mF external bypass capacitor Positive reference voltage

FPATH DRATE[2:0] START CS OTRD OTRA SCLK

33 34-36 37 38 39 40 41

Digital input Digital input Digital input Digital input Digital output Digital input Digital output

SCLK DOUT DOUT DRDY DRDY CLK CAP1 VREFN CAP2 VREFP

42 43 44 45 46 55 59 60, 61 62 63, 64

Digital input/output Digital output Digital output Digital output Digital output Digital input Analog Analog Analog Analog

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

TIMING CHARACTERISTICS
tLSCLK SCLK tLDRPW DRDY tLSCLKDR tLDOPD DOUT MSB LSB MSB tLSCLKDC

(1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101. (2) Timing shown is the single-end version of the LVDS signal pairs.

Figure 1. High-Speed LVDS Data Retrieval Timing

TIMING REQUIREMENTS: High-Speed LVDS

At TA = 40C to +85C, and DVDD = 2.85V to 3.15V.
SYMBOL tLDRPW tLSCLKDR tLDOPD tLSCLK tLSCLKDC tCLK tLCLKSCLK tLPLLSTL tSTCLK tSETTLE DRDY pulse width SCLK to DRDY delay Valid data delay time from serial shift clock Period of LVDS serial shift clock (SCLK) Shift clock duty cycle CLK period (1/fCLK) Delay from rising edge of CLK to rising edge of SCLK PLL settling time Setup time, rising edge of START to falling edge of CLK Digital filter settling time
tCLK CLK tLPLLSTL SCLK tSETTLE START tSETTLE DRDY tLSCLKDR tSTCLK tLCLKSCLK tLSCLK

DESCRIPTION

MIN 2 2 1.5

TYP

MAX 4 3 2.5

UNIT tLSCLKs ns ns tCLKs % ns ns ms ns

0.33 47 31.25 13 3 20 80 3 53

See Table 5 and Table 6

Figure 2. PLL Timing

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
tCLK tDC

www.ti.com

CLK tLCLKDR DRDY tLDRPW

CS tLSCLK tDRSCLK SCLKinternal tLDOPD DOUT MSB LSB tSPWH

Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)

TIMING REQUIREMENTS: Internal SCLK

At TA = 40C to +85C, and DVDD = 2.85V to 3.15V.
SYMBOL tDC tSPWH tCLK tCLKDR tLDRPW tDRSCLK tLSCLK tLDOPD CLK duty cycle SCLK pulse width high CLK period (1/fCLK) CLK to DRDY delay DRDY pulse width Internal SCLK Rising to DRDY active edge Internally-generated SCLK rising edge to DRDY rising edge Rising edge of SCLK to new valid data output (propagation delay) 1.9 2.2 1 2.8 31.25 23 1 4.4 30 DESCRIPTION MIN 47 TYP 50 15.6 MAX 53 UNIT % ns ns ns tCLK ns tCLK ns

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com
tCLK CLK tCLKDR DRDY tLDRPW CS
(1)

SBAS416D DECEMBER 2008 REVISED AUGUST 2010

tLSCLKDR

tCSSC SCLKEXTERNAL tLDOPD DOUT Hi-Z tCSFDO MSB

tSPW

tSPW

tLSCLK tCSRDO LSB

(3)

CS may be tied low.

Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1)

TIMING REQUIREMENTS: External SCLK

At TA = 40C to +85C, and DVDD = 2.85V to 3.15V.
SYMBOL tCLK tCLKDR tLDRPW tCSSC tLSCLK tSPW tLDOPD tLSCLKDR tCSRDO CLK period (1/fCLK) CLK to DRDY delay DRDY pulse width CS active low to first Shift Clock (setup time) SCLK period (1/fSCLK) SCLK high or low pulse width Rising edge of SCLK to new valid data output (propagation delay) Setup time of DRDY rising after SCLK falling edge CS rising edge to DOUT 3-state
tSTART_CLKR CLK tSETTLE START tSTART DRDY tCLKDR

DESCRIPTION

MIN 31.25 23

TYP

MAX

UNIT ns

29 1

ns tCLK ns ns ns

5 25 12 10.5 3 8 15

ns tCLK ns

Figure 5. START Timing

TIMING REQUIREMENTS: START

At TA = 40C to +85C, and DVDD = 2.85V to 3.15V.
SYMBOL tSTART_CLKR tSTART DESCRIPTION Setup time, rising edge of START to rising edge of CLK Start pulse width MIN 0.5 2 TYP MAX UNIT tCLK tCLK

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

TYPICAL CHARACTERISTICS
All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
SPECTRAL RESPONSE (DRATE = 000, WB Filter)
0 -20 fIN = 1kHz, -0.5dBFS THD = -106.8dBc 65,536 Points 0 -20

SPECTRAL RESPONSE (DRATE = 000, WB Filter)

fIN = 1kHz, -6dBFS THD = -106.7dBc 65,536 Points

Amplitude (dBFS)

-60 -80 -100 -120 -140 -160 0 10 20 30 Frequency (kHz) 40 50 60

Amplitude (dBFS)

-40

-40 -60 -80 -100 -120 -140 -160 0 10 20 30 Frequency (kHz) 40 50 60

Figure 6. SPECTRAL RESPONSE (DRATE = 100, WB Filter)

0 -20 fIN = 10kHz, -0.5dBFS THD = -103dBc 65,536 Points
Amplitude (dBFS)
0 -20 -40 -60 -80 -100 -120 -140 -160

Figure 7. SPECTRAL RESPONSE (DRATE = 100, WB Filter)

fIN = 10kHz, -6dBFS THD = -109dBc 65,536 Points

Amplitude (dBFS)

-40 -60 -80 -100 -120 -140 -160 0

100 200 300 400 500 600 700 800 900 1000 Frequency (kHz)

20

40

60

80

100 120 140 160 180

200

Frequency (kHz)

Figure 8. SPECTRAL RESPONSE (DRATE = 101, WB Filter)

0 -20 fIN = 10kHz, -0.5dBFS THD = -102.7dBc 65,536 Points
Amplitude (dBFS)
0 -20 -40 -60 -80 -100 -120 -140 -160

Figure 9. SPECTRAL RESPONSE (DRATE = 101, WB Filter, Detailed View)

fIN = 10kHz, -0.5dBFS THD = -102.7dBc 65,536 Points

Amplitude (dBFS)

-40 -60 -80 -100 -120 -140 -160 0

200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (kHz)

20

40

60

80

100 120 140 160 180

200

Frequency (kHz)

Figure 10.

Figure 11.

10

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

TYPICAL CHARACTERISTICS (continued)

All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
SPECTRAL RESPONSE (DRATE = 101, WB Filter, Detailed View)
0 -20 fIN = 10kHz, -6dBFS THD = -109dBc 65,536 Points 0 -20 fIN = 10kHz, -60dBFS THD = -62.7dBc 65,536 Points

SPECTRAL RESPONSE (DRATE = 101, WB Filter, Detailed View)

Amplitude (dBFS)

-60 -80 -100 -120 -140 -160 0 20 40 60 80 100 120 140 160 180 200 Frequency (kHz)

Amplitude (dBFS)

-40

-40 -60 -80 -100 -120 -140 -160 0 20 40 60 80

100 120 140 160 180

200

Frequency (kHz)

Figure 12. SPECTRAL RESPONSE (DRATE = 101, LL Filter)

0 -20 -40 fIN = 10kHz, -0.5dBFS THD = -102.7dBc 65,536 Points
Amplitude (dBFS)
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200

Figure 13. SPECTRAL RESPONSE (DRATE = 101, LL Filter, Detailed View)

fIN = 10kHz, -0.5dBFS THD = -102.7dBc 65,536 Points

Amplitude (dBFS)

-60 -80 -100 -120 -140 -160 -180 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (kHz)

20

40

60

80

100 120 140 160 180

200

Frequency (kHz)

Figure 14. SPECTRAL RESPONSE (DRATE = 101, LL Filter, Detailed View)

0 -20 -40 fIN = 10kHz, -5.9dBFS THD = -107.8dBc 65,536 Points 0 -20

Figure 15. SPECTRAL RESPONSE (DRATE = 101, WB Filter)

fIN = 100kHz, -0.5dBFS THD = -102.4dBc 65,536 Points

Amplitude (dBFS)

-60 -80 -100 -120 -140 -160 -180 -200 0 20 40 60 80 100 120 140 160 180 200 Frequency (kHz)

Amplitude (dBFS)

-40 -60 -80 -100 -120 -140 -160 0

200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M Frequency (Hz)

2M

Figure 16.

Figure 17.

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

11

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
SPECTRAL RESPONSE (DRATE = 101, WB Filter)
0 -20 fIN = 100kHz, -6dBFS THD = -103.2dBc 65,536 Points 0 -20

SPECTRAL RESPONSE (DRATE = 101, WB Filter)

fIN = 1600kHz, -0.5dBFS THD = -122.9dBc 65,536 Points

Amplitude (dBFS)

-60 -80 -100 -120 -140 -160 0 200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M Frequency (Hz) 2M

Amplitude (dBFS)

-40

-40 -60 -80 -100 -120 -140 -160 0 200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M Frequency (Hz) 2M

Figure 18. SPECTRAL RESPONSE (DRATE = 101, WB Filter)

0 -20 fIN = 1600kHz, -6dBFS THD = -125dBc 65,536 Points

Figure 19. SIGNAL-TO-NOISE RATIO vs INPUT SIGNAL AMPLITUDE

100 90 80 fIN = 10kHz

Amplitude (dBFS)

-40

SNR (dBc)

-60 -80 -100 -120 -140 -160 0 200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M Frequency (Hz) 2M

70 60 50 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Signal Amplitude (dBFS) fDATA = 2MSPS, WB fDATA = 4MSPS, WB

Figure 20. |TOTAL HARMONIC DISTORTION| vs INPUT SIGNAL AMPLITUDE

120 110 100 fIN = 10kHz
95 94 93 92

Figure 21. SIGNAL-TO-NOISE RATIO vs INPUT COMMON-MODE VOLTAGE

fIN = 10kHz fDATA = 4MSPS WB Filter

AIN = -0.5dBFS

|THD| (dBc)

SNR (dBc)

90 fDATA = 2MSPS, WB 80 70 60 50 40 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Signal Amplitude (dBFS) fDATA = 4MSPS, WB

91 90 89 88 87 86 85 1.5 2.0 2.5 3.0 3.5 Input Common-Mode Voltage (V) AIN = -6dBFS

Figure 22.

Figure 23.

12

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

TYPICAL CHARACTERISTICS (continued)

All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
|TOTAL HARMONIC DISTORTION| vs INPUT COMMON-MODE VOLTAGE
115 fIN = 10kHz fDATA = 4MSPS WB Filter
SNR (dBc)
93.0 92.5 92.0 91.5 fCLK = 8MHz

SIGNAL-TO-NOISE RATIO vs RBIAS

110

|THD| (dBc)

AIN = -6dBFS 105

91.0 90.5 90.0 89.5 89.0 fCLK = 32MHz

fCLK = 16MHz

100 AIN = -0.5dBFS 95 1.5 2.0 2.5 3.0 3.5 Input Common-Mode Voltage (V)

88.5 88.0 0 10 20 30 RBIAS (kW) 40

fIN = 10kHz AIN = -0.5dBFS 50 60

Figure 24. |TOTAL HARMONIC DISTORTION| vs RBIAS

114 112 110 108 106 104 102 100 98 96 94 0 10 20 30 RBIAS (kW) 40 50 60 fCLK = 32MHz fCLK = 16MHz fCLK = 8MHz fIN = 10kHz AIN = -0.5dBFS 1100 1000 900 800

Figure 25. POWER vs RBIAS

fIN = 10kHz AIN = -0.5dBFS

Power (mW)

|THD| (dBc)

700 600 500 400 300 200 100 0 10 fCLK = 8MHz 20 30 RBIAS (kW) 40 50 60 fCLK = 16MHz fCLK = 32MHz

Figure 26. SIGNAL-TO-NOISE RATIO AND |TOTAL HARMONIC DISTORTION| vs TEMPERATURE

105
112 110

Figure 27.

DYNAMIC RANGE vs OVERSAMPLING RATIO

Dynamic Range (dBFS)

|THD|

108 106 104 102 100 98 96 94

LL Filter WB Filter Input Shorted fCLK = 32MHz 125kSPS: DRATE = 000 250kSPS: DRATE = 001 500kSPS: DRATE = 010 1MSPS: DRATE = 011 2MSPS: DRATE = 100 4MSPS: DRATE = 101 8 16 32 64 128 Oversampling Ratio 256

SNR, |THD| (dBc)

100 fIN = 10kHz AIN = -0.5dBFS fDATA = 4MSPS WB Filter SNR 90 -40 -15 10 35 60 85 Temperature (C)

95

92

Figure 28.

Figure 29.

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

13

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless otherwise noted.
CURRENT vs OVERSAMPLING RATIO
100 90 Input Shorted fCLK = 32MHz LVDS Interface 125kSPS: DRATE = 000 250kSPS: DRATE = 001 500kSPS: DRATE = 010 1MSPS: DRATE = 011 2MSPS: DRATE = 100 4MSPS: DRATE = 101
590 580 570 560

POWER vs OVERSAMPLING RATIO

Input Shorted fCLK = 32MHz LVDS Interface 125kSPS: DRATE = 000 250kSPS: DRATE = 001 500kSPS: DRATE = 010 1MSPS: DRATE = 011 2MSPS: DRATE = 100 4MSPS: DRATE = 101

Current (mA)

Power (mW)

80 IAVDD, WB/LL Filter 70 60 50 40 8 16 32 64 128

550 540 530 520 LL Filter

IDVDD, LL Filter IDVDD, WB Filter 256

510 500 490 8 16 32 64 128

WB Filter

256

Oversampling Ratio

Oversampling Ratio

Figure 30. NOISE HISTOGRAM (DRATE = 101, WB Filter)

600 500 Input Shorted s = 60LSB 65,536 Points Wide Bandwidth fDATA = 4MSPS

Figure 31. NOISE HISTOGRAM (DRATE = 000, WB Filter)

1600 1400 Input Shorted s = 17LSB 65,536 Points Wide Bandwidth fDATA = 125kSPS

Number of Occurrences

Number of Occurences

1200 1000 800 600 400 200 0

400 300 200 100

0 -400

-300

-200

-100

100

200

300

400

-80

-60

-40

-20

20

40

60

80

23-Bit Output Code (LSB)

24-Bit Output Code (LSB)

Figure 32. INTEGRAL NONLINEARITY vs ANALOG INPUT VOLTAGE

3 2 1 +25C +85C -40C

Figure 33.

INL (ppm)

0 -1 -2 -3 -3 -2 -1 0 1 2 3 Analog Input Voltage (V) fCLK = 32MHz fDATA = 125kSPS Wide Bandwidth

Figure 34.

14

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

OVERVIEW
The ADS1675 is a 24-bit, delta-sigma () analog-to-digital converter (ADC). It provides high-resolution measurements of both ac and dc signals and features an advanced, multi-stage analog modulator with a programmable and flexible digital decimation filter. Figure 35 shows a block diagram of the ADS1675. The modulator measures the differential input signal VIN = (AINP AINN) against the differential reference VREF = (VREFP VREFN). The digital filter receives the modulator signal and processes it through the user-selected path. The Low-Latency path settles quickly, and is ideal when using a multiplexer or when measuring large transients. The Wide-Bandwidth path provides outstanding frequency response with very low passband ripple, a steep transition band, and large stop band attenuation. This path is well-suited for applications that require high-resolution measurements of high-frequency ac signal content. A dedicated START pin allows precise conversion control; toggle the pin to begin the conversion process. The ADS1675 is configured by setting the appropriate I/O pinsthere are no registers to program. Data are retrieved over a serial interface that can support either CMOS or LVDS voltage levels. In addition, the standard CMOS serial interface can be internally or externally clocked. This flexibility allows direct connection to a wide range of digital hosts including DSPs, FPGAs, and microcontrollers. All data rates are available only using the LVDS mode interface. A detection circuit monitors the conversions to indicate when the inputs are out-of-range for an extended duration. A power-down pin (PDWN) shuts off all circuitry when the ADS1675 is not in use. The device offers two speed modes with distinct interfaces, resolution, and feature set. The high-speed mode is enabled by setting DRATE[2:0] to either 100 or 101. The rest of the DRATE configurations enable the low-speed mode.
DVDD AVDD

RBIAS

CAP1

CAP2

VREFN

VREFP

CLK

PLL

3x

ADS1675

PDWN START

VCM

Biasing

S
VREF DS Modulator

Dual Filter Path Low-Latency Filter Wide-Bandwidth Filter

CLK CMOS- and LVDSCompatible Serial Interface and Control DRDY, DRDY DOUT, DOUT SCLK, SCLK CS LVDS SCLK_SEL DRATE[2:0] FPATH LL_CONFIG OTRD OTRA

AINP AINN

VIN

AGND

Figure 35. Block Diagram

DGND

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

15

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

NOISE PERFORMANCE
The ADS1675 offers outstanding noise performance that can be optimized by adjusting the data rate. As the averaging is increased (thus reducing the data rate), the noise drops correspondingly. Table 1 shows the noise as a function of data rate for both the Low-Latency and the Wide-Bandwidth filter paths under the conditions shown. Table 1 lists some of the more common methods of specifying noise. The dynamic range is the ratio of the root-mean-square (RMS) value of a full-scale sine wave to the RMS noise with the inputs shorted together. This value is expressed in decibels relative to full-scale (dBFS). The input-referred noise is the RMS value of the noise with the inputs shorted, referred to the input of the ADS1675. The effective number of bits (ENOB) is calculated from a dc perspective using the formula in Equation 1, where full-scale range equals 2VREF.
ln ENOB = ln(2) Full-scale range RMS noise

Noise-free bits specifies noise, again from a dc perspective using Equation 1, with peak-to-peak noise substituted for RMS noise.

ANALOG INPUTS (AINP, AINN)

The ADS1675 measures the differential signal, VIN = (AINP AINN), against the differential reference, VREF = (VREFP VREFN). The most positive measurable differential input is VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is VREF, which produces the most negative digital output code of 800000h. Analog inputs must be driven with a differential signal to achieve optimum performance. The recommended common-mode voltage is 2.5V. The ADS1675 samples the analog inputs at very high speeds. It is critical that a suitable driver be used. See the Application Information section for recommended circuit designs.

(1)

Table 1. Noise Performance (1)

DATA RATE (kSPS) 125 250 500 1000 2000 4000 125 250 500 1000 2000 4000 DYNAMIC RANGE (dB) 111 109 107 105 104 103 111 109 107 104 101 94 INPUTREFERRED NOISE (mVRMS) 6.30 7.47 9.51 11.72 13.72 14.23 6.17 7.44 9.66 12.99 18.64 44.02 NOISE-FREE BITS 17.14 16.89 16.54 16.24 16.02 15.96 17.17 16.90 16.52 16.09 15.57 14.33

FILTER PATH

DATA RATE[2:0] 000 001 010 011 High-speed modes 100 101 000 Low-speed modes 001 010 011 High-speed modes 100 101

ENOB 19.86 19.61 19.27 18.97 18.74 18.69 19.89 19.62 19.25 18.82 18.30 17.06

Low-Latency (Fast Response Mode configuration)

Low-speed modes

Wide-Bandwidth

(1)

VREF = 3V, fCLK = 32MHz.

16

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

VOLTAGE REFERENCE INPUTS (VREFN, VREFP)

The voltage reference for the ADS1675 is the differential voltage between VREFP and VREFN:
VREF = (VREFP VREFN) (2)

CONVERSION START
The START pin provides an easy and precise conversion control. To perform a single conversion, pulse the START pin as shown in Figure 36. The START signal is latched internally on the rising edge of CLK. Multiple conversions are performed by continuing to hold START high after the first conversion completes; see the digital filter descriptions for more details on multiple conversions, because the timing depends on the filter path selected. A conversion can be interrupted by issuing another START pulse before the ongoing conversion completes. When an interruption occurs, the data for the ongoing conversion are flushed and a new conversion begins. DRDY indicates that data are ready for retrieval after the filter has settled, as shown in Figure 37.

A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1675. Noise and drift on the reference degrade overall system performance. See the Application Information section for reference circuit examples. It is recommended that a minimum 10mF and 0.1mF ceramic bypass capacitors be used directly across the reference inputs, VREFP and VREFN. These capacitors should be placed as close as possible to the device under test for optimal performance.

COMMON-MODE VOLTAGE (VCM)

The VCM pin outputs a voltage of AVDD/2. This pin must be bypassed with a 1F capacitor placed close to the package pin. The VCM pin connects an external capacitor to compensate the internal amplifier; it is not intended to drive an external load.
tSTART_CLKR CLK
(1)

tSETTLE START tSTART DRDY

tSETTLE

(1)

Figure 36. START Pin Used for Single Conversions

Ongoing conversion flushed; new conversion started tSTART_CLKR CLK
(1)

tSETTLE START tSTART DRDY

(1) See the Low-Latency Filter and Wide-Bandwidth Filter sections for specific values of settling time tSETTLE.

Figure 37. Example of Restarting a Conversion with START

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

17

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

DIGITAL FILTER
In ADCs, the digital filter has a critical influence on device performance. The digital filter sets the frequency response, data rate, bandwidth, and settling time. Choosing to optimize some of these features in a filter means that compromises must be made with other specifications. These tradeoffs determine the applications for which the device is best suited. The ADS1675 offers two digital filters on-chip, and allows the user to direct the output data from the modulator to either the Wide-Bandwidth or Low-Latency filter. These filters allow the user to use one converter design to address multiple applications. The Low-Latency path filter has minimal latency or settling time. This reduction is achieved by reducing the bandwidth of the filter. This path is ideal for measurements with large, quick changes on the inputs (for example, when using a multiplexer). The Low-Latency characteristic allows the user to cycle through the multiplexer at high speeds. The other path provides a filter with excellent frequency response characteristics. The passband ripple is extremely small, the transition band is very steep, and there is large stop band attenuation. These characteristics are needed for high-resolution measurements of ac signals. The tradeoff here is that settling time increases; for signal processing, however, this increase is not generally a critical concern. The FPATH digital input pin sets the filter path selection, as shown in Table 2. Note that the START pin must be strobed after a change to the filter path selection or data rate. If a conversion is in process during a filter path or data rate change, the output data are not valid and should be discarded. Table 2. ADS1675 Filter Path Selection
FPATH PIN 1 0 SELECTED FILTER PATH Low-Latency path Wide-Bandwidth path

LOW-LATENCY DIGITAL FILTER

The Low-Latency (LL) filter provides a fast settling response targeted for applications that need high-precision measurements with minimal latency. A good example of this type of application is a multiplexer that measures multiple inputs. The faster the ADC settles, the faster the measurement can complete and the multiplexer can advance to the next input. The ADS1675 LL filter supports two configurations to help optimize performance for these types of applications. The LL_CONFIG input pin selects the configuration, as shown in Table 3. Be sure to strobe the START pin after changing the configuration. If a conversion is in process during a configuration change, the output data for that conversion are not valid and should be discarded. Table 3. Low-Latency Pin Configurations
LL_CONFIG PIN 0 1 LOW-LATENCY CONFIGURATION Single-cycle settling Fast response

The first configuration is single-cycle settling. As the name implies, this configuration allows for the filter to completely settle in one conversion cycle; there is no need to discard data. Each data output is comprised of information taken during only the previous conversion. The DRATE[2:0] digital input pins select the data rate for the Single-Cycle Settling configuration, as shown in Table 4. Note that the START pin must be strobed after a change to the data rate. If a conversion is in process during a data rate change, the output data for that conversion are not valid and should be discarded. blank blank

Table 4. Low-Latency Data Rates with Single-Cycle Settling Configuration

DRATE[2:0] 000 001 010 011 (1) DATA RATE (kSPS) 57.80 107.53 188.68 277.78 SETTLING TIME, tSETTLE-LL 17.375ms 9.375ms 5.375ms 3.625ms 556tCLK 300tCLK 172tCLK 116tCLK 3dB BANDWIDTH (kHz) (1) 54 109 208 344

The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem.

18

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

The second configuration is fast response. The DRATE[2:0] digital input pins select the data rate for the Fast Response Configuration, as shown in Table 5. When selected, this configuration provides a higher output data rate. The faster output data rate allows for more averaging by a post-processor within a given time interval to reduce noise. It also provides a faster indication of changes on the inputs when monitoring quickly-changing signals (for example, in a control loop application). Table 5. Low-Latency Data Rates with Fast-Response Configuration
DRATE [2:0] 000 001 010 011 100 101 DATA RATE (kSPS) 125 250 500 1000 2000 4000 SETTLING TIME, tSETTLE-LL 17.375ms 9.375ms 5.375ms 3.625ms 2.76ms 2.385ms 556tCLK 300tCLK 172tCLK 116tCLK 265tLSCLK 229tLSCLK 3dB BANDWIDTH (kHz) 54 109 208 344 350 355

Settling Time The settling time in absolute time (ms) is the same for both configurations of the Low-Latency filter, as shown in Table 4 and Table 5. The difference between the configurations is seen with the timing of the conversions after the filter has settled from a pulse on the START pin. Figure 38 illustrates the response of both configurations on approximately the same time scale in order to highlight the differences. With the single-cycle settling configuration, each conversion fully settles; in other words, the conversion period tDRDY-SCS = tSETTLE-LL. The benefit of this configuration is its simplicitythe ADS1675 functions similar to a successive-approximation register (SAR) converter and there is no need to consider discarding partially-settled data because each conversion is fully settled. With the fast response configuration, the data rate for conversions after initial settling is faster; that is, the conversion time is less than the settling: tDRDY-FR < tSETTLE-LL. One benefit of this configuration is a faster response to changes on the inputs, because data are supplied at a faster rate. Another advantage is better support for post-processing. For example, if multiple readings are averaged to reduce noise, the higher data rate of the fast response configuration allows this averaging to happen in less time than it requires with the single-cycle settling filter. A third benefit is the ability to measure higher input frequencies without aliasing as a result of the higher data rate.

1. The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem. 2. For high-speed mode, the first data are unsettled.

tSTART_CLKR CLK tSETTLE-LL tCLKDR START

tDRDY-SCS = tCLKDR + 1tCLK + tSETTLE-LL

DRDYSCS

DRDYFR

tDRDY-FR

NOTE: DRDYSCS is the DRDY output with the Low-Latency single-cycle settling configuration. DRDYFR is the DRDY output with the Low-Latency fast-response settling configuration.

Figure 38. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

19

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com
0 -10 -20

It is important to note, however, that the absolute settling time of the Low-Latency path does not change when using the fast response configuration. Changes on the input signal during conversions after the initial settling require multiple cycles to fully settle. To help illustrate this requirement, consider a change on the inputs as shown in Figure 42, where START is assumed to have been taken high before the input voltage was changed. The readings after a step change in the input is settled as shown in Figure 39 for all different data rates.
1.4 1.2 1.0 DRATE = 000, 001, 010 DRATE = 011

DRATE = 000

Magnitude (dB)

-30 DRATE = 011 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Normalized Frequency (fIN/fDATA) 0.9 1.0 DRATE = 101 DRATE = 100

DRATE = 100

Figure 40. Frequency Response of Low-Latency Filter in Fast-Response Configuration

DRATE = 101 0 -20

Settling (%)

0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 Conversions (1/fDRDY-FR)

Magnitude (dB)

-40 -60 -80 -100 -120 -140 0 0.5 1.0 1.5 2.0 2.5 3.0

Figure 39. Step Response for Low-Latency Filter with Fast-Response Configuration Frequency Response Figure 40 shows the frequency response for the Low-Latency filter path normalized to the output data rate, fDATA. The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency. Figure 41 shows the response with the fastest data rate selected (4 MSPS when fCLK = 32MHz).
Change on Analog Inputs

Normalized Frequency (fIN/fCLK)

Figure 41. Extended Frequency Response of Low-Latency Path

VIN

Fully-Settled Data Available for DRATE = 000 , 001, 010 Data 0 Data 1 Data 2 Data 3 Data 4
(1)

DRDYLL-FR

NOTE: START pin held high previous to change on analog inputs. (1) Refer to Figure 39 for other modes.

Figure 42. Settling Example with the Low-Latency Filter in Fast-Response Configuration

20

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010
20 0 -20

Phase Response The Low-Latency filter uses a multiple-stage, linear-phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (also know as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency. This behavior results in essentially zero phase error when measuring multi-tone signals.

Magnitude (dB)

-40 -60 -80 -100 -120 -140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Frequency (fIN/fDATA)

WIDE-BANDWIDTH FILTER
The Wide-Bandwidth (WB) filter is well-suited for measuring high-frequency ac signals. This digital filter offers excellent passband and stop band characteristics. The DRATE[2:0] digital input pins select from the four data rates available with the WB filter, as shown in Table 6. Note that the START pin must be strobed after a change to the data rate. If a conversion is in process during a data rate change, the output data for that conversion are not valid and should be discarded. While using the Wide-Bandwidth filter path, the LL_CONFIG pin must be set to logic high. Setting LL_CONFIG low forces the ADS1675 to switch to a low-latency filter path, overriding the FPATH pin. Table 6. Wide-Bandwidth Data Rates
DRATE [2:0] 000 001 010 011 100 101 DATA RATE (kSPS) 125 250 500 1000 2000 4000 SETTLING TIME, tSETTLE-LL 439.44ms 219.81ms 110.00ms 55.04ms 27.52ms 13.79ms 14062tCLK 7074tCLK 3520tCLK 1763tCLK 2642tLSCLK 1324tLSCLK 3dB BANDWIDTH (kHz) 59.375 118.75 237.5 475 950 1900
Magnitude (dB)

Figure 43. Frequency Response of Wide-Bandwidth Filter blank

0.000010 0.000005 0

Magnitude (dB)

-0.000005 -0.000010 -0.000015 -0.000020 -0.000025 -0.000030 -0.000035 -0.000040 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Normalized Frequency (fIN/fDATA)

Figure 44. Passband Response for Wide-Bandwidth Filter

2 0 -2 -4 -6 -8 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Normalized Frequency (fIN/fDATA)

1. The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem. Frequency Response Figure 43 shows the frequency response for the Wide-Bandwidth filter path normalized to the output data rate, fDATA. Figure 44 shows the passband ripple, and the transition from passband to stop band is illustrated in Figure 45. These three plots are valid for all of the data rates available on the ADS1675. Simply substitute the selected data rate to express the x-axis in absolute frequency.

Figure 45. Transition Band Response for Wide-Bandwidth Filter

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

21

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency. Figure 46 shows the response with the fastest data rate selected (4 MSPS when fCLK = 32MHz).
20 0 -20

Settling Time The Wide-Bandwidth filter fully settles before indicating data are ready for retrieval after the START pin is taken high, as shown in Figure 48. For this filter, the settling time is larger than the conversion time: tSETTLE-WB > tDRDY-WB. Instantaneous steps on the input require multiple conversions to settle if START is not pulsed. Figure 47 shows the settling response with the x-axis normalized to conversions or data-ready cycles. The output is fully settled after 55 data-ready cycles.
120

Magnitude (dB)

-40 -60 -80 -100 -120

100 80

Settling (%)

-140 0 0.5 1.0 1.5 2.0 2.5 3.0 Normalized Frequency (fIN/fCLK)

60 40 20

Fully Settled at 55 Conversions

Figure 46. Extended Frequency Response of Wide-Bandwidth Path Phase Response The Wide-Bandwidth filter uses a multiple-stage, linear-phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (also know as constant group delay). This feature means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency. This behavior results in essentially zero phase error when measuring multi-tone signals.
tSTART_CLKR

0 -20 0 10 20 30 40 50 60 Conversions (1/fDRDY-WB)

Figure 47. Step Response for Wide-Bandwidth Filter

CLK

tSETTLE

START tDRDY
(1)

tDRDY

tDRDY

tDRDY

DRDY

(1) tDRDY = 1/fDATA. See Table 6 for the relationship between tSETTLE and tDRDY when using the Wide-Bandwidth filter.

Figure 48. START Pin Used for Multiple Conversions with Wide-Bandwidth Filter Path

22

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

OTRA, OTRD FUNCTIONS

The ADS1675 provides two out-of-range pins (OTRD, OTRA) that can be used in feedback loops to set the dynamic range of the input signal. The OTRA signal is triggered when the analog input to the modulator exceeds the positive or the negative full-scale range, as shown in Figure 49. This signal is triggered synchronous to CLK and returns low when the input becomes within range. The falling edge of OTRA is synchronized with the falling edge of DRDY. OTRA can be used in feedback loops to correct input over range conditions quicker instead of waiting for the digital filter to settle. The OTRD function is triggered when the output code of the digital filter exceeds the positive or negative full-scale range. OTRD goes high on the rising edge of DRDY. When the digital output code returns within the full-scale range, OTRD returns low on the next rising edge of DRDY. OTRD can also be used when small out-of-range input glitches must be ignored. OTRA can be used in feedback loops to correct input over-range conditions quickly.

SERIAL INTERFACE
The ADS1675 offers a flexible and easy-to-use, read-only serial interface designed to connect to a wide range of digital processors, including DSPs, microcontrollers, and FPGAs. In the low-speed modes (DRATE = 000 to 011) the ADS1675 serial interface can be configured to support either standard CMOS voltage swings or low-voltage differential swings (LVDS). In addition, when using standard CMOS voltage swings, SCLK can be internally or externally generated.
3V AIN

The high-speed modes (DRATE = 100, 101) are supported in high-speed LVDS interface mode only. The state of the LVDS pin and the SCLK_SEL are ignored. In these two modes, an on-chip PLL is used to multiply the input clock (CLK) by three, to be used for the serial interface. This high-speed clock enables all 23-bit output data to be shifted out at the high data rate. The DRDY pulse in this case is three serial clocks wide. The on-chip PLL can lock to input clocks ranging from 8MHz to 32MHz. To conserve power, the PLL is enabled only in the high-speed modes. After power up as well as after the CLK signal is issued, if the CLK frequency is changed, and when switching from low-speed mode to high-speed mode, the PLL needs at least tLPLLSTL to lock on and generate a proper LVDS serial shift clock. Switching among the high-speed modes does not require the user to wait for the PLL to lock. While the PLL is locking on, DOUT and SCLK are held low. After the PLL has locked on, the SCLK pin outputs a continuous clock that is three times the frequency of CLK. The device gives out a DRDY pulse (regardless of the status of the START signal) to indicate that the lock is complete. Disregard the data associated with this DRDY pulse. After this DRDY pulse, it is recommended that the user toggle the start signal before starting to capture data. The ADS1675 is entirely controlled by pins; there are no registers to program. Connect the I/O pins to the appropriate level to set the desired function. Whenever changing the digital I/O pins that control the ADS1675, be sure to issue a START pulse immediately after the change in order to latch the new values.

CLK SCLK (High-Speed Mode) DRDY

OTRA

(Low-Speed Mode)

OTRA

(High-Speed Mode)

Figure 49. OTRA Signal Trigger

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

23

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

USING LVDS OUTPUT SWINGS

When the LVDS pin is set to '0', the ADS1675 outputs are LVDS TIA/EIA-644A compliant. The data out, shift clock, and data ready signals are output on the differential pairs of pins DOUT/DOUT, SCLK/SCLK, and DRDY/DRDY, respectively. The voltage on the outputs is centered on 1.2V and swings approximately 350mV differentially. For more information on the LVDS interface, refer to the document Low-Voltage Differential Signaling (LVDS) Design Notes (literature number SLLA014) available for download at www.ti.com. When using LVDS, SCLK must be internally generated. The states of SCLK_SEL pin is ignored. Do not leave these pins floating; they must be tied high or low.

The DRDY pulse is the primary indicator from the ADS1675 that data are available for retrieval. Table 5 and Table 6 only give approximate values for settling time after a START signal. The rising edge of DRDY should be used as an indicator to start the data capture with the serial shift clock.

SERIAL SHIFT CLOCK (SCLK, SCLK, SCLK_SEL)

The serial shift clock SCLK is used to shift out the conversion data, MSB first, onto the Data Output pins. Either an internally- or externally-generated shift clock can be selected using the SCLK_SEL pin. If SCLK_SEL is set to '0', a free-running shift clock is generated internally from the master clock and outputs on the SCLK and SCLK pins. The LVDS pin determines if the output voltages are CMOS or LVDS. If SCLK_SEL is set to '1' and LVDS is set to '1', the SCLK pin is configured as an input to accept an externally-generated shift clock. In this case, the SCLK pin enters a high-impedance state. When SCLK_SEL is set to '0', the SCLK and SCLK pins are configured as outputs, and the shift clock is generated internally using the master clock input (CLK). When LVDS signal swings are used, the shift clock is automatically generated internally regardless of the state of SCLK_SEL. In this case, SCLK_SEL cannot be left floating; it must be tied high or low. Table 7 summarizes the supported serial clock configurations for the ADS1675. Table 7. Supported Serial Clock Configurations
DIGITAL OUTPUTS LVDS CMOS SHIFT CLOCK (SCLK) Internal Internal (SCLK_SEL = '0') External (SCLK_SEL = '1')

USING CMOS OUTPUT SWINGS

When the LVDS pin is set to '1', the ADS1675 outputs are CMOS-compliant and swing from rail to rail. The data out and data ready signals are output on the differential pairs of pins DOUT/DOUT and DRDY/DRDY, respectively. Note that these are the same pins used to output LVDS signals when the LVDS pin is set to '0'. DOUT and DRDY are complementary outputs provided for convenience. When not in use, these pins should be left floating. See the Serial Shift Clock section for a description of the SCLK and SCLK pins.

DATA OUTPUT (DOUT, DOUT)

Data are output serially from the ADS1675, MSB first, on the DOUT and DOUT pins. When LVDS signal swings are used, these two pins act as a differential pair to produce the LVDS-compatible differential output signal. When CMOS signal swings are used, the DOUT pin is the complement of DOUT. If DOUT is not used, it should be left floating.

DATA READY (DRDY, DRDY)

Data ready for retrieval are indicated on the DRDY and DRDY pins. When LVDS signal swings are used, these two pins act as a differential pair to produce the LVDS-compatible differential output signal. When CMOS signal swings are used, the DRDY pin is the complement of DRDY. If one of the data ready pins is not used when CMOS swings are selected, it should be left floating.

CHIP SELECT (CS)

The chip select input (CS) allows multiple devices to share a serial bus. When CS is inactive (high), the serial interface is reset and the data output pins DOUT and DOUT enter a high-impedance state. SCLK is internally generated; the SCLK and SCLK output pins also enter a high-impedance state when CS is inactive. The DRDY and DRDY outputs are always active, regardless of the state of the CS output. CS may be permanently tied low when the outputs do not share a bus.

24

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

DATA FORMAT
In the low-speed modes, the ADS1675 outputs 24 bits of data in twos complement format. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8 summarizes the ideal output codes for different input signals. When the input is positive out-of-range, exceeding the positive full-scale value of VREF, the output clips to all 7FFFFFh. Likewise, when the input is negative out-of-range by going below the negative full-scale value of VREF, the output clips to 800000h. Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN = (AINP AINN) VREF IDEAL OUTPUT CODE 7FFFFFh 000001h 000000h FFFFFFh
23

Measuring high-frequency, large amplitude signals requires tight control of clock jitter. The uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. Fortunately, the ADS1675 oversampling topology reduces clock jitter sensitivity over that of Nyquist rate converters, such as pipeline and SAR converters, by at least a factor of 8.

SYNCHRONIZING MULTIPLE ADS1675s

The START pin should be applied at power-up and resets the ADS1675 filters. START begins the conversion process, and the START pin enables simultaneous sampling with multiple ADS1675s in multichannel systems. All devices to be synchronized must use a common CLK input. It is recommended that the START pin be aligned to the falling edge of CLK to ensure proper synchronization because the START signal is internally latched by the ADS1675 on the rising edge of CLK. With the CLK inputs running, pulse START on the falling edge of CLK, as shown in Figure 50. Afterwards, the converters operate synchronously with the DRDY outputs updating simultaneously. After synchronization, DRDY is held high until the digital filter has fully settled.
ADS16751

+VREF
2
23

-1

-VREF
2
23

-1
23

< -VREF

( 2 2 - 1)

8000000h

1. Excludes effects of noise, INL, offset and gain errors. In the high-speed modes, the ADS1675 has 23 bits of resolution. The 24th bit in these modes is held low.

START CLK

START1 CLK

DRDY

DRDY1

CLOCK INPUT (CLK)

The ADS1675 requires an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any high-speed data converter, a high-quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources, such as frequency synthesizers, are usually inadequate. Make sure to avoid excess ringing on the CLK input; keep the trace as short as possible. For best performance, the CLK duty cycle should be very close to 50%. The rise and fall times of the clock should be less than 1ns and clock amplitude should be equal to AVDD.
CLK

ADS16752 START2 DRDY DRDY2

CLK tSETTLE START

DRDY1

DRDY2

Figure 50. Synchronizing Multiple Converters

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

25

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

ANALOG POWER DISSIPATION

An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 51. The current is inversely proportional to the resistor value. Figure 24 to Figure 26 (in the Typical Characteristics) show power and typical performance at values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS, because this additional capacitance interferes with the internal circuitry used to set the biasing.
ADS1675 RBIAS RBIAS AGND

including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. Make sure to allow time for the reference to start up after exiting power-down mode. After the reference has stabilized, allow for the modulator and digital filter to settle before retrieving data.

POWER SUPPLIES
Two supplies are used on the ADS1675: analog (AVDD) and digital (DVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1mF and 0.1mF ceramic capacitor be placed as close to each supply pin as possible. AVDD must be very clean and stable in order to achieve optimum performance from the device. Connect each supply-pin bypass capacitor to the associated ground. Each main supply bus should also be bypassed with a bank of capacitors from 47mF to 0.1mF. Figure 52 illustrates the recommended method for ADS1675 power-supply decoupling. Power-supply pins 53 and 54 are used to drive the internal clock supply circuits and, as such, are very noisy. It is highly recommended that the traces from these pins not be shared or run close to any of the adjacent AVDD or AGND pins of the ADS1675. These pins should be well-decoupled, using a 0.1mF ceramic capacitor close to the pins, and immediately terminated into power and ground planes.

Figure 51. External Resistor Used to Set Analog Power Dissipation (Depends on fCLK)

POWER DOWN (PDWN)

When not in use, the ADS1675 can be powered down by taking the PDWN pin low. All circuitry shuts down,

26

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com
+5V +3V 0.1mF 0.1mF 0.1mF 10mF

SBAS416D DECEMBER 2008 REVISED AUGUST 2010

58

57

56

54

53

52

51

50

49

AVDD AGND AGND 1 AVDD 2 AGND 3 AGND

AGND AVDD DVDD DGND DGND DVDD DVDD 48 0.1mF DGND 47 10mF

+5V

0.1mF

10mF

6 AGND

ADS1675
7 AVDD

9 AGND 10 AGND 11 AVDD 12 AVDD DGND DGND DGND DGND DVDD DVDD DGND DGND DVDD DGND 17 18 19 20 23 24 25 26 27 31

0.1mF 10mF

Figure 52. Power-Supply Decoupling

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

27

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010 www.ti.com

APPLICATION INFORMATION
To obtain the specified performance from the ADS1675, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires two power supplies for operation: DVDD and AVDD. A very clean and stable AVDD supply is needed to achieve optimal performance from the device. For both supplies, use a 10mF tantalum capacitor, bypassed with a 0.1mF ceramic capacitor, placed close to the device pins. Alternatively, a single 10mF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power-supply source is used, the voltage ripple should be low (less than 2mV). The power supplies may be sequenced in any order. 2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. 3. Digital Inputs: Source terminate the digital inputs to the device with 50 series resistors. The resistors should be placed close to the driving end of the digital source (oscillator, logic gates, DSP, etc.). These resistors help reduce ringing on the digital lines, which may lead to degraded ADC performance. 4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 5. Reference Inputs: The ADS1675 reference input has 400 across VREFP and VREFN. The driving amplifier must source current for this static current, as well as dynamic switching current as a result of the 32MHz clock. The reference driving amplifier should be ready to source at least 10.5mA. 6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 750pF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground should be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the ac common-mode performance. 7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This placement is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components. Figure 53 through Figure 55 illustrate the basic connections and interfaces that can be used with the ADS1675.

28

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

1kW 10nF +5V

0.1mF 10W OPA211 10mF 0.1mF 1mF 1mF 100W 100mF 1kW 0.1mF 3V 22mF OUT TRIM REF5030 VIN +5V

64 10W VINN Differential Inputs 10W VINP 100pF 4 AINN 750pF 5 AINP 100pF

63

62

61

60

59

VREFP VREFP CAP2 VREFN VREFN CAP1

ADS1675
8 RBIAS 7.5kW 13 VCM 1 mF

Figure 53. Basic Analog Signal Connection

CF 100pF RF 249W +9V RG 249W VIN+ VINRG 249W -4V +
THS4503

CM 2.5V CM 2.5V

VINN VINP

+ CM 2.5V RF 249W

CF 100pF

Figure 54. Basic Differential Input Signal Interface

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

29

ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
CF 100pF

www.ti.com

Signal Source RS 50W RG 243W RT 59W CM 2.5V RF 249W

VIN

+9V

CM 2.5V

CM 2.5V

RS 50W

RG 243W

+ -

THS4503

VINN VINP

RT 59W

CM 2.5V

CM -4V 2.5V RF 249W CF 100pF

Figure 55. Basic Single-Ended Input Signal Interface

30

Submit Documentation Feedback Product Folder Link(s): ADS1675

Copyright 20082010, Texas Instruments Incorporated

ADS1675
www.ti.com SBAS416D DECEMBER 2008 REVISED AUGUST 2010

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ form page numbers in the current version.
Changes from Revision C (September 2009) to Revision D Page

Changed 115dB to 86dB in second paragraph of Description section ................................................................................. 1 Changed AC Performance, Total harmonic distortion (fDATA = 4MSPS) typical specifiaction in Electrical Characteristics table ............................................................................................................................................................. 3 Changed Digital Filter Characteristics (Wide-Bandwidth Path), Stop band attentuation typical specification in Electrical Characteristics table .............................................................................................................................................. 3 Added footnote 2 to Figure 1 ................................................................................................................................................ 7 Updated Figure 3 .................................................................................................................................................................. 8 Changed description of tDRSCLK parameter in internal SCLK timing requirements table ....................................................... 8 Changed description of tLSCLK parameter in internal SCLK timing requirements table ......................................................... 8 Deleted footnote 1 from Figure 5 .......................................................................................................................................... 9 Changed the description of the Common-Mode Voltage section ....................................................................................... 17 Added description of 24th bit to Data Format section ........................................................................................................ 25 Changed description of the Reference Inputs guidline in Application Information section ................................................. 28

Changes from Revision June 2009 (B) to Revision C

Page

Changed [1:0] to [2:0] in DRATE column of Table 6 .......................................................................................................... 21 Changed REF5030 connections in Figure 53 ..................................................................................................................... 29

Copyright 20082010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): ADS1675

31

PACKAGE OPTION ADDENDUM

www.ti.com

16-Jul-2010

PACKAGING INFORMATION
Orderable Device ADS1675IPAG ADS1675IPAGR Status
(1)

Package Type Package Drawing TQFP TQFP PAG PAG

Pins 64 64

Package Qty 160 1500

Eco Plan

(2)

Lead/ Ball Finish

MSL Peak Temp

(3)

Samples (Requires Login) Request Free Samples Purchase Samples

ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU Level-4-260C-72 HR CU NIPDAU Level-4-260C-72 HR

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing TQFP PAG 64

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 13.0

B0 (mm) 13.0

K0 (mm) 1.5

P1 (mm) 16.0

W Pin1 (mm) Quadrant 24.0 Q2

ADS1675IPAGR

1500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2010

*All dimensions are nominal

Device ADS1675IPAGR

Package Type TQFP

Package Drawing PAG

Pins 64

SPQ 1500

Length (mm) 346.0

Width (mm) 346.0

Height (mm) 41.0

Pack Materials-Page 2

MECHANICAL DATA
MTQF006A JANUARY 1995 REVISED DECEMBER 1996

PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17

PLASTIC QUAD FLATPACK

0,08 M

49

32

64

17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0 7 0,75 0,45 16

1,20 MAX

0,08 4040282 / C 11/96

NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee Solutions www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Applications Communications and Telecom www.ti.com/communications Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Transportation and Automotive Video and Imaging Wireless www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/automotive www.ti.com/video www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2011, Texas Instruments Incorporated