Spring Semester Faculty of Engineering and
2024/2025 Technology
Computer Organization & Course Code: ELC 152
Architecture
& COM 132 & COM 223
Sheet 8
1. Consider a memory system that uses a 32-bit address to address at the byte level, plus a
cache that uses a 64-byte line size.
a. Assume a direct mapped cache with a tag field in the address of 20 bits. Show the
address format and determine the following parameters: number of addressable units,
number of blocks in main memory, number of lines in cache, size of tag.
b. Assume an associative cache. Show the address format and determine the following
parameters: number of addressable units, number of blocks in main memory, number
of lines in cache, size of tag.
c. Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show
the address format and determine the following parameters: number of addressable
units, number of blocks in main memory, number of lines in set, number of sets in
cache, number of lines in cache, size of tag.
2. A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main
memory contains 4K blocks of 128 words each. Show the format of main memory
addresses.
3. Virtual memory in a computer system divided to 8 pages each page has 1k words in each,
the memory mapping table shown in the following.
a. What is fault pages?
b. Find the addresses in each fault page (in decimal)?
Page Block
0 3
1 1
4 2
6 0
Memory mapping table
Best Wishes
Dr. Samar Ashraf