UNIT II
Combinational circuit
design
Combinational circuit
When logic gates are connected together to produce a specified output
for certain specified combinations of input variables, with no storage
involved, the resulting circuit is called combinational logic circuit.
In combinational logic circuit, the output variables are at all times
dependent on the combination of input variables.
In combinational logic circuit the output depends only on the present
input.
The combinational circuit accepts n-input binary variables and
generates output variables depending on the logical combination of
gates.
Examples of
combinational circuits
Binary Adder - Half adder ,Full adder,RCA,CPA
Binary Subtractor - Half subtractor, Full subtractor
Binary Multiplier
Multiplexer
Demultiplexer
Encoder
Decoder
Comparator
Parity generator
Code converter
Design procedure
The design procedure of the combinational circuit involves
following steps :
Step 1: The problem definition.
Step 2: The determination of number of available input
variables and required output variables. Assigning
letter symbols to input and output variables.
Step 3: Draw the block diagram
Step 4: The derivation of truth table indicating the
relationships between input and output variables.
Step 5: Obtain simplified Boolean expression for each output
using K-Map.
Step 6: Obtain the logic diagram.
Design of Adders
Digital computers perform various arithmetic
operations.
The most basic operation, no doubt, is the
addition of two binary digits.
The higher significant bit of the result is called a
carry, and lower significant bit is called sum.
The logic circuit which performs addition of two
bits is called a half-adder.
The circuit which performs addition of three bits
is a full-adder.
Design of half adder
Step 1: Definition - Performs two bit addition
Step 2: Determination of number of input and output
variable.
* Input - A,B
* Output - Sum (S) , Carry (C)
Step 3: Block diagram
A S
Half
B Adder C
Step 4: Derivation of truth table
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Step 5: simplified Boolean expression for each output using
K-Map
B’ B B’ B
B 0 1 B 0 1
A A
A’ 0 0 0 1 1 A’ 0 0 0 0 1
A 1 1 2 03 A 1 0 2 13
S= AB’+A’B C=AB
= A⊕B
Step 6: Draw the logic diagram
Limitations of Half-Adder :
In multidigit addition we have to add two bits along with
the carry of previous digit addition. Effectively such
addition requires addition of three bits. This is not possible
with half-adder. Hence half-adders are not used in practice.
Design of full adder
Step 1: Definition - Performs three bit addition
Step 2: Determination of number of input and output
variable.
* Input - A, B, C
* Output - Sum (S) , Carry (Cout)
Step 3: Block diagram
A S
Full
B
C Adder Cout
Step 4: Derivation of truth table
Inputs Outputs
A B C S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Step 5: simplified Boolean expression for each output using
K-Map
BC B’C’ B’C BC BC’
A 00 o1 11 10
A’ 0 0 1 0 1 S =A’B’C+A’BC’+AB’C’+ABC
0 1 3 2
=A’(B’c+BC’)+A(B’C’+BC)
A 1 1 0 1 0 = A’(B⊕C)+A(B⊕C)’
4 5 7 6
= A⊕B⊕C
BC B’C’ B’C BC BC’
A 00 o1 11 10
A’ 0 0 0 1 0
0 1 3 2
A 1 0 1 1 1
4 5 7 6 Cout=AC+BC+AB
Step 6: Draw the logic diagram
Full adder using two half
adder
Design of subtractor
Another basic operation is the subtraction of two
binary digits.
In all subtraction operations, each subtrahend bit
is subtracted from the minuend bit.
In case the minuend bit is smaller than the
subtrahend bit, then 1 is borrowed.
The logic circuit which performs subtraction of
two bits is called a half-subtractor.
The circuit which performs subtraction of three bits
is a full-subtractor.
Design of half subtractor
Step 1: Definition - Performs two bit subtraction
Step 2: Determination of number of input and output
variable.
* Input - A,B
* Output - Difference (D) , Barrow (Bout)
Step 3: Block diagram
A D
Half
B Subtractor
Bout
Step 4: Derivation of truth table
Inputs Outputs
A B D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Step 5: simplified Boolean expression for each output using
K-Map
B’ B B’ B
B 0 1 B 0 1
A A
A’ 0 0 0 1 1 A’ 0 0 0 1 1
A 1 1 2 03 A 1 0 2 03
D= AB’+A’B Bout=A’B
= A⊕B
Step 6: Draw the logic diagram
Limitations of half-subtractor :
In multidigit subtraction, we have to subtract two bits along with
the borrow of the previous digit subtraction. Effectively such
subtraction requires subtraction of three bits. This is not possible
with half-subtractor
Design of full Subtractor
Step 1: Definition - Performs three bit subtraction
Step 2: Determination of number of input and output
variable.
* Input - A, B, C
* Output - Difference (D) , Barrow (Bout)
Step 3: Block diagram
A D
Full
B
C
Subtractor
Bout
Step 4: Derivation of truth table
Inputs Outputs
A B C D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Step 5: simplified Boolean expression for each output
using K-Map
BC B’C’ B’C BC BC’
A 00 o1 11 10
A’ 0 0 1 0 1
0 1 3 2 D=A’B’C+A’BC’+AB’C’+ABC
A 1 = A⊕B⊕C
1 0 1 0
4 5 7 6
BC B’C’ B’C BC BC’
A 00 o1 11 10
A’ 0 0 1 1 1
0 1 3 2 Bout=A’C+BC+A’B
A 1 0 0 1 0
4 5 7 6
Step 6: Draw the logic diagram
Full subtractor using two
half subtractor
Parallel adder or ripple carry
adder
A single full-adder is capable of adding two one-
bit numbers and an input carry.
In order to add binary numbers with more than one
bit, additional full adders must be employed.
A n-bit, parallel adder can be constructed using
number of full adder circuits connected in parallel.
Fig. shows the block diagram of n-bit parallel adder
using number of full-adder circuits connected in
cascade, i.e. the carry output of each adder is
connected to the carry input of the next higher-
order adder.
A ripple carry adder is a logic circuit in
which the carry-out of each full adder is
the carry in of the succeeding next most
significant full adder.
It is called a ripple carry adder because
each carry bit gets rippled into the next
stage.
n-bit Parallel
adder
4 bit ripple carry adder or
parallel adder
1 1 1 1 01 01
1 1 0 0 0
1 0 0 0C
Eg: 1 1 0 0 A
1 0 1 1 +
1 1 1 1 B
1 1 0 1 1
The two 4-bit numbers are 1100 (A3A2A1A0) and 1111 (B3B2B1B0).
These numbers are to be added using a 4-bit ripple carry adder.
Assume initial carry Cin = 0.
In least significant stage A0,B0,Cin are added the resulting in
sum S0 and carry C0.This carry C0 becomes carry input of
second stage.
In the second stage A1,B1,C0 are added the resulting in sum S1
and carry C1.This carry C1 becomes carry input of third stage.
In the third stage A2,B2,C1 are added the resulting in sum S2
and carry C2.This carry C2 becomes carry input of fourth stage.
In the fourth stage A3,B3,C2 are added the resulting in sum S3
and carry Cout.
S0,S1,S2,S3 is final sum and Cout is final carry output.
Disadvantage of ripple carry
adder
The main disadvantage of RCA is speed of
operation is limited of carry propagation delay.
In ripple carry adder the carry output of each full-
adder stage is connected to the carry input of the
next higher-order stage.
Therefore, the sum and carry outputs of any stage
cannot be produced until the input carry occurs;
this leads to a time delay in the addition
process.This delay is known as carry propagation
delay.
Parallel subtractor using
full subtractor
01 01 11 10
1 1 0 Bout
Eg: 1 1 1 0 A -
0 1 1 0 0 0 1 1 B
1 0 1 1
1 0 1 1
0
Parallel subtractor
using Full adder
The subtraction of binary numbers can be done most
conveniently by means of complements.
Remember that the subtraction A-B can be done by
taking the 2’s complement of B and adding it to A.
The 2’s complement can be obtained by taking the 1’s
complement and adding one to the least significant
pair of bits.
The 1’s complement can be implemented with inverters
and a one can be added to the sum through the input
carry, as shown in the Fig.
Parallel subtractor
using Full adder
Parallel adder / subtractor
A B S
0 0 0
0 1 1
Exor gate truth table
1 0 1
1 1 0
Parallel adder / subtractor
The addition and subtraction operations can be
combined into one circuit with one common
binary adder.
This is done by including an exclusive-OR gate
with each full adder, as shown in Fig.
The mode input M controls the operation of the
circuit.
When M = 0, the circuit is an adder,
When M = 1, the circuit becomes a subtractor.
When M = 0, we have B⊕0 = B. The full-adders
receive the value of B, the input carry is 0,
and the circuit performs A plus B.
When M = 1, we have B⊕1 = B’ and Cin0 = 1. The
B inputs are all complemented and a 1 is
added through the input carry. The circuit
performs the operation A plus the 2’s
complement of B, i.e. A – B.
Carry look ahead adder
BCD Adder
The digital systems handle the decimal number
in the form of binary coded decimal numbers
(BCD).
A BCD adder is a circuit that adds two BCD
digits and produces a sum digit also in BCD.
To implement BCD adder we require :
* 4-bit binary adder for initial addition
* Logic circuit to detect sum greater than 9 and
* One more 4-bit adder to add 0110 in the sum
if sum is greater than 9 or carry is 1.
The logic circuit to
detect sum greater than
9 can be determined by
simplifying the boolean
expression of given
truth table.
Y = 1 indicates sum is
greater than 9. We can
put one more term,
Cout in the above
expression to check
whether carry is one.
BCD adder
The two BCD numbers, together with input carry, are
first added in the top 4-bit binary adder to produce
a binary sum.
When the output carry is equal to zero (i.e. when sum
< = 9 and Cout = 0) nothing (zero) is added to the
binary sum.
When output carry is equal to one (i.e. when sum > =
9 or Cout = 1), binary value of 9 ie. 0110 is added
to the binary sum through the bottom 4-bit binary
adder.
The output carry generated from the bottom binary
adder can be ignored, since it supplies information
already available at the output-carry terminal.
