Module 4
Intel 80386DX Processor
Module 4: Intel 80386DX Processor
Topics:
4.1: Architecture of 80386 microprocessor
4.2:80386 registers–General purpose Registers, EFLAGS and Control registers
4.3:Real mode, Protected mode, virtual 8086 mode
4.4:80386 memory management in Protected Mode – Descriptors and selectors,
descriptor tables, the memory paging mechanism
Features of 80836
80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit operations in one cycle. It has
a data and address bus of 32-bit each. Thus has the ability to address 4 GB (or 232) of physical memory.
● It is a 32-bit microprocessor. Thus has a 32-bit ALU.
● 80386 has a data bus of 32-bit.
● It holds an address bus of 32 bit.
● It supports physical memory addressability of 4 GB and virtual memory addressability of 64 TB.
● 80386 supports a variety of operating clock frequencies, which are 16 MHz, 20 MHz, 25 MHz, and 33
MHz.
● It offers 3 stage pipeline: fetch, decode and execute. As it supports simultaneous fetching, decoding, and
execution inside the system.
Architecture of 80386 Microprocessor
Architecture of 80386 Microprocessor
Basically, it has 6 functional units which are as follows:
1. Bus Interface Unit
2. Code Fetch Unit
3. Instruction Decode Unit
4. Execution Unit
5. Memory Management Unit
1. Bus Interface Unit
The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as a 32-bit address bus. Whenever a need for instruction or a data fetch is
generated by the system then the BIU generates signals (according to the priority) for activating the data and address bus in order to fetch the data
from the desired address.
2. Code Prefetch Unit
This unit fetches the instructions stored in the memory by making use of system buses. Whenever the system generates a need for instruction then
the code prefetch unit fetches that instruction from the memory and stores it in a 16-byte prefetch queue. So to speed up the operation this unit
fetches the instructions in advance and the queue stores these instructions. The sequence in which the instructions are fetched and gets stored in
the queue depends on the order they exist in the memory.
As this unit fetches one double word in a single access. So, in such a case, it is not necessary that each time only a single instruction will be
fetched, as the fetched instruction can be parts of two different instructions.
3. Instruction Decode Unit
We know that instructions in the memory are stored in the form of bits. So, this unit decodes the instructions stored in the prefetch queue. Basically
the decoder changes the machine language code into assembly language and transfers it to the processor for further execution.
4. Execution Unit
The decoded instructions are stored in the decoded instruction queue. So, these instructions are provided to the execution unit in order to execute
the instructions. The execution unit controls the execution of the decoded instructions. This unit has a 32-bit ALU, that performs the operation over
32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8 special purpose registers. These are used for data handling and
calculation of offset address.
5. Memory Management Unit
This unit has two separate units within it. These are
1. Segmentation Unit and
2. Paging Unit
Segmentation unit: The segmentation unit plays a vital role in the 80836 microprocessor. It offers a protection mechanism in order to protect the
code or data present in the memory from application programs. It gives 4 level protection to the data or code present in the memory. Every
information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the highest priority and PL3 holds the lowest
priority.Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0. Then only those programs which are working
at PL0 would be able to access that file.
Paging Unit: The paging unit operates only in protected mode and it changes the linear address into a physical address. As the programmer only
provides the virtual address and not the physical address. The segmentation unit controls the action of the paging unit, as the segmentation unit has
the ability to convert the logical address into the linear address at the time of executing an instruction.
Registers of 80386
80386: General purpose register
1. EAX (Accumulator) Register
EAX 32 bit register
AX 16 bit register
AH AND AL 8 bit register
It usually accumulates the result of any ALU operation, but can also be used as general
purpose register. In 386 and above It may also hold an address to access a memory
location.
2. EBX Register
EBX:32 bit register
BX:16 bit register
BH AND BL:8 bit register
It works as Base Index. In 386 and above It may also hold an address to access a
memory location.
3. ECX (Counter) Register
ECX:32 bit register
CX:16 bit register
CH AND CL:8 bit register
It is used for repeated string instruction, shift, rotate and loop instruction. In 386 and above It
may also hold an address to access a memory location.
4. EDX (Data Register)
EDX:32 bit register
DX:16 bit register
DH AND DL:8 bit register
It holds result after multiplication or for division it holds the dividend. In 386 and above It may
also hold an address to access a memory location.
5. EBP (Base Pointer) Register
EBP:32 bit register
BP:16 bit register
It works as pointer for stack segment
6. EDI (Destination Index)
EDI:32 bit register
DI:16 bit register
It holds the destination data for string instructions. For other instruction it is used to
select a location in data segment.
7. ESI (Source Index)
ESI:32 bit register
SI:16 bit register
It holds the source data for string instruction,For other instruction it is used to select a
location in data segment.
8. ESP (Stack Pointer)
Used to address the memory location in the stack segment.
80386: Flag Register
80386: Control Register
A control register is a processor register which changes or controls the
general behavior of a CPU or other digital device. Common tasks performed by
control registers include interrupt control, switching the addressing mode,
paging control, and coprocessor control.
80386 has 4 control register of 32 bit each namely CR0, CR1,CR2, CR3. Only
3 are used namely CR0, CR2, CR3. CR1 is reserved for future use .
CR0 : Control Register
Address Modes of 80386
Protection Mechanism in 80386
80386 DX has four levels of protection which isolate and protect user
programs from each other and the operating system.
It offers an additional type of protection on a page basis, when paging is
enabled(using U/S and R/W fields)
The four-level hierarchical privilege system is illustrated as follows:
1. The privilege levels (PL) are numbered 0 through 3.
2. Level 0 is the most privileged or trusted level.
3. Rules for privilege:
Intel 80386 controls access to both data and procedures according to the following rules:
a. Data segment with privilege level p can be accessed only by the code executing at a
privilege level atleast as privileged as p (E.g. Application programs are prevented from
reading or changing OS Tables)
b. A code segment with a privilege level p can only be called by a task executing at the
same or lesser privilege level than p (E.g. An Application Program may call an OS
routine)
4. Privilege Level
There are 3 different types of privilege level entering into the privilege level checks:
Current Privilege Level (CPL)
Descriptor Privilege Level (DPL)
Requestor Privilege Level (RPL)
Protected mode addressing
