EE5332 Mapping DSP to Arch Tutorial 1 - Feb 2025
1. Which of the following operations is implemented by the following equation (mark all that apply):
y(n) = ax(n) + bx(n − 1) + cx(n − 3)
A. FIR filter B. IIR filter C. FFT D. DCT
2. Which of the following operations is implemented by the following equation (mark all that apply):
y(n) = ax(n) + by(n − 1) + cx(n − 3)
A. FIR filter B. IIR filter C. FFT D. DCT
3. A signal is being sampled using an ADC, and you are told that the highest frequency component in the
signal is 20kHz. What is the minimum rate (in Hz) at which the ADC should capture samples to permit
lossless reconstruction of the signal?
4. Represent the following in 2’s complement binary notation using the minimum required number of bits:
(a) +57:
(b) -37:
5. What is the value of 01011010 when interpreted as:
• Q4.4
• Q2.6
• Q6.2
6. Represent the following numbers in Q3.8 format:
• 0.0
• 1.25
• -2.3
7. For each question below, select True (T) or False (F). Assume all other operating conditions are un-
changed.
(a) Higher operating voltage will make a circuit operate more slowly.
(b) Higher operating voltage will make a circuit consume more power.
(c) A larger gate will have a lower input capacitance than a smaller one.
8. Draw block diagrams and dataflow graphs corresponding to the following equations:
1. y(n) = ay(n − 1) + bx(n)
2. y(n) = a1 y(n − 1) + a2 y(n − 2) + b0 x(n) + b1 x(n − 1) + b2 x(n − 2)
3. v1 (n) = x1 (n) + x2 (n); v2 (n) = x1 (n) − x2 (n)
9. If we want to represent numbers having a dynamic range of 104 using two’s complement binary numbers,
the minimum number of bits required is:
10. Consider a 32-bit floating point representation similar to the IEEE standard representation discussed in
class, with the following settings:
• 1 bit used for sign
• 4 bits for exponent: here 0000 and 1111 are reserved values, and the exponent is stored with an
offset of 7 (ie, 7 is added to the value of the exponent just like 127 is added in the case of IEEE-754
single precision floating point)
EE5332 Mapping DSP to Arch Tutorial 1 - Feb 2025
• Remaining bits are used for mantissa
(a) What are the smallest and largest positive values that can be represented using this format, and
what is the dynamic range?
(b) What is the maximum dynamic range you would get if you used the 32 bits as a fixed point number?
How many bits should be used for the integer and fraction portions to get this dynamic range?
(c) What is the minimum number of bits to be used for exponent so you get a dynamic range better
than fixed point?
11. A system designer finds several design solutions to a problem, and has 3 cost metrics: (area, latency,
power). For all metrics, lower values are better. From the solutions given here, identify which are the
Pareto optimal solutions, and briefly explain why the others are not. Solutions – A: (10, 20, 50), B: (20,
20, 50), C: (12, 25, 60), D: (8, 25, 30), E: (20, 15, 40), F: (30, 15, 50).
(a) Mark all the Pareto Optimal solutions here.
⃝ A ⃝ B ⃝ C ⃝ D ⃝ E ⃝ F
(b) Mark all the solutions that are dominated by solution A.
⃝ B ⃝ C ⃝ D ⃝ E ⃝ F
(c) Mark all the solutions that dominate solution B.
⃝ A ⃝ C ⃝ D ⃝ E ⃝ F
(d) If only latency and power are considered important metrics, mark all the Pareto Optimal solutions
here.
⃝ A ⃝ B ⃝ C ⃝ D ⃝ E ⃝ F
12. Consider the FIR filter shown in the figure below. Assuming each multiplier and each adder has a delay
of 1 time unit, answer the following questions:
(a) What is the equation implemented by the filter?
(b) What is the length of the critical path, and mark this critical path in the figure.
(c) What is the minimum critical path that can be obtained for this circuit using only pipelining (no
parallelism or other changes)?
(d) What is the minimum number of extra registers you will need to add to this circuit to get to the
minimum critical path? Show all the cutsets you will use for pipelining this way.
13. Two processors A and B communicate through a FIFO buffer that is implemented in hardware. A
produces data in bursts, and writes data into the buffer at a rate of 10Mbps. B consumes data (whenever
present) at a steady rate of 100kbps. The maximum time duration of any single burst from A is 1ms.
Fig. 1 shows an example sequence of transmissions from A: the Toni values are the time durations when
A is transmitting, while Tof f i are when it is silent. B is always ready to read data if present. In this
case, max Toni = 1ms.
(a) What should be the average time between bursts of data from A to ensure that the FIFO will not
eventually overflow? ie. What should be the average value of Tof f i as t → ∞?
Page 2
EE5332 Mapping DSP to Arch Tutorial 1 - Feb 2025
Figure 1: Question 13
(b) Assuming that the minimum Tof f i = 10ms but the average Tof f i over any interval of 1 second
duration has the value computed above (to prevent overflow), what should be the capacity of the
FIFO (number of bits it can hold) to prevent overflow?
14. For the following figure assume addition takes 1 time unit, and multiplication takes 2 t.u.
x(n)
+
x x
x x x
y(n)
+ +
(a) What is the critical path that will determine the clock period assuming the delay elements are
registers?
(b) What is the iteration period bound?
(c) Pipeline the filter by placing latches at appropriate positions, to reduce the critical path to 3 t.u.
15. Find the critical path and iteration period bound for the following DFG (delay values in brackets):
A(1) B(1) C(2) D(3)
E(2) D
D
Page 3
