Processor Architecture

Unit-3 Part -2

Processor Architecture ( Unit-3 ) 1

Topics

• Interrupt processing in 8086

• Classification of interrupts
• Interrupt handler
• Interrupt vector table
• Multiple interrupt processing
• DOS INT 21H, INT 10H,
• Interrupt function codes.
Rules of storing different data types
Type Example Valid / Invalid

Decimal 245 Valid

Decimal 23674d Valid

Decimal A234 Invalid (Invalid Digit)

Decimal 65478D Valid

Hexadecimal 0ABCD Invalid (Should end with h/H)

Hexadecimal 1EFCH Valid

Hexadecimal 2DDDh Valid

Hexadecimal ABCDEh Invalid (Doesn’t start with digit)

Binary 0011000b Valid

Binary 100001 Invalid (Should end with b/B)

Binary 310000b Invalid (Wrong digit )

Binary 1011010B Valid

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Rules of storing different data types
Type Example Valid / Invalid

Character ‘A’ Valid

Character “D” Valid

Character S Invalid

Character ‘P’ Valid

String ‘Vishwakarma$’ Valid

String “University$” Valid

String Amit Invalid ( Not in quotes)

String ‘Kishore ’ Invalid ( Not terminated with $’ )

String “Ajit $” Valid

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Variable Declarations

5
Interrupts

6
Role of Control Unit - Control Signals

• CU is the controlling unit within a CPU

• CU maintains the proper sequence of events required for any processing task by generating
micro-instructions (signals in sequence)

– Using clock inputs

• CU issues the appropriate signals for initiating the proper sub-tasks needed in processing of
data - to units both internal and external to CPU

• Often CU is capable of responding to external signals known as interrupts

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Interrupt

• An Interrupt request will cause the CPU to temporarily suspend the main program
execution to serve the interrupting device

• After serving the interrupting device, the CPU will automatically return to the main
program at point where execution was left.

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Interrupt Signal

ADDRESS BUS
16 / 20 / 24 / 32 / 64-bit wide
µP
contains
CONTROL BUS
CU
ALU
Timing signals, ready
data registers
and
signals, interrupts etc
pointer registers

DATA BUS –
bidirectional
8 / 16 / 32 / 64 / 128-bit

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Role of IF Interrupt Flag

• The interrupt flag controls the operations of the INTR (Interrupt request)
input pint.

• If IF= 1, the INTR pin is enabled;

• if IF =0, the INTR pin is disabled.

• Can be set by the STI (set IF flag) instruction

• Can be clear/reset by CLI (Clear IF flag) instruction

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Interrupts
➢ When your phone rings during a lecture, what will happen?

➢ When you are studying then your cell phone rings – what will you do?

❖ When you finish talking on the phone then you will continue with your study.

➢ Now your phone rings again and someone also knocking at your door then what will
you do?

❖ When being interrupted, you will perform some pre-

defined action.
❖ Interrupt has priority – some interrupt is more important than the others.

For example, answering your phone is more import

Interrupts

➢ An interrupt is used to cause a temporary halt in the execution of program.

➢ The meaning of ‘interrupts’ is to break the sequence of operation.

➢ While the Microprocessor is executing a program, an ‘interrupt’ breaks the normal

sequence of execution of instructions, diverts its execution to some other program
called Interrupt Service Routine (ISR).

• After executing ISR, IRET returns the control back again to the main program.
Interrupt processing is an alternative to polling.
Need for Interrupt

➢ Interrupts are particularly useful when interfacing I/O devices, that provide or
require data .

• Sources of Interrupts:

• Three types of interrupts sources are there:

– An external signal applied to NMI or INTR input pin( hardware interrupt)
– Execution of Interrupt instruction( software interrupt)
– Interrupt raised due to some error condition produced in 8086 instruction
execution process. (Divide by zero, overflow errors etc)
8086 Interrupt Processing
If an interrupt has been requested, the 8086 Microprocessor processes it by
performing the following series of steps:
• Pushes the content of the flag register onto the stack to preserve the status of the interrupt
flag (IF) and trap flags (TF), by decrementing the stack pointer (SP) by 2

• Disables the INTR interrupt by clearing IF in the flag register

• Resets TF in the flag register, to disable the single step or trap interrupt
• Pushes the content of the code segment (CS) register onto the
stack by decrementing SP by 2

• Pushes the content of the instruction pointer (IP) onto the

stack by decrementing SP by 2

• Performs an indirect far jump to the start of the interrupt service routine (ISR) corresponding

to the received interrupt.

Steps involved in processing an interrupt instruction by the processor
Executes the Interrupt instructions INT 21H mother
ISR-M

INT 10 H father
Jumps to the Interrupt Vector Table ISR-F

INT 03H - sister

ISR-S
Takes the CS and IP in the Vector Table
IVT

Pushes the existing CS and IP on the Stack

Address of ISR-F ISR-F
Address of ISR--M

Address of ISR--S IRET

Loads the new CS and IP

ISR-M
Jumps to the Interrupt Service Routine
IRET

Executes the Interrupt Service Routine

ISR-S

IRET
Comes back and continues the Main Program
Processing of an Interrupt by the 8086

Main Program Push flags register Interrupt Service

Clear IF and TF Routine (ISR)
Push Current CS and IP Load CS
and IP from IVT

Interrupt program
Interrupt :
:
:
Pop IP and CS from stack
:
Pop flags register from stack
:
:
IRET
 Interrupts

Hardware Software Interrupts

Interrupts INT n

Maskable Nonmaskable 256 Types of

Interrupts Interrupts software Interrupts
INT 00 to INT FF

The programmer The programmer cannot

can choose to mask control when a non maskable
specific interrupts interrupt is served
and re-enable them
later The processor has to stop
the main program to execute
the NMI Service Routine.
Hardware Interrupt

• The interrupts initiated by external hardware by sending an appropriate signal to

the interrupt pin of the processor is called hardware interrupt.

• The 8086 processor has two interrupt pins INTR and NMI. The interrupts
initiated by applying appropriate signal to these pins are called hardware
interrupts of 8086.
Hardware Interrupt

Used to handle external hardware peripherals , such as key boards , mouse , hard

disks , floppy disks , DVD drivers, and printers.

Maskable interrupt

• The processor has the facility for accepting or rejecting hardware interrupts.
Programming the processor to reject an interrupt is referred to as masking or disabling
and

• Programming the processor to accept an interrupt is referred to as unmasking or

enabling.

• In 8086 the interrupt flag (IF) can be set to one to unmask or enable all hardware
interrupts and IF is cleared to zero to mask or disable a hardware interrupts except NMI.

• The interrupts whose request can be either accepted or rejected by the processor are
called maskable interrupts.
Non Maskable

• The interrupts whose request has to be definitely accepted (or cannot be rejected) by
the processor are called non-maskable interrupts.

• Whenever a request is made by non-maskable interrupt, the processor has to

definitely accept that request and service that interrupt by suspending its current
program and executing an ISR.

• In 8086 processor all the hardware interrupts initiated through INTR pin are maskable
by clearing interrupt flag (IF).

• The interrupt initiated through NMI pin and all software interrupts are non-maskable.
Software interrupts

• The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.

• While running a program, if software interrupt instruction is encountered then the

processor initiates an interrupt.

• The 8086 processor has 256 types of software interrupts. The software interrupt
instruction is INT n, where n is the type number in the range 0 to 255.
 Interrupt Vector Table( IVT)
• The processor uses the interrupt vector to determine the address of the ISR
of the interrupting device.
• In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt vector is
a pointer to the Interrupt Vector Table.
– The Interrupt Vector Table occupies the address range from 00000H to
003FFH (the first 1024 bytes in the memory map).
– Each entry in the Interrupt Vector Table is 4 bytes long:
• The first two represent the offset address and the last two the
segment address of the ISR.
– The first 5 vectors are reserved by Intel to be used by the processor.
• The vectors 5 to 255 are free to be used by the user.
IVT 003FFH
Type FFH Interrupt (Available)
:- 003FCH
Available Interrupts
(224)
Type 21H Interrupt (Available)
00084H
Type 20H Interrupt (Available)
00080H
Type 1FH Interrupt (Reserved)
0007CH
Reserved Interrupts
(27)
1 KB

Type 05H Interrupt (Reserved)

00014H
Type 04H Interrupt (Over Flow)
00010H
0000CH Type 03H Interrupt (Break Point)
Type 02H Interrupt (NMI)
00008H
Type 01H Interrupt Dedicated Interrupts
00004H (Trap or Single step)
(05)
00003H
CS CSInterrupt
Type 00H
00002H
(Divide by Zero)
IP 00001H IP
00000H
 2 bytes 00002H 00003H
CS LSB CS MSB Type 0 or
INT 00 Interrupt
2 bytes 00000H 00001H
IP LSB IP MSB

Given a vector,
where is the ISR address
stored in memory ?

Offset = Type number X 4

Example:- INT 02h

Offset = 02 x 4 = 08
= 00008h
 256 Interrupts Of 8086 are Divided in To 3 Groups

1. Type 00 to Type 04 I nterrupts (5) -

These are used for fixed operations and hence are called
dedicated interrupts

2. Type 05 to Type 1F interrupts (27 )

Not used by 8086,reserved for higher processors like 80286
80386 etc.

3. Type 20 to Type FF interrupts (224)

Available for user, called user defined interrupts these can be
H/W interrupts and activated through INTR line or can be S/W
interrupts.
Dedicated interrupts (INT 0…..INT 4):
INT 0 (Divide Error)-
This interrupt occurs whenever there is division error i.e. when
the result of a division is too large to be stored. This condition
normally occurs when the divisor is very small as compared to
the dividend or the divisor is zero.
Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
INT 1 (Single Step)-
The microprocessor executes this interrupt after every
instruction if the TF is set.
It puts microprocessor in single stepping mode i.e. the
microprocessor pauses after executing every instruction. This is
very useful during debugging.
Its ISR generally displays contents of all registers. Its ISR
address is stored at location 1 x 4 = 00004H in the IVT.
 Dedicated interrupts
• INT 2 (Non mask-able Interrupt)-
– The microprocessor executes this ISR in response to an interrupt on the NMI
(Non mask-able Interrupt) line.
– Its ISR address is stored at location 2 x 4 = 00008H in the IVT.

• INT 3 (Breakpoint Interrupt)-

– This interrupt is used to cause breakpoints in the program. It is caused by
writing the instruction INT 03H or simply INT.
– It is useful in debugging large programs where single stepping is inefficient.
– Its ISR is used to display the contents of all registers on the screen. Its ISR
address is stored at location 3 x 4 = 0000CH in the IVT.
 Dedicated interrupts
• INT 4 (Overflow Interrupt)-
– This interrupt occurs if the overflow flag is set and the microprocessor
executes the INTO (Interrupt on Overflow) instruction.
– It is used to detect overflow error in signed arithmetic operations.
– Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

– Xxxxx
– Yyyyyy
– Zzzzz
– Hhhhh
– Jjjjjj
 Reserved interrupts (INT 5…..INT 1F):

These levels are reserved by Intel to be used in higher

processors like 80386, Pentium etc. They are not
available to the user.

Available interrupts (INT 20…..INT FF):

These are user defined, software interrupts.
ISRs for these interrupts are written by the users to
service various user defined conditions.
These interrupts are invoked by writing the instruction
INT n. Its ISR address is obtained by the microprocessor
from location n x 4 in the IVT.
 Conclusion
• The CPU executes program, as soon as a key is pressed, the Keyboard
generates an interrupt. The CPU will response to the interrupt – read the
data. After that returns to the original program. So by proper use of
interrupt, the CPU can serve many devices at the “same time”
INT 21H

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INT 10
Interrupts
• There are some extremely useful subroutines within BIOS or DOS that are available to the
user through the INT (Interrupt) instruction.

• The INT instruction is like a FAR call; when it is invoked

– It saves CS:IP and flags on the stack and goes to the subroutine associated with that
interrupt.

– Format:

• INT xx ; the interrupt number xx can be 00-FFH

– This gives a total of 256 interrupts

– Two of them are widely used: INT 10H and INT 21H

– Before the services of INT 10H and 21H is requested, certain registers must have
specific values in them, depending on the function being requested.
INT 10H
• INT 10H subroutines are burned into the ROM BIOS of the 80x86-based PC and
are used to communicate with the computer’s screen video.

00,00 00,79
•
12,39

24,00 24,79
Cursor Locations

• INT 10H Function 06 (Scroll Up Window)

– AL = number of lines to scroll (with AL=00, window will be cleared)
– BH = attribute of blank rows
– CH, CL = upper row, left column
– DH, DL = lower row, right column
INT 10H
• INT 10H function 02; setting the cursor to a specific location
– Function AH = 02 will change the position of the cursor to any location.
– The desired cursor location is in DH = row, DL = column
• EX. Write a program that clears the screen and sets the cursor at the center of
the screen
; clearing the screen
MOV AX, 0600H ;scroll the entire page
MOV BH, 07 ; normal attribute (white on black)
MOV CX, 0000 ; upper left
MOV AH, 03
MOV DX,184FH ; lower right
INT 10H MOV BH, 00
;setting the cursor at the center INT 10H
MOV AH,02 ; set cursor option
MOV BH, 00 ; page 0
MOV DL, 39 ;
MOV DH, 12 ;
INT 10H

• INT 10H function 03; get current cursor position

– Registers DH and DL will have the current row and column positions and CX
provides info about the shape of the cursor.
Thank You

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