UNIT 1 [ MPI ]

8085 Microprocessor – Functional Units 8085 consists of the following functional units −

Accumulator It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Arithmetic and logic unit As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
General purpose register There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like
B-C, D-E & H-L.
Program counter It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so that the program
counter points to the memory address of the next instruction that is going to be executed.
Stack pointer It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push
& pop operations.
Temporary register It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result
stored in the accumulator. These are the set of 5 flip-flops −
D7 D6 D5 D4 D3 D2 D1 D0
Sign (S) Zero (Z) Auxiliary Carry (AC) Parity (P) Carry (C)
Its bit position is shown in the following table − S Z AC P CY

Instruction register and decoder It is an 8-bit register. When an instruction is fetched from memory then it is stored
in the Instruction register. Instruction decoder decodes the information present in the Instruction register.
Timing and control unit It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −
• Control Signals: READY, RD’, WR’, ALE
 • Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
Interrupt control As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the control from the main
program to process the incoming request. After the request is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
Serial Input/output control It controls the serial data communication by using these two instructions: SID (Serial
input data) and SOD (Serial output data).
Address buffer and address-data buffer The content stored in the stack pointer and program counter is loaded into
the address buffer and address-data buffer to communicate with the CPU. The memory and I/O chips are connected to
these buses; the CPU can exchange the desired data with the memory and I/O chips.
Address bus and data bus Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O devices.

Interrupts in 8085 microprocessor In the 8085 microprocessor, an interrupt is a signal that temporarily
suspends the normal execution of a program and redirects the control to a specific interrupt service routine (ISR).
Interrupts allow the microprocessor to respond to external events, such as user input, system events, or hardware
signals, without the need for constant polling.
There are five interrupt signals in the 8085 microprocessor:
1. TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an external device, such as
a power failure or a hardware malfunction. The TRAP interrupt has the highest priority and cannot be
disabled.
2. RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software instruction. It
has the second highest priority.
3. RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software instruction. It
has the third highest priority.
4. RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software instruction. It
has the fourth highest priority.
5. INTR: The INTR interrupt is a maskable interrupt that is generated by an external device, such as a
keyboard or a mouse. It has the lowest priority and can be disabled.
When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its
current execution and program control is transferred to a sub-routine by generating CALL signal and after
executing sub-routine by generating RET signal again program control is transferred to main program from where
it had stopped. When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the
peripheral which is requesting for its service. Interrupts can be classified into various categories based on different
parameters:
1. Hardware and Software Interrupts – When microprocessors receive interrupt signals through pins
(hardware) of microprocessor, they are known as Hardware Interrupts. There are 5 Hardware Interrupts
in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP Software Interrupts are
those which are inserted in between the program which means these are mnemonics of microprocessor.
There are 8 software interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4,
RST 5, RST 6, RST 7.
2. Vectored and Non-Vectored Interrupts – Vectored Interrupts are those which have fixed vector
address (starting address of sub-routine) and after executing these, program control is transferred to that
address. Vector Addresses are calculated by the formula 8 * TYPE
Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting device
gives the address of sub-routine for these interrupts. INTR is the only non-vectored interrupt in 8085
microprocessor.
3. Maskable and Non-Maskable Interrupts – Maskable Interrupts are those which can be disabled or
ignored by the microprocessor. These interrupts are either edge-triggered or level-triggered, so they can be
disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a
non-maskable interrupt. It consists of both level as well as edge triggering and is used
Instruction for Interrupts –
1. Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are enabled following
the execution of next instruction followed by EI. No flags are affected. After a system reset, the
 interrupt enable flip-flop is reset, thus disabling the interrupts. This instruction is necessary to enable
the interrupts again (except TRAP).
2. Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop hence disabling
all the interrupts. No flags are affected by this instruction.
3. Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST
5.5) by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line.
First the required value is loaded in accumulator then SIM will take the bit pattern from it.
4. Read Interrupt Mask (RIM) – This instruction is used to read the status of the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the condition of the
mask bits for the interrupts. It also reads the condition of SID (Serial Input Data) bit on the
microprocessor.

8086 Microprocessor 8086 is a 16-bit microprocessor and was designed in 1978 by Intel. Unlike, 8085, an
8086 microprocessor has 20-bit address bus. Thus, is able to access 220 i.e., 1 MB address in the memory. It performs
arithmetic and logic operations. And an 8086 microprocessor is able to perform these operations with 16-bit data in
one cycle. Hence is a 16-bit microprocessor. Thus the size of the data bus is 16-bit as it can carry 16-bit data at a
time. The architecture of 8086 microprocessor, is very much different from that of 8085 microprocessor.

Block Diagram of 8086 Microprocessor The architecture of 8086 microprocessor is composed of 2 major units, the
BIU i.e., Bus Interface Unit and EU i.e., Execution Unit. The figure below shows the block diagram of the
architectural representation of the 8086 microprocessor:

Bus Interface Unit (BIU) The Bus Interface Unit (BIU) manages the data, address and control buses.The BIU
functions in such a way that it: 1) Fetches the sequenced instruction from the memory, 2) Finds the physical address
of that location in the memory where the instruction is stored and 3) Manages the 6-byte pre-fetch queue where the
pipelined instructions are stored.
An 8086 microprocessor exhibits the property of pipelining the instructions in a queue while performing decoding and
execution of the previous instruction. This saves the processor time of operation by a large amount. This pipelining is
done in a 6-byte queue. Also, the BIU contains 4 segment registers. Each segment register is 16-bit. The segments
are present in the memory and these registers hold the address of all the segments. These registers are as follows:

1.Code segment register: It is a 16-bit register and holds the address of the instruction or program stored in the code
segment of the memory.
Also, the IP in the block diagram is the instruction pointer which is a default register that is used by the processor in
order to get the desired instruction. The IP contains the offset address of the next byte that is to be taken from the
code segment.
2. Stack segment register: The stack segment register provides the starting address of the stack segment in the
memory. Like in stack pointer, PUSH and POP operations are used in this segment to give and take the data to/from it.
3. Data segment register: It holds the address of the data segment. The data segment stores the data in the memory
whose address is present in this 16-bit register.
4. Extra segment register: Here the starting address of the extra segment is present. This register basically contains
the address of the string data.
It is to be noteworthy that the physical address of the instruction is achieved by combining the segment address with
that of the offset address.

6-byte pre-fetch queue: This queue is used in 8086 in order to perform pipelining. As at the time of decoding and
execution of the instruction in EU, the BIU fetches the sequential upcoming instructions and stores it in this queue.
The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this queue. The queue
exhibits FIFO behavior., first in first out.

Execution Unit (EU) The Execution Unit (EU) performs the decoding and execution of the instructions that are
being fetched from the desired memory location.

Control Unit: Like the timing and control unit in 8085 microprocessor, the control unit in 8086 microprocessor
produces control signal after decoding the opcode to inform the general purpose register to release the value stored in
it. And it also signals the ALU to perform the desired operation.
ALU: The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU. The
result of the operation is stored in the desired register.
Flag: Like in 8085, here also the flag register holds the status of the result generated by the ALU. It has several flags
that show the different conditions of the result.
Operand: It is a temporary register and is used by the processor to hold the temporary values at the time of operation.
The reason behind two separate sections for BIU and EU in the architecture of 8086 is to perform fetching and
decoding-executing simultaneously.

Working of 8086 Microprocessor. when an instruction is to be fetched from the memory, then firstly its physical
address must be calculated and this is done at the BIU. The physical address of an instruction is given as:
PA = Segment address Χ 10 + Offset For example: Suppose the segment address is 2000 H and the offset address is
4356 H. So, the generated physical address is 24356 H. Here, the code segment register provides the base address of
the code segment which is combined with the offset address.
The code segment contains the instructions. Each time an instruction is fetched the offset address inside the code
segment gets incremented. So, once the physical address of an instruction is calculated by the BIU of the processor, it
sends the memory location by the address bus to the memory. Further, the desired instruction at that memory location
which is present in the form of the opcode is fetched by the microprocessor through the data bus.
Suppose the instruction is ADD BL, CL. But, inside the memory, it will be in the form of an opcode. So, this opcode
is sent to the control unit.
The control unit decodes the opcode and generates control signals that inform the BL and CL register to release the
value stored in it. Also, it signals the ALU to perform the ADD operation on that particular data.
It is noteworthy that in any instruction, like ADD BL, CL. BL denotes the destination of the result of the add
operation. This clearly shows that whatever, the operation is performed its result must be stored in the first register
i.e., BL for this particular example.
8085 microprocessor 8086 microprocessor
The data bus is 8 bits. The data bus is 16 bits.
The address bus is 16 bits. The address bus is 20 bits.
The memory capacity is 64 KB. Also, 8085 Can Perform Operation Up to 2 8 i.e. 256 numbers. A number greater
than this is to be taken multiple times in an 8-bit data bus.
The memory capacity is 1 MB. Also, 8086 Can Perform
operations up to 216 i.e. 65,536 numbers.
The input/output port addresses are 8 bits. The input/output port addresses are 16 bits.
The operating frequency is 3.2 MHz. The operating frequency is 5 MHz, 8 MHz, and 10 MHz.
8085 MP has a Single Mode Of Operation. 8086 MP has Two Modes Of Operation. 1. Minimum Mode
= Single CPU PROCESSOR 2. Maximum Mode = Multiple CPU PROCESSOR.
It does not have multiplication and division instructions. It has multiplication and division instructions.
It does not support pipelining. It supports pipe-lining as it has two independent
units Execution Unit (EU) and Bus Interface Unit (BIU).
It does not support an instruction queue . It supports an instruction queue.
Memory space is not segmented. Memory space is segmented.
It consists of 5 flags(Sign Flag, Zero Flag, Auxiliary Carry Flag, Parity Flag, and Carry Flag)
. It consists of 9 flags(Overflow Flag, Direction Flag,
Interrupt Flag, Trap Flag, Sign Flag, Zero Flag, Auxiliary Carry Flag, Parity Flag, and Carry Flag).
It is a low-cost Microprocessor It is a comparatively High-cost Microprocessor.
There are 5 Addressing Modes. There are 11 addressing modes.
There is no concurrency in Fetching, Decoding, and execution.
There is Concurrency in Fetching, Decoding, and
Execution because of the instruction queue.
It has almost 6500 transistors. It has almost 29000 transistors.

Pin diagram of 8085 microprocessor

The pins of a 8085 microprocessor can be classified into
seven groups −

Address busA15-A8, it carries the most significant 8-

bits of memory/IO address.
Data bus AD7-AD0, it carries the least significant 8-bit
address and data bus.
Control and status signals These signals are used to
identify the nature of operation. There are 3 control
signal and 3 status signals.
Three control signals are RD, WR & ALE.

RD − This signal indicates that the selected IO or

memory device is to be read and is ready for accepting
data available on the data bus.
WR − This signal indicates that the data on the data bus
is to be written into a selected memory or IO location.
ALE − It is a positive going pulse generated when a new
operation is started by the microprocessor. When the
pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M This signal is used to differentiate between IO
and Memory operations, i.e. when it is high indicates IO operation and when it is low then it indicates memory
operation.

S1 & S0 These signals are used to identify the type of current operation.

Power supply There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS indicates
ground signal.
Clock signals There are 3 clock signals, i.e. X1, X2, CLK OUT.
 • X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set frequency of the
internal clock generator. This frequency is internally divided by 2.
• CLK OUT − This signal is used as the system clock for devices connected with the microprocessor.

Interrupts & externally initiated signals Interrupts are the signals generated by external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We
will discuss interrupts in detail in interrupts section.

• INTA − It is an interrupt acknowledgment signal.

• RESET IN − This signal is used to reset the microprocessor by setting the program counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If READY is low, then
the CPU has to wait for READY to go high.
• HOLD − This signal indicates that another master is requesting the use of the address and data buses.
• HLDA (HOLD Acknowledge) − It
indicates that the CPU has received the
HOLD request and it will relinquish the
bus in the next clock cycle. HLDA is set
to low after the HOLD signal is removed.

Serial I/O signals There are 2 serial signals, i.e. SID

and SOD and these signals are used for serial
communication.

• SOD (Serial output data line) − The

output SOD is set/reset as specified by
the SIM instruction.
• SID (Serial input data line) − The data on
this line is loaded into accumulator
whenever a RIM instruction is executed.

Pin diagram of 8086 microprocessor

• The Intel 8086 is 40 pin DIP Microprocessor.

Here we will see the actual pin level diagram of
8086 MPU.
• 8086 was the first 16-bit microprocessor
available in 40-pin DIP (Dual Inline Package)
chip. Let us now discuss in detail the pin
configuration of a 8086 Microprocessor.
• This is the actual pin diagram of 8086
Microprocessor.
• Now let us see the Pin functions of the 8086
microprocessor.
Pins Function
AD15 – AD0 These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries
higher order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit data.
A16 – A19 These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address and later
it carries status signals.
Vcc It uses 5V DC supply at VCC pin 40
GND These are ground at VSS pin 1 and 20.
Clock Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
S7/BHE BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data
using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
Read(RD) It is available at pin 32 and is used to read signal for Read operation.
𝐑𝐞𝐚𝐝𝐲 It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to transfer data. When it is
low, it indicates wait state.
 RESET It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles to RESET the
microprocessor.
INTR It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.
NMI It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
TEST This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN/MX It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor
is to operate in; when it is high, it works in the minimum mode and vice-versa.
INTA It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
ALE It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address on the address/data
lines.
DEN It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.
DT/R It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of
data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicating the memory operation. It is available at pin 28.
WR It stands for write signal and is available at pin 29. It is used to write the data into the memory or
the output device depending on the status of M/IO signal.
HLDA It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges
the HOLD signal.
HOLD This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0 These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue.
S0, S1, S2 These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27, and 28.
LOCK When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0 These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has a higher
priority than RQ/GT1.

There are some conditions for QS0 and QS1. These conditions are as follows.

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

The S2, S1 and S0 are the status signals. Here is a list of status and their bit patterns.

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read
 S2 S1 S0 Status

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

Segmentation is the process in which the main memory of the computer is logically divided into different segments
and each segment has its own base address. It is basically used to enhance the speed of execution of the computer
system, so that the processor is able to fetch and execute the data from the memory easily and fast.
Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then
the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up
to 64kilobytes. But if another segment starts before this 64kilobytes location of the first segment, then
the two segments are said to be Non-Overlapped Segment.
Rules of Segmentation Segmentation process follows some rules as follows:
• The starting address of a segment should be such that it can be evenly divided by 16.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 Kb