International Journal of Advanced Technology and Engineering Exploration, Vol 5(44)

ISSN (Print): 2394-5443 ISSN (Online): 2394-7454

Research Article
http://dx.doi.org/10.19101/IJATEE.2018.545002

Area efficient SR flip-flop designed using 90nm CMOS technology

Akshay Malhotra1* and Rajesh Mehra2
ME Scholar, Department of Electronics & Communication Engineering, National Institute of Technical Teachers
Training & Research, Chandigarh, India1
Associate Professor, Department of Electronics & Communication Engineering, National Institute of Technical
Teachers Training & Research, Chandigarh, UT, India2

©2018 ACCENTS

Abstract
In this paper SR flip-flop is designed to reduce area and power using 90nm technology for efficient utilization of the
circuit. This is done using digital schematic (DSCH) and microwind application. Two designs have been proposed for SR
flip-flop, namely fully automatic and semicustom design. In fully automatic design inbuilt active devices are used along
with auto routing and placements. In semi-custom design inbuilt active devices are used with optimized manual routing
and placement. The proposed schematic in case of fully automatic approach is designed by using DSCH and its
equivalent layout is created using microwind. While in the case of semi-custom approach optimized layout is created with
microwind. It can be observed from the simulated results that power is reduced by 81% and area consumption is improved
by 15% in case of semi-custom design as compared to fully automatic design.

Keywords
Area, CMOS FET, Layout, Power, Sequential circuits, SR flip-flop.

1.Introduction Very-large-scale integration (VLSI) is the procedure

The primary objective of this S-R flip-flop design is of making an integrated circuit (IC) by integrating
to reduce the area so that the circuit fits into the many transistors into a single chip. All basic elements
required integrated circuit chip efficiently. like flip-flops, registers and memory elements fall in
Secondarily, this paper also aims to reduce the power this category [3]. Before the introduction of VLSI
consumed by the circuit for efficient utilization of technology, ICs could perform limited set of
power provided to the integrated circuit chip. functions. ICs have advantage of speed, size and
Sequential circuits are circuits in which output is power consumption over digital circuits. We have
determined by current inputs as well as past inputs number of different IC fabrication technologies. The
and thus they require memory. The combinational most important difference between technologies is
circuit does not use any memory. Hence the previous the types of transistors they can produce [4].
state of input does not have any effect on the present MOSFETs offer the advantage of drawing almost
state of the circuit. Sequential circuits have memory zero control current while idle [5]. They come in two
so output can vary based on given input. These type variants: pMOS and nMOS using n-type and p-type
of circuits use previous input, output, clock and a dopants respectively. An individual complementary
memory element. Sequential circuit designs use flip- metal–oxide–semiconductor (CMOS) transistor
flops or latches, which are sometimes called memory consumes very little energy each time it switches on;
elements that hold data. Sequential circuits are sorted the huge amount of transistors switching at very high
as bistable, mono stable and astable. Bistable states speed rate makes power utilization a major design
have two stable states, either of them can be attained consideration [6−10]. In this paper the estimation of
as per given conditions. Among the group of SR flip-flop‟s performance is done based on area
sequential circuits, the bistable circuits are the most measured.
popular ones. Timing elements such as latches, flip-
flops, registers, and memory storage cells form the Section 2 discusses the SR flip-flop. Section 3 shows
group of most important components in synchronous design schematic simulations; layout analysis is done
VLSI designs [1−2]. in section 4 followed by result comparison in section
5 and concluded in section 6.
*Author for correspondence

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2.SR flip-flop if clock is equal to logic „1‟ and those inputs will
The SR latch or SR flip-flop can be considered as a affect the outputs only when clock is active [13].
basic sequential logic circuit. This simple flip-flop is
a one-bit memory bistable device that has two inputs, 3.Schematic design simulation
one which will “SET” the device (meaning the output After designing the initial schematic circuit in Figure
= “1”), and is labelled S and one which will 1, we test the running of this circuit in DSCH for
“RESET” the device (meaning the output = “0”), further analysis. This testing is depicted in Figure 2.
labelled R. The SR stands for “Set-Reset”. The reset
input resets the flip-flop back to its original state with
an output Q that will be either at a logic level “1” or
logic “0” depending upon this set/reset condition
[11,12].

Figure 1 Clocked NAND based SR latch circuit

A basic NAND gate SR flip-flop circuit gives

Figure 2 Simulation of NAND based sr latch circuit
feedback through both its outputs back to its
opposing inputs and is commonly used in memory
circuits to store a single data bit [8]. Then the SR Further, then we study the timing diagram of the
circuit in DSCH and compare it with ideal circuit
flip-flop actually has three inputs, Set, Reset and its
timing diagram. This generated timing diagram is
current output Q related to its current state [6-7]. The
shown in Figure 3.
word “Flip-flop” is related to the actual operation of
the device, as it can be “flipped” into one logic Set
state or “flopped” back to the opposing logic Reset Table 1 shows the theoretical truth table of SR flip-
state. The NAND based SR latch is implemented by flop. In microwind, we simulate the file generated
from the DSCH and get the voltage vs current graph
combining the clock input as shown in Figure 1. The
for the circuit. This graph is shown in Figure 4.
inputs (S and R) and clock signal (Clk1) are active
low. It would mean that input signal will be nullified

Figure 3 Timing diagram of fully automatic

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Table 1 S-R flip-flop truth table

CLK S R QN ǬN+1 Operation
0 0 0 0 0 Not allowed
0 0 1 1 0 Set
0 1 0 0 1 Reset
1 x x Qn Ǭn Hold

Figure 4 Voltage vs current graph

4.Layout design analysis afterwards simulation is done. In this, 90nm foundry

In the first method the schematic of SR flip-flop is is selected. The Figure 5 represents the auto generated
designed, with the help of Microwind software the layout.
auto generated layout of SR flip-flop is created,

Figure 5 Fully automatic SR flip-flop

The layout is checked for DRC and if there no error is measured. Here the consuming power is 9.699
is generated then simulated result appears. Later µWatt. Area required for this particular layout is
generated timing waveforms are verified by 65.2µm2 .Width is 8.8 µm and height is 7.4 µm.
comparing to the circuit operation. The power Secondly we prepare layout using semicustom
generated is shown by the simulated result. The approach. In semicustom approach the transistors are
Figure 6 shows the timing diagram of this automatic inbuilt, in this approach connections are made by
layout. The power and area consumed by this layout following the lambda design rules. There is slight
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possibility of power reduction. Figure 7 represents simulation, is 1.852 µWatt, more than automatic
the layout using semicustom approach. The layout and area is calculated from the properties.
semicustom layout is checked for DRC if there is no Here the width is 6.8 µm (114 lambda) and height is
error present in layout, the circuit is simulated and 8.1 µm (135 lambda). In semicustom layout area is
timing waveforms are generated. The generated 55.4 µm2. Voltage versus current graph is shown in
timing waveforms are verified with the truth table or Figure 9.
operation of original circuit.
Figure 8 shows the timing diagram of semicustom
layout. The power observed from this particular

Figure 6 Timing diagram of fully automatic

Figure 7 Semi custom SR flip-flop

Figure 8 Timing diagram of semi-custom layout

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Figure 9 Voltage vs current graph

5.Result comparison Comparative analysis table (Table 2) shows that in

The performance of proposed semi-custom layout is terms of power the performance of semi-custom
compared with automated layout. The performance layout approach decreases. In terms of area and
parameters being area and power. power both the semi-custom layout has better
performance among the two design approaches.
Through above results a comparative study can be
done between the two designing approaches.

Table 2 Comparison table

S. No. Approach Area(µM2) Power(µWATT)
1. Fully Automatic 65.2 µm2 9.699 µWatt
2. Semi-custom 55.4 µm2 1.852 µWatt

From the above comparison we observed, there is a Acknowledgment

reduction of 81% in power for semicustom layout I would like to thank our honourable Director Dr. S.S.
generated in comparison to fully automatic layout Pattnaik, National Institute of Technical Teachers Training
and reduction of 15% in terms of area consumed. & Research, Chandigarh, India for constant motivation, co-
More area is required in auto generated approach. operation and support in pursuing my research work in ME
Regular Program.
Comparative analysis in terms of area is done, which
indicates that semi customized layouts have less area
Conflicts of interest
than auto generated [14, 15]. The authors have no conflicts of interest to declare.

6.Conclusion References
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[5] Raj P, Mehra R. Performance and analysis of T flip Akshay Malhotra received his
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proceeding 2015 (pp.1-4). Email: malhotraaki3@gmail.com
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Technology.2015; 2(5):169-72. Institute of Technical Teachers
[9] Weste NH, Harris D. CMOS VLSI design: a circuits Training & Research, Chandigarh,
and systems perspective. Pearson Education India; India. He has received his Doctor of
2015. Philosophy and Masters Degree in
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fundamentals. Pearson; 2013. Engineering from Punjab University, Chandigarh, India.
[11] Aggarwal D. Review of flip-flop. Journal of Basic Dr. Mehra has completed his Bachelor of Technology from
Applied and Engineering Research. 2014; 1(10):4-19. NIT, Jalandhar, India. Dr. Mehra has 22 years of Academic
[12] Wolf W. Modern VlSI design. Second Edition. Experience along with 10 years of research experience. He
Prentice Hall;1994. has nearly 500 publications in refereed peer reviewed
[13] Gupta P, Mehra R. Low power design of SR flip-flop international journals and international conferences. Dr.
using 45nm technology. IOSR Journal of VLSI and Mehra has guided more than 100 PG scholars for their ME
Signal Processing. 2016; 6(2):54-7. thesis work and also guiding 03 independent PhD scholars
[14] Kaur U, Mehra R. Low power CMOS counter using in his research areas. His research areas include VLSI
clock gated flip-flop. International Journal of Design, Digital Signal & Image Processing, Renewable
Engineering and Advanced Technology. 2013; Energy and Energy Harvesting. He has authored one book
2(4):796-8. on PLC & SCADA. Dr. Mehra is senior member of IEEE
[15] Rajasri K, Bharathi A, Manikandan M. Performance and Life member ISTE.
of flip-flop using 22nm CMOS technology.
International Journal of Innovative Research in
Computer and Communication Engineering. 2014;
2(8):5272-6.

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