Computer Architecture

PCC-CS402

Day: 6
Date: 19.02.2025
Topics to be Covered:

• Pipeline Processor
• Classification of pipeline organization in computer
• Instruction Pipeline
• Limitation of Instruction Pipeline
Learning Objective:

• After this lesson students will be able to get a overview of pipeline processor,
different organization of pipeline processor in computer also detailed description
of instruction pipeline configuration and its limitation.
Course Outcome:

• PCC-CS402.2 : Design basic and intermediate RISC pipelines, including

the instruction set, data paths, and ways of dealing with pipeline hazards.
Applying (Level III).
 Pipeline

• There are three major area of computer design where the pipeline organization
is applicable.
• Instruction pipelines,
• Arithmetic pipelines and
• Memory-access pipelines

• An Instruction pipeline operates on a stream of instructions by overlapping

and decomposing the fetch, decode and execute phases of the instruction
cycle. One of the major contributor to achieve RISC’s high performance.
• An arithmetic pipeline divides an arithmetic operation into sub-operation for
execution in the pipeline segments.
• A Memory-access pipeline is operated using separate instruction and data
caches to minimize delays due to availability of data for arithmetic operation
instruction.
Instruction Pipeline:
• An m-stage instruction pipeline thus can overlap the processing of a
maximum of m instruction.
• A typical instruction execution under pipeline architecture consists of
a sequence of operation , including instruction fetch, decode, calculate
operand address, fetch operands, execute and write back operand
phases.
• The design of the instruction pipeline will be most efficient if the
instruction cycle is divided into segments of equal duration.
 i) Fetch Instruction(FI): Read the next expected
instruction into a buffer (prefetch buffer) from a
cache memory
ii) Decode Instruction/Register fetch(DI):
Determine the opcode and the operand specifier.
Access the register file to read the registers. The
output of the general-purpose registers are put
into temporary registers.
iii) Calculate operand address(CO): Calculate the
effective address of each source operand.
iv) Fetch operand/memory Access(FO): Access
memory, if needed, to fetch each operand. For a
load instruction, data returns from memory and
placed in the LMD (Load memory Data) register.
If it is store, then data from register is written into
memory. Operand in registers need not be fetched.
v) Execute Instruction(EI): The ALU perform the
indicated operation on the operands prepared in
the prior cycle and store the result, if any , in the
specified destination operand location.
vi) Write Back (Operand) (WB): Write the result
Flow-chart of an instruction pipeline consisting of into the register file or store the result in memory.
six stages.
 Limitation:
• If all the stages of a pipeline are not equal duration , there will be some
waiting involved at various pipeline stages.
• If amount of workload assign to a stage in the pipeline is too much, the time
taken to complete the operation at that stage become unacceptably long.
This relatively long time spent at one stage will inevitably create a
bottleneck in the pipeline. The pipeline operation in this situation called
stalled.
• Some type of instruction do not require all the stages and hence some stages
are skipped.
• Resource conflicts: This is caused when two or more stages/segments
(FI,FO,WB) may involve a memory access at the same time, causing one
segment to wait until another is completed.
• Another difficulty is called the fetching problem that arises due to the
presence of the conditional branch instruction. This instruction can cause to
invalidate several instructions previously fetched and already under
operation in prior stages.
• Figure depicts the effects of conditional branch.
• Instruction 4 is a conditional branch instruction to instruction 12.
• Until the I4 is executed there is no way of knowing which instruction will come next.
• The pipeline as usual simply loads the I5 in sequence and proceeds through the stages.
• The branch has not been taken till 8th time unit has determined the branching.
• At this point the pipeline must clear off instructions 5 to 8 that are not useful.
• Killing (draining) off the instructions currently in the pipeline sometimes called squashing is
required and start over afresh.
• During time unit 9, the instruction 12 enter the pipeline.
• No instructions are completed during time unit 10 to 13. This happen due to the fact that we could
not anticipate the branch which leads to a situation of performance penalty.
• An unpredictable event is an interrupt which forces the pipelining to
leave user instruction already in pipeline and start executing the
interrupt service routine instructions.
Any Question?

Thank You