American International University-Bangladesh

Department of Electrical and Electronic Engineering

EEE4217: VLSI Circuit Design Laboratory

Title: I-V Characteristics of MOS transistors

Objective:
To gain insights into the operation of MOSFETs.

Theory and Methodology

Part-1: SPICE Simulation of Circuits -SPICE History

CANCER:
In early 1970s, Ron Rohrer intended to develop a simulation program at the University of California
Berkley. Rohrer's students, including Larry Nagel, created the CANCER simulator—Computer
Analysis of Non-Linear Circuits Excluding Radiation. It performed DC, AC and Transient Analysis;
components include diodes (Shockley equations) and bipolar transistors (Ebers-Moll equations). Other
simulation programs of the day included IBM's ECAP and Autonetics TRAC.

SPICE1:
In 1972, Nagel and Pederson released PICE1 (Simulation Program with IC Emphasis) into the public
domain. SPICE becomes industry standard simulation tool. In addition to Bipolar transistors—BJTs,
JFET and MOSFET devices were added. The program (and simulation) was based on Nodal Analysis.
It was written in FORTRAN code running on large main frame computers. The cover page of the
original SPICE paper written in 1972 is shown on page2, available now at University of California at
Berkeley at the web address:
http://www.eecs.berkeley.edu/Pubs/TechRpts/1973/22871.html

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SPICE2:
In Nagel's 1975 release offers significant improvements. It included Modified Nodal Analysis (MNA),
replacing the old analysis, now supports voltage sources and inductors. Memory was dynamically
allocated to accommodate growing circuit size and complexity. It has adjustable time-step control
speeds simulation. MOSFET and bipolar models were overhauled and extended. Version SPICE2G.6
(1983) is the last FORTRAN version (still available today from Berkeley). Many commercial simulators
today are based on SPICE2G.6.

SPICE3:
In 1985, SPICE code was rewritten in the C programming language. It now featured a graphical
interface for viewing results. It includes polynomial capacitors, inductors and voltage controlled
sources. This new version eliminated many convergence problems. New added models included
MESFET, lossy transmission line and non-ideal switch. Improved semiconductor models
accommodated smaller transistor geometries. It was not backward compatible with SPICE2.

1980's AND BEYOND

In the 1980’s commercial versions of SPICE that were released included HSPICE, IS_SPICE and
MICROCAP. MicroSim releases PSPICE, the first PC version of SPICE. MicroSim was later bought
by Cadence Design Systems (http://www.cadence.com). SPICE started to attract many more users in
industry and academia than before. Companies started to integrate SPICE versions to their schematic
entry and layout packages. Ngspice was developed in 1993 by Paolo Nenzi and others. It is still
maintained by a team of developers. Ngspice is an open-source SPICE simulator and is based on the
latest stable release of Berkeley SPICE, version 3f.5.

SPICE Availability:
The free student version of SPICE—ORCAD PSPICE Student—from Cadence Design Systems used
to be available at their website. They do not seem to offer it at this point. However, they do offer an
evaluation version that includes PSPICE, which is called Cadence ORCAD Demo Software that
includes only Schematic and PSPICE, at
http://www.cadence.com/products/orcad/pages/downloads.aspx#pspice. One needs to create an
account there to download this evaluation software. The PSPICE Student (version 9.1) software,
however, is still legally available at many academic sites such as at University of Kentucky’s College
of Engineering—http://www.engr.uky.edu/~cathey/pspice061301.html. The open-source Ngspice is
available at Sourceforge at https://sourceforge.net/projects/ngspice/files/ng-spice-rework/

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Part-2: SPICE Simulation of Circuits-A Short Introduction to SPICE:

To simulate the performance of the circuit, the various nodes are identified (e.g., 1,2,3) and each device
is given a unique name (e.g. Mpu, Cload, Mpd). The circuit can now be simulated in SPICE by a set of
program statement stored in a data file. A typical input file consists of a title line, a set of element
statements that describe the circuit, and a set of control statements that instruct SPICE during program
execution. The entire input file must be terminated by an .END control statement. Input line in which
the first character is an asterisk (*) are interpreted as comment line. Detailed rules for circuit description
and control statements are described below.

Rules for circuit description

1. Node identifiers or numbers must be non-negative integers.

2. The ground node (0 Volts) must be numbered zero.
3. Device names can be up to 8 characters in length.
4. The first letter of a device name identifies the device type, e.g. ‘R’ for resistance, ‘C’ for capacitor,
‘M’ for MOSFET, ‘V’ for independent voltage source and ‘I’ for independent current source.
5. Values can be expressed as integers or floating point numbers, the following abbreviations may be
employed:
t: 1e12 k: 1e3 n: 1e-9
g: 1e9 m: 1e-3 p: 1e-12
meg: 1e6 u: 1e-6 f: 1e-15
6. Comments can be inserted into the circuit description by beginning the statement with an ‘*’ as
the first character.

Writing your circuit description:

Use the following as a template to write a description:
(title)
∗ Spice options:
∗ To limit width of output to 80 characters- useful for ttys.
.width out = 80
∗ To suppress page ejects and printout of model parameters.
.options nopage nomode
∗ Circuit description (See Circuit Element Description):
….
….
∗ Model specification (see Circuit Element Description):
….
….
∗ Input signals (see Signal Source Description):
….
….
∗ Simulation modes:
….
….
∗ Generating outputs
….
….
∗ End of simulation:
.end

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Circuit Element Description:

Resistor and Capacitors:

General Form: Devicename n1 n2 Value
where Devicename is rxxxxxxx for a resistance, cxxxxxx for a capacitor.
n1, n2 are the node numbers of the device terminals.
Value is the resistance in ohms or capacitance in Farads.

MOSFETs:
General Form: Devicename n1 n2 n3 n4 model name l w
where Devicename is mxxxxxx
The nodes in order are drain, gate, source and substrate
l and w are channel length and width (in meters) respectively.

e.g.
mpu 2 1 3 2 penh l=3u w=10u
mpd 3 1 0 0 nenh l=3u w=4u

Note that the substrate of the p-type enhancement device is connected to the positive supply whereas
that of the n-type enhancement device is connected to the ground node.

Model name:
The simulator needs detailed information on the technology being simulated. The MOSFET model in
SPICE 2G5 permits 37 different parameters to be set in order to describe the target technology. These
parameters are included in a ‘model’ statement and the model name refers to the required model. The
models of the CMOS p and n type enhancement mode transistors provided here following this
introduction are values derived by the fabricators for this particular CMOS technology and should be
included in the circuit description file.

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Part-3: MOS I-V Characteristics

MOS is the building block of digital circuits. Complimentary MOS or CMOS is the most
widely used logic family that is used to construct digital circuits. CMOS logic utilizes n-type
MOS or NMOS for pull-down and PMOS for pull-up.

MOS is a voltage-controlled device where voltage applied to the gate terminal changes the
doping type of a region underneath the gate-oxide (typically SiO2) called channel, which is not
electrically connected to the gate. When the channel gets inverted, a conductive region forms
between drain and source terminal. In an NMOS, drain and source are n-type and the channel
changes from p to n type during inversion. In PMOS, drain and source are p-type and the
channel changes from n to p type during inversion. With the channel inverted, current can flow
between drain and source if there is a positive drain voltage, i.e., there is a voltage difference
between drain and source terminals.

When gate voltage is kept constant, one can observe how the drain current varies against drain
voltage. For different gate voltages, this process can be repeated. This current-voltage
characteristic is a fundamental feature of MOS. One can observe from the following figures
that MOS operates in 3 regions. In cut-off region (when gate voltage is below the threshold
voltage), MOS does not produce drain current, as channel does not exist. In linear region, drain
current increases linearly with drain voltage. In saturation region, current stays largely constant
despite change in drain voltage.

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When drain voltage is kept constant, one can observe how the drain current varies against gate
voltage. For different drain voltages, this process can be repeated. One can observe from the
above figure that drain current increases exponentially after gate voltage crosses the threshold
voltage, however the current level depends on the chosen drain voltage.

Apparatus:
 A Windows PC
 Ngspice Simulator

Precautions
Ensure Windows Security of your PC is activated to ensure the PC is free of virus.

Experimental Procedure

1. Draw an NMOS with voltage sources connected to its drain and gate terminals.
Annotate the nodes of the circuit.
2. Write NGSPICE code to produce the current-voltage characteristics (I-V
characteristics) for an NMOS for constant gate voltage. Consider a 180 nm CMOS
process, where gate length = 180nm and gate width = 200nm, Vgs = 2V and Vds varies
between 0 to 2V.
3. Write NGSPICE code to produce the current-voltage characteristics (I-V
characteristics) for an NMOS for constant drain voltage. Consider a 180 nm CMOS
process, where gate length = 180nm and gate width = 200nm, Vds = 2V and Vgs varies
between 0 to 2V.

Simulation and Measurement

1. Simulate current-voltage characteristics (I-V characteristics) for the NMOS described

in Step 2 of experimental procedure.
2. Simulate current-voltage characteristics (I-V characteristics) for the NMOS described
in Step 3 of experimental procedure.
3. Repeat steps 1 and 2 for a PMOS in a 180 nm CMOS process, where gate length =
180nm and gate width = 400nm.

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Question to be answered on the report
Can you estimate threshold voltage (VTH) from the I-V plots?

Discussions and Conclusions

Interpret the data and the plots. Write down what you learnt about MOS I-V characteristics from the
data and the plots.

Reference

1. http://www.cadence.com/products/orcad/pages/default.aspx

2. Orcad PSpice A/D User’s Guide

3. http://www.eecs.berkeley.edu/Pubs/TechRpts/1973/22871.html

4. https://ngspice.sourceforge.io/index.html

5. Ngspice User Guide (https://ngspice.sourceforge.io/docs/ngspice-43-manual.pdf)

6. CMOS VLSI Design A Circuits and Systems Perspective, 4th Edition, Neil Weste, David
Harris, 2011.

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