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EE67031 Lab 2 Report: Power Amplifier design

and Fabrication
Joshua Mathis

Abstract—A class AB power amplifier is designed to function However, these Bias Tees are frequency dependent, meaning
from 2.4 GHz to 2.5 GHz. A stability network was implemented other frequencies will be able to travel through it. They are
using a parallel resistor and capacitor to guarantee that the usually addressed by adding capacitors on the other side of
power amplifier would be unconditionally stable. Bias Tees were
designed for the gate and drain of the transistor to isolate the Bias Tee to short them to ground.
the RF signal from the DC biasing circuitry. The Bias Tees Once the PA is both stabilized and properly biased, match-
resulted provided -76 dB of isolation at the center frequency. To ing networks need to be added to the input and the output
maximize the PAE, gain, and output power, matching networks to allow for the PA to function properly with the 50 Ω
are designed with open stubs to present the optimal source and transmission line connecting it to the rest of the system. For
load impedances as given by the datasheet of the transistor. The
circuit is then realized with a linear gain of 16.16 dB, a PAE of a PA, the impedance presented to the output, known as the
35.2%, an OP1dB of 31 dB, and is shown to output 40 dBm with load impedance, is important in determining its power added
an input of 29 dBm. The performance of the realized amplifier efficiency (PAE) and gain. The PAE describes how effeciently
resembles that of the simulated design with a 1.2 dB decrease the PA converts the DC power into power it has added to the
in gain and OP1dB, and the frequency shifts down by 15 Mhz, RF signal. The equation for PAE can be seen in eq. (1), where
with a 20 MHz increase in bandwidth.
Pout represents the RF power out, Pin represents the RF power
in, and PDC represents the DC power in. This is an important
I. I NTRODUCTION parameter as more efficient PAs not only save on operating
costs, but also produce less heat that needs to be extracted.
T HIS lab’s purpose was to design and fabricate a power
amplifier (PA) that would be capable of outputting 10 W
of power. The previous lab in this class focused on the design PAE =
Pout − Pin
× 100% (1)
PDC
of a receiver that could receive any of the various WiFi
channels. That design utilized a low noise amplifier and an To find the correct load impedance to present to the biased
RF gain amplifier to be able to amplify the small signal that transistor, the designer should perform a load-pull test that
would be received, while contributing the least amount of sweeps various load impedances and calculates the gain and
noise possible. In contrast, a PA is designed to be used in PAE for each impedance. Then the designer would choose
a transmitter by outputting a large amount of power so that the impedance with desired balance between the two. This
the transmitted signal can travel further. This specific PA was test is rather involved, and if time is a constraint, many
designed for a center frequency of 2.45 GHz, and a 100 MHz manufacturers perform this test for various frequencies and
bandwidth, allowing it to send any of the WiFi channels. All provide the results within their datasheets. This design will use
of the design work for this project was done using Keysight’s the load impedance given within the datasheet of the transistor.
Advanced Design Suite (ADS). The final part to the PA is the input matching network. To
allow for maximum power transfer, the impedance that should
II. D ESIGN T HEORY be presented to the input, known as the source impedance,
should be the complex conjugate of the input impedance
When developing a PA, there are multiple sections in the corresponding to the chosen load impedance. This value is also
design. First, the amplifier has the potential to be unstable provided in the datasheet and will be utilized in this design.
at any of the frequencies at which it has gain. Therefore, a
simulation must be run to determine its stability across these
frequencies. If an amplifier is unstable, it will begin to oscillate III. S TABILITY
frequencies that are undesirable. This can be mitigated in a The transistor being used in this design is the CREE
variety of ways, but they fundamentally amount to lowering CGH40010, with the corresponding datasheet seen in [1]. To
the overall gain of the system at the bands that are of less test this transistor for stability, a simulation was setup in ADS
importance. using a provided model of the transistor and a terminal at the
Once the PA is stable, it needs to be biased to allow it to turn input and the output. Then, specific functions were used to
on and provide gain to the RF signal. This is accomplished plot the stability circles and the µ for each port. The stability
through the use of Bias Tees. A Bias Tee will allow the DC circles show what impedances on the Smith chart, that when
voltage to reach the transistor without allowing the RF signal presented, would result in an unstable system if they would
to interact with the DC circuitry. This means that the trace fall within the circle. The µ value of each circle is another
for the DC bias needs to appear as an open circuit to the way of determining the stability at each frequency, and it
RF signal, keeping the signal from traveling up the Bias Tee. is calculated using the scattering parameters (S-Parameters),
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which is shown in eq. (2). If µ has a value larger than 1, then

that frequency will not effect the system’s stability. The goal is
that the stability circle at every frequency would be completely
outside of the Smith chart, meaning that they would all have
a µ with a value greater than 1.
1 − |S11 |2
µ= ∗ | + |S S | > 1. (2)
|S22 − ∆S11 12 21
Initial simulations showed that all frequencies below
3.9 GHz had a µ less than 1, meaning that they could be
potentially unstable. To address this, a 100 Ω resistor and
a 2 pF capacitor were put in parallel at the gate of the
transistor, resulting in the µ of all frequencies from 0.5 GHz
to 6 GHz rising above 1. Therefore, no matter the value of
the impedances presented at the input or output, the transistor
should be unconditionally stable.

IV. DC B IASING AND B IAS T EES Fig. 1. I-V curve of the CGH400100 with the gate voltage varying from -1 V
to -3.5 V.
When choosing the proper voltages to apply to the gate
and the drain of the transistor, it is important to consider the
desired class of operation. The three main classes of operation
for an amplifier are class A, class B, and class AB. Class A
results in the least distortion of the signal, allowing there to
be conduction through 360◦ of the incoming signal. However,
this is also the least efficient of the three, often 25% to
50%, resulting in the most power dissipated as heat. Class
B is the most efficient of the three, up to 78.5%, but this is
accomplished by limiting the conduction of the incoming RF
signal to 180◦ . Class AB is a mixture of the two, allowing for
conduction being anywhere between classes A and B, resulting
in an efficiency between the two. This design is a class AB
amplifier with a conduction angle of 270◦ .
The class of the amplifier is determined by the biasing on Fig. 2. Bias Tee design using a radial stub, and a capacitor as a DC block.
the gate of the transistor. To determine the proper biasing, an
ADS simulation was provided and was used to show the effects
of different gate bias voltages. This simulation resulted in a keep the DC circuitry from affecting the RF signal, and the
plot of the drain voltage plotted against the drain current with DC block would prevent the DC voltage from harming any
a range of gate voltages. This plot can be seen in Fig. 1, where other components connected to the amplifier. In this design,
the gate voltage is varied from -1 V to -3.5 V. The gate needs the RF choke was implemented using open ended radial stubs
a negative voltage because this transistor is a depletion mode that would connect to the main microstrip transmission line
transistor. This means that the channel from the drain to the with a quarter wavelength long trace. This trace also used
source is on by default, and a negative voltage must be applied an increased impedance of 90 Ω to attempt to improve the
to turn the transistor off. It was decided to bias the transistor isolation of the RF from the DC circuitry. Using the LineCalc
to have a drain current of 200mA, which resulted in a gate tool in ADS, and taking into account the Rogers 4530B 30 mil
bias of -2.7 V. In Fig. 1, the black line shows how the RF thick substrate, the main 50 Ω microstrip was determined to
signal would swing the drain voltage down to the maximum be 64.8 mil wide, and the 90 Ω trace was 20 mil wide. Both
current at VDS of 6 V, then up into cutoff at about 32 V. The the input and the output used the same Bias Tee design, which
gate bias point would then be the center, allowing for the drain can be seen in Fig. 2. The S2P device is using the S2P data of
voltage to swing from 6 V to 50 V. This point is known as a capacitor provided by the manufacturer, and is present to act
the quiescent point. as a DC block. The corresponding S-Parameters can be seen
With the DC bias point having been chosen, the Bias Tees in Fig. 3, where the S31 represents the isolation of the Bias
can be designed. The first concern for a PA’s Bias Tee would Tee that reached -76 dB at the center frequency of 2.45 GHz.
be the relatively high current to travel through the trace, but
by ensuring that the traces were large enough for the lab’s
milling machine the traces would be large enough to disregard
this concern.
The Bias Tees would need to include an RF choke and
a DC block. The RF choke was the component that would
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Fig. 3. S-Parameters of the Bias Tee with the isolation reaching -76 dB at Fig. 4. S-Parameters of the output matching network with an S11 of -30 dB
the center frequency of 2.45 GHz, with an S11 of -24.8 dB. at the center frequency.

V. I MPEDANCE M ATCHING
The output matching network was designed to present the
desired load impedance as given by the datasheet, which was
19+j9.2 Ω [1]. This was accomplished by using two terminals
in ADS, one set to have a characteristic impedance of 50 Ω,
and the other to have the desired impedance. Then the Bias Tee
and the DC block were placed in between them. This allowed
the matching network to be able to account for the effects that
these components would contributed to the impedance actually
presented to the drain of the transistor. The Smith chart tool
in ADS was used to determine the needed components of
the matching network, which were a length of line and an
open circuited stub. These would first be implemented as ideal
transmission lines to confirm the design was correct. Then
a Tee intersection was added, and parametric sweeps were
performed to optimize the lengths of the the line and the Fig. 5. S-Parameters of the input matching network with an S11 of -21.2 dB
at its shifted center frequency of 2.55 GHs, and the insertion loss is also
stub to account for the effects of the Tee intersection. Once 1.8 dB at that frequency.
optimized, the ideal transmission lines were replaced with
realistic microstrip line models, and the optimization process
was repeated. The design resulted in the S-Parameters that can of 1.8 dB. This is caused by the RC stability circuit that does
be seen in Fig. 4, where the S11 was as low as -30 dB at the ensure stability, but results in some attenuation of the desired
center frequency, and the insertion loss was only 0.22 dB. signal band.
The input matching network was designed using the same
process as the output matching network, attempting to present VI. F INALIZED D ESIGN
the desired source impedance of 3.9 − j4.2 Ω. This network With all of the components completed, the amplifier was
also used a length of line and an open circuited stub. How- assembled in ADS. The S-Parameters are shown in Fig. 6,
ever, even though the resulting S-Parameters of the matching where a gain of 17.35 dB, and an S11 of -17.5 dB were realized
network were centered upon the correct frequency, once it at 2.45 GHz. The datasheet of the transistor shows an example
was added to the rest of the circuit, the center frequency PA that the manufacturer designed, and much of the band of
of the system shifted down by about 100 MHz. To correct interest had an S11 of about -7.5 dB. Usually -10 dB is a
this issue, parametric sweeps were repeated to optimize the standard maximum value of S11 for a device, but the PA is
input matching network for the correct center frequency. This attempting to optimize for PAE, gain and output power, so
resulted in the S-Parameters shown in Fig. 5, where the center sacrificing some power loss at the input can result in better
frequency of the network is actually 2.55 GHz to account for overall results. Based upon this as a criterion for a maximum
the overall downshift in frequency. This network had a good S11 , this PA would have a bandwidth of about 70 MHz from
S11 of 21.2 dB at its center frequency, but the insertion loss 2.415 GHz to 2.485 GHz with an S11 of -7.15 dB. Which
was significantly more than the output network with a value would allow for transmission of WiFi channels 4 through 13.
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resulted in a calculated output referenced third order intercept

point (OIP3) being 42.15 dBm.

VII. R EALIZED D ESIGN L AYOUT AND T ESTING

Once the design was verified, the layout was made using the
layout tool in ADS, and can be seen in Fig. 8. This layout in-
cludes all aforementioned parts of the design. Once completed,
the instructor added the necessary traces and pads for the DC
circuitry above the Bias Tees. In the lower left of the layout
can be seen a symbol called ”Ligma”. This was added because
it automatically increases the coolness factor of the realized
device by over 1000%, which is an often overlooked factor
when attempting to optimize the performance of a quality RF
device.
With the layout completed, the PCB was made using a
PCB milling machine to remove the copper everywhere except
for the specified places, and drill holes for mounting to the
Fig. 6. S-Parameters of the final amplifier design in class AB bias. With a
gain of 17.35 dB at the center frequency, a functioning bandwidth of 70 MHz heatsink. Then, the board was attached to the heatsink, the
from 2.415 GHz to 2.485 GHz with an S11 of -7.15 dB, and an S11 of - lumped components, the transistor, the SMA connectors, and
17.5 dB at 2.45 GHz. the DC bias wires were soldered to the PCBs. The realized
PA can be seen in Fig. 9.
Initial oscillation testing without an input resulted in the PA
oscillating significantly across all frequencies below 2 GHz.
This was found to be caused by a mistake in implementing
the ground connection of the DC power supply. The team had
forgotten to add copper tape to connect the DC ground pads to
the rear of the PCB, and instead used the ground of the SMA.
After adding the copper tape, the oscillations disappeared and
the PA output no signals from DC to 6 GHz without an input.
The PA was tested with a vector network analyzer (VNA)
and the measured S-Parameters can be found in Fig. 10. The
center frequency shifted down from 2.45 GHz to 2.43 GHz,
with a gain of 16.16 dB, and an S11 of -29.44 dB. Based upon
the desired S11 being -7.4 dB or below, this PA would function
from 2.38 GHz to 2.47 GHz, which would still allow for the
transmission of WiFi channels 1 through 10. When comparing
with the simulated results, the gain was not as high, decreasing
by 1.19 dB. However, the S11 at the center frequency improved
Fig. 7. Input power plotted against output power from 0 dBm to 30 dBm.
The OP1dB being 32.22 dBm, and a 40 dBm output requiring an input of by nearly 12 dB, and while it did shift down by 15 Mhz, the
26 dBm. bandwidth also increased by 20 MHz.
To test the linearity and power capabilities of the PA, data
points were collected to plot the input power versus the output
To ensure that the design was optimal before realizing, a
Harmonic Balance simulation was run to sweep the input
power from 0 dBm to 30 dBm at 2.45 GHz. The resulting
input power versus output power curve can be seen in Fig. 7,
where the output referenced 1 dB compression point (OP1dB)
was found to be 32.22 dBm. To reach the desired 10 W, or
40 dBm, output, an input of about 26 dBm was required. This
is because there was about 3 dB of compression with this high
of an output power, but this is expected for a PA. However,
after only about 1 dB past 40 dBm, it can be clearly seen that
the PA had completely saturated, resulting in nearly no more
output power with the increase in the input power.
While the lab did run out of time to run a two tone test on
the realized PA in the lab, this test was run on the simulated
PA. This was performed with an input power of 0 dBm for
both tones, which were at 2.43 GHz and 2.46 GHz. This test Fig. 8. Completed layout of the PA without DC biasing circuitry.
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Fig. 11. PIn -POut curve of the realized PA circuit. Showing an OP1dB of
Fig. 9. Realized PA circuit with all components attached and mounted to the 31 dBm.
heatsink.

Fig. 10. S-Parameters of the realized PA circuit. Resulting in a gain of

16.16 dB, and an S11 of -29.44 dB, at a center frequency of 2.43 GHz. Fig. 12. PIn -POut curve of the realized PA circuit in class A bias. Showing
an OP1dB of 38 dBm.

power. This would require inputting nearly 1 W of power to be 38 dBm, and an output of 40 dBm required an input of
the PA, so a driving amplifier was used to amplify the signal 28 dBm. Switching from class AB to class A interestingly
from the signal generator. This signal would feed the PA, resulted in the 1 dB compression point being raised by 7 dB,
then travel through 20 dB worth of attenuators and measured which makes sense considering how much larger the signal can
by a spectrum analyzer. All of the losses of the attenuators be without clipping in class A. To get an output of 40 dBm, an
and cables, and the true gain of the driving amplifier were input power of 28 dBm was required. The DC power supply
accounted for in the recording of the input and output powers. provided 28 V and 1 A, which is 28 W of DC power. With
The resulting PIn -POut curve can be seen in Fig. 11, where the an input of 0.63 W of RF power, 9.37 W of RF power was
OP1dB is shown to be 31 dBm, and an output of 40 dBm added to the signal. This would result in a PAE of 33.5%. This
required an input of 29 dBm. When outputting 40 dBm, the is lower than the class AB PA, which follows the theory of
DC power supply was providing 28 V and 0.933 A, which amplifier classes.
is 26.124 W of DC power, and there was about 0.8 W of Table. I, shows the primary parameters of the simulated
RF power at the input. This means that 9.2 W of DC power and realized PAs, including the aforementioned differences of
was converted to RF power, which results in a PAE of 35.2%, center frequency and bandwidth. The realized PA had about
using 1. Which is within the expected range for a class AB 1.2 dB lower gain and OP1dB. The required input for the
amplifier. desired 40 dBm output was 3 dBm more for the realized
This test was repeated after changing the gate bias such PA. Overall, the performance of the PA is very close to the
that the PA would behave as a class A amplifier. The PIn -POut simulated results, and this could be considered a successful
curve can be seen in Fig. 12, where the OP1dB is shown to design.
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TABLE I
C OMPARISON OF THE S IMULATED PA AND THE R EALIZED PA.

Simulated PA Realized PA
Linear Gain (dB) 17.35 16.16
OP1dB (dBm) 32.22 31
Input for 40 dBm output 26 29
Center Frequency (GHz) 2.45 2.35
Bandwidth (MHz) 70 90

VIII. C ONCLUSION
A class AB power amplifier was designed to function with a
center frequency of 2.45 GHz, and a bandwidth of 100 MHz.
A stability network was implemented with an RC circuit
to ensure unconditional stability across all frequencies with
which the transistor had gain. Bias Tees were designed to
isolate the RF signal from the DC biasing circuitry resulting
in an isolation of -76 dB at the center frequency. Input and
output matching networks were designed to present the desired
source and load impedances based upon the stated values of
the datasheet while taking into account the effects of the Bias
Tees and the stability circuit. The circuit was then successfully
realized with a linear gain of 16.16 dB, a PAE of 35.2%, an
OP1dB of 31 dB, and was able to output 40 dBm with an
input of 29 dBm. This performance was close to the simulated
results, so this was a successful realization of the design. The
frequency did shift down by 15 Mhz, with a 20 MHz increase
in bandwidth.

R EFERENCES
[1] Cree, Inc., ”CGH40010 10 W, DC - 6 GHz, RF Power GaN HEMT
Datasheet,” Rev. 4.0, May 2015.
[2] test