Detectors and Focal Plane Assembly

Christine Allen Naresh Das Mike Amato

48

Outline
Focal Plane Assembly (FPA) Requirements Design Approach Design Description
Detector Overview Silicon Bridge overview

FPA Electrical Interfaces JFET Design Description- Naresh Das Detector Mechanical Design Description- Mike Amato Test/Verification Plan Development Plan

49

FPA Team
Member Christine Allen Naresh Das Mike Amato Sachi Babu Tom Hartman Quanmin Su Dave Franz Wayne Smith Ernie Buchanan Tim Powers Richard McClanahan Frank Peters Carlos Munroy Dorothy Talley Affiliation Detector Systems Branch/ Code 553 JFETs & Calibration Sources Code 553/Ratheon STX Detector Mechanical Electromechanical Systems Branch/Code 544 Ceramic Boards and High Code 553/Ball Aerospace Density Connectors FPA Mechanical & JFET Detector Systems Branch Mechanical Detector Development Code 553/Ratheon STX Bridge Development Code 553/Ratheon STX Cold Electronics Interfaces Code 553/Ratheon STX Electronics/Detector Testing Code 685/Ratheon STX Electronics/Detector Testing Code 685/Ratheon STX Fabrication Detector Systems Branch Assembly Detector Systems Branch Fabrication Code 553/Ratheon STX Fabrication Code 553/Ratheon STX Description Detector and FPA, Lead

50

FPA Requirements
Format: 12x32 array of 1 mm square, close-packed pixels Detectors must be sensitive enough to achieve background-limited performance For all filter passbands (60m, 100m, and 200m defined by Yerkes) Performance must not be limited by microphonics, magnetic pickup from telescope torque motors, or any other extraneous noise source other than sky noise Must be able to reproduce, predict, or calibrate detector gains over the expected range of operating conditions Calibration time must be << total observing time (Instrument Requirement)

51

FPA Design Approach

Detectors: Pop-up bolometers Pre-Amplification: Silicon JFETs operating at ~77K Connectors:
Silicon microbridges High-density connectors Limit microphonics
No cables from detectors to pre-amps Minimize bond wire lengths

CTE optimized, Kevlar suspended detector packaging Load resistors Polysilicon microfilaments (Calibration sources)

52

Design Description-Detectors

Pop-Up Bolometers (PUBs)

Close packed, 2-D arrays of microbolometers containing
Weak thermal link to ADR bath Measured conductance: G 7x10-12 W/K @ 0.1K G can easily be increased through design changes Ion implanted resistor Measured: NEP5x10-18 W/Hz @ 0.1 K Absorber (Bismuth) Deposited directly onto back-side of detector

53

Design Description-Detectors
Ion-implanted, temperature sensitive resistor (thermistor)
Boron-compensated Phosphorous with temperature dependence:

To R(T ) = Ro exp T
Target R(0.2K)=30-60M

Weak thermal path to ADR bath, anisotropically etched silicon support legs Pop-up configuration to allow close-packing of detectors (filling-factor ~ 98%) Detector pitch (c-c spacing)
1 mm pitch +/- 0.004 mm (4 m), x-direction 1mm pitch +/- 0.025 mm (baseline), y-direction, < 0.010 mm (goal)

54

Key Factors in Assembly

Monolithic, batchfabricated, micromachining on SOI wafers Linear arrays are folded to form Pop-Up structures (see figure) Linear arrays are then stacked in 2-D arrays

55

Folded Array

32-element detector chip, attached to cryogenic Buss-bar. Note the asymmetry of the detector chips frame which will aid in stacking of 2-D arrays.

56

SEM of folded array

Close-up shows details of leg design allowing the silicon to be bent 90 during folding

5 element linear array after folding

57

Design Description-Detectors

5 x 32 assembled array of Pop-Up Bolometers.

58

Design Description-Loads
Ion implanted
Same implant dose as detector, but different length-width ratio Target is 5x higher resistance than detector

Integrated onto detector chip Optimized for stability/low noise

Utilize largest total area which space on detector frame allows

59

Design Description-Detector Readout

1
Source (Common)

2 RL

32 VB(Load)

Gate

Rd

Signal (VOUT)

Ref.

60

Design Description Silicon Bridges Silicon bridge chips for low-thermalconductance, close-packed electrical connections. Used in two places for HAWC.
Detector Bridges
65 bridges, minimum, required per 32-element array Spares for redundant load-bias lines and frame-sensors (as required)

JFET Bridges

61

Design Description Silicon Bridges Baseline description (IRAC Flight version):

1 m thick silicon, 20 m wide ~.3 m thick aluminum, 8 m wide Suspended length: 3.3 mm Air-gap spanned by bridge: 1.5 mm Average electrical resistance: 8 @ 4.2K Average elongation (compliance) at RT: 160 m

Secondary path: Replace single-crystal silicon with a non-crystalline substrate to make it ultracompliant. Polyimide is under consideration.
62

30-wire Silicon Bridge Chip

Bridges

Temporary Frame

63

SEM Close-up of Silicon Bridge

Close-up of a single S-curve seen at an angle of 70. The curves provide strain relief during thermal cycling.

64

Silicon Bridges History

Picture shows a detector mount (IRAC), with three 30-wire silicon bridge chips providing electrical connections for the Kevlar-suspended, hex-shaped detector board in the interior of the mount. 65

JFETs
Low-Noise Silicon Junction Field Effect Transistors
GSFC supplied Housed within a 4.2K enclosure, isolated from bath and shielded to prevent light leaks to detector stage Silicon bridges to provide electrical connection for JFETs

66

Design Description-Connectors
Connectors
Provide a signal & reference lead from each PUD to JFET with goal to:
Minimize loop area Minimize the effect of vibration in a magnetic field (microphonics) Minimize distance from PUD to JFET Minimize cross-talk

Provide a common detector bias lead for each linear array of 32 elements

67

Design Description-Sources
Calibration
Polysilicon microfilaments as black-body calibration sources
Provides a calibration reference internal to the instrument GSFC Supplied

68

Focal Plane Assembly

69

FPA Electrical Interfaces Flow Chart

Detector Card Detectors Load Resistors Silicon Bridge Detector Fanout Board

Temperature Gradients

.2 K 4.2 K 77 K

Detector Motherboard JFET Motherboard Silicon Bridge JFET Silicon Bridge Dewar wiring

70

FPA Electrical Interfaces Detector Card

Detector Card Breakdown
32 element linear array folded onto cryogenic buss-bar
Alumina for CTE match Gold coating for thermal conductivity

Detector bridge chip Detector Fanout Board (FOB)

71

FPA Electrical Interfaces

Detector Fanout Board (FOB)
Single-layer, alumina, circuit board Recessed to allow attachment of bottom edge of bridge chip Wrap-around-the-edge metallization on indexed tab which fits into slots on the Detector Motherboard

72

FPA Electrical Interfaces Detector Motherboard

Mother Board
Multi-layer, alumina, circuit-board (Signal & Returns in pairs) Slots for detector FOB to interface with wraparound
2 detector FOBs per slot 4 FOBs in lower slot
Arrows show direction Of signals on board

Inset shown in later slide

Vias for Hughes connectors

73

Detector Motherboard Block Diagram

32-element Detector Channels
A C H A N N E L A B C H A N N E L B C H A N N E L C C H A N N E L D C H A N N E L E CHANNEL E CHANNEL F C H A N N E L F C H A N N E L M C H A N N E L L C H A N N E L K C H A N N E L J C D E F M L K J H C H A N N E L H G C H A N N E L G

Motherboard Slot Assignments

Symmetric about center line (Right Hand Side is Mirror image of Left Hand Side)

CHANNEL L CHANNEL M CHANNEL J CHANNEL K CHANNEL G CHANNEL H

Motherboard Via Assignments

CHANNEL C CHANNEL D CHANNEL A CHANNEL B

74

Detector FOB to Motherboard Slot detail

Staggered Bonds to motherboard Wrap-around-the-edge metallization

Example of staggered bonds to reduce effective pitch.

.010 in. pitch bond pads on edge of fanout board

75

FPA Electrical Interfaces High Density Connectors

Hughes High Density Printed Circuit Connectors 304 contacts/ connector
3 connectors/ motherboard Overall Dim.: 4.6 x 0.4
Pins which pass through and are soldered to vias in the detector motherboard

Socket side of connector mates to JFETs (next slide)

Photos show Hughes connectors having half of the pins required for each HAWC connector

76

FPA Electrical Interfaces JFET Motherboard

Hughes mating connector JFET Module
Pins mate to sockets in the Detector Motherboard Connectors (previous slide) Flexible circuit is soldered to JFET Motherboard

77

JFET Module Overview

JFET Motherboard
Two-sided, alumina, circuit-board Hughes mating connectors soldered to edge on each side Vias through the board for returnsignal pairs to be transferred to opposite sides of board where they travel in parallel Shield inside module over JFETs and bridges External housing for shielding and mechanical package JFET modules fit inside a large housing, which acts as an additional shield and mechanical support for the array

Heat shielding

78

JFET Module Overview

Pre-amplifies the detector signal Each JFET module handles 4, 32-element linear arrays 3 modules enclosed in JFET housing Modules are independent and interchangeable

79

JFET Motherboard
JFETs
JFET Platform

Heat shield

Bridge chip

G10 Isolation Region

80

FPA Electrical Interfaces

Heaters and sensors

JFET Cold-Side bridge chip (to detectors)

JFET Cold-Side bridge chip (to detectors)

81

FPA Electrical Interfaces

JFET Platform
Alumina board for CTE match to silicon JFETs epoxied to platform Epoxy-glass cylinders for thermal stand-offs Signal lines come in and out through bridge chips Return lines travel under JFET platform Heaters & sensors on JFET platform to heat from 4.2 K to 77 K (JFET op. temp.)

Hughes mating connector Dewar harness

82

JFETs and Calibration Sources Design Description

Naresh C. Das

83

Outline
JFET on Board Device Specification Bulk Silicon Vs SOI JFET Fabrication I-V characteristics Noise performance

84

Polysilicon IR Sources Design Layout Fabrication SEM of Poly Source Resistances Performance

85

Polysilicon IR Sources

Device Active area 150X300 m Array pitch is 254 m

86

Design Specifications
(I) For Vds=1.2 V and Id=25 A, Vgs= -1.0 to 1.5 V (ii) gm > 0.2 mS (iii) Ig < 20 pA @ RT (iv) Gate-source breakdown < -12 V (v) Noise voltage at 77 K Frequency (Hz) 1 Noise (nV/Hz1/2) 75 20 20 100 8 1000 7

87

Design Specifications

S
n-epi

D
n-epi

2 KAng. SiO2 <100.> p-type substrate <100.> p-type substrate

Bulk Si-JFET

SOI JFET

88

JFET Fabrication
1) Oxidation 2) Grove etching 3) Boron Diffusion 4) Phosphorous diffusion 5) Drive in 6) Contact opening 7) Metalization 8) LTO deposition Six masks process 89

Device Characteristics
gm at RT is 2 mS Vtoff at RT is -1.1 V gm at 77 K is 4 mS Vtoff at 77 K is -.81 V

90

Noise Performance
Noise voltage for both bulk Si and SOI JFET at 77K is similar Noise is measured with source follower mode with Vd of 5.0 V

91

Poly sources layout

Design layout available for 150X30, 150X40, 200X30, 200X 40 m

92

Fabrication
Deposit 10 m LTO on Silicon substrate Polysilicon Deposition Low Dose Implant Heavy Dose Implant on leg area Metallization Oxide etching

93

Poly sources

94

Poly Resistance
Implant dose changes poly resistance

95

Power Spectrum
Emission spectra in IR region Linear dependence of emissivity vs power

96

Detector Mechanical Design Description

Mike Amato

97

Detectors
Detector mechanical design - 12X32 detector packaging requirements and goals. Keep the diameter of the upper part of the assembly under 4 inches (future applications). Detector row spacing of 1 mm (currently working with +/~ .025 mm (.001 in) mechanical tolerance goal). Detector plane alignment of better than 0.25 mm.

98

Detectors
12X32 Detector mechanical requirements Fan-out board pad alignment of approximately .0025 in. between fan-out boards (to aid wire bonding to the back plane board). Keep thermal and load motions at the bridge chips to less than tested limit (~160 microns room temp) with positive margin. Current worst case (emergency landing) at temperature motion estimated at ~ 30 microns (.030 mm)

99

Detectors
12X32 Detector mechanical requirements Keep conduction thermal losses between 200 mK stage and 4.2 K stage of detector assembly within assigned budget (~ less than 10 microwatts). Meet all of the above requirements after a worst case handling load, currently using ~ 60G static equivalent goal from JPL small part spec. Meeting this will also tend to meet ~ 3G operating load and 9G emergency landing load.

100

Detectors
Detector mechanical design - A good way to describe the detector subassembly is to work from the inside out which is also how the system is, in a simplified sense, assembled.

101

Detectors
The PUB chips are folded and epoxied to the buss bars.
PUB chip 32 pop up detectors

2.4 inches

Alumina ceramic buss bar

102

Detectors
The bridge chips are epoxied to a buss bar and a fan-out board. Bridge
chip 0.2 K 4K Fan-out board pad
3.8 in.

Alumina fan-out board

103

Detectors
The upper and lower ceramic C parts are aligned and assembled into two half C subassemblies.
Spacer bracket Upper alumina C Lower alumina C

104

Detectors
Six buss bar/bridge chip/fan-out board subassemblies are aligned and epoxied to each ceramic C subassembly. 0.2 K 4K 1 C subassembly 6 Bar-bridge chipfan-out board subassemblies

105

Detectors
Two of the resulting subassemblies are aligned and bolted together to form a 12X32 array.

Two half detector subassemblies joined into one full detector array subassembly

106

Detectors
The resulting 12X32 detector assembly is lowered into and bolted to the card-cage interface structure.
Full detector array subassembly from previous picture

Card cage interface structure (titanium, low CTE for commonly machined metals)

107

Detectors
The six kevlar straps are epoxied to end hardware and tensioned into the claw with Belleville spring stacks on the top ends.
Strap tensioning nut Disc -spring stack Claw part
(titanium)

Kevlar straps

108

Detectors
The claw is lowered over the detector array and bolted to the lower Cs.
Suspension claw with tensioned kevlar straps Full detector array in card cage structure

109

Detectors
The cold plate is lowered, twisted into position with its hooks or grooves at the kevlar straps, and bolted or epoxied to the upper Cs.

Cold plate epoxied to kevlar straps at each strap set crossing point

Cold plate (alumina)

110

Detectors
The assembly is mounted to the top of the JFET box.
3 JFET electronics modules on card guides Not shown high density connectors are on both ends of the modules

Subassembly from previous picture mounted to top of JFET box

JFET heat straps

111

Detectors
The mother board is aligned to the fan out board tabs and attached to the card cage structure and the JFET box. Mother board (alumina) The pads on the tabs of the fan out boards are wire bonded to mother board tabs High density connector mates (not shown) Shim adjustable mechanical interface to instrument

112

Detectors
The ADR heat strap is attached to the cold plate and the suspension brackets which suspended the detectors during the assembly are removed. Spacer
brackets removed ADR heat strap attach area

113

Test and Verification

Christine Allen

114

Test/Verification Plan
Mechanical Model-Prototype assembly, to test and develop the focal plane assembly process (Code 553/544)
Vibration test of sub-assemblies

CTE Compatible Assembly Model (Code 553/544)

Identical in mechanical function to flight unit Test bridge compliance under thermal cycling (monitor continuity) Shake test of assembly Mount thermal profile

Bridge Test Assembly (Code 553)

Test thermal conductivity Test electrical conductivity

115

Test/Verification Plan (cont.)

JFET testing/screening (Code 553) Detector Testing/screening (Code 685/U. Chicago)
Ion implant screening and selection of optimum dose Detector testing - cold JFET module testing - cold

CSO ground demonstration

116

Risk Analysis and Mitigation Plan

Mechanical Model assembly fabrication to identify design flaws and assembly roadblocks Connectors:
Redundant silicon bridges for array bias lines Redundant silicon bridges for JFET drains Optimize silicon bridge design for compliance under mount thermal cycles

Off-the-shelf technologies used where feasible CTE match of materials to Silicon Kevlar suspension of ADR detector stage for stiffness/thermal isolation Back-up detector assembly for flight Design for ease of instrument integration (Modular design) CSO detector assembly qualification (PUD FPA test-bed)

117

Development Plan Cold Electronic Components

Detectors
No major changes from present detector design except to tailor the thermal conductance to higher conductance required for HAWC Design integration of load resistor and bias lines Operational test models (target 2nd quarter 99)

Bridges
Baseline: Redesign IRAC chip/bridge (1st quarter 99) Secondary path: Bridge with improved compliance over single-crystal silicon

JFETs
Baseline: JFET on standard wafers with isolation etch (2nd quarter 99) Secondary path: Integrate discrete devices onto single JFET board by dicing between elements

Calibration Sources
Selection of optimum source design (2nd quarter 99) Fabrication and bonding to suitable carrier for integration into Yerkes package (2nd-3rd quarter 99)

118

FPA Development Plan

Engineering Unit (Aluminum Mechanical Model)
Non-functioning detector assembly prototype (in fabrication now)

Detector Assembly Prototype (CTE matched Mechanical Model) (1st - 2nd quarter 99) Field Test (CSO unit) (June 99)
Fully functional 6x32 array

Flight Unit 1 (1st-3rd quarter 00, contingent on CSO) Flight Unit 2 (2nd-4th quarter 00, contingent on CSO)

119