IC Fabrication

Sivasubramaniyan S B
Fabrication

 It consists of sequence of photographic and

chemical processing steps
 The desired circuit is gradually created on Wafer,
a pure semiconductor material

S. B. Sivasubramaniyan MSEC, Chennai

Wafer

 Wafers (0.75 mm thick) are formed from highly

pure, defect free single crystalline material
referred to as ingot or boules (300 mm ~ 12 in)
 Ingot of a pure monocrystalline is formed by a
process called Czochralski process

S. B. Sivasubramaniyan MSEC, Chennai

Wafer

 After this wafer preparation, many steps are

involved in the chip fabrication
 In general, the steps can be classified into
 Front-end-of-line (FEOL) processing
 Back-end-of-line (BEOL) processing

S. B. Sivasubramaniyan MSEC, Chennai

Processing after Wafer

 The various processing steps fall under four

major categories
 Deposition
 Removal
 Patterning
 Modification of electrical properties

S. B. Sivasubramaniyan MSEC, Chennai

Deposition

 Depositing something by growing, coating or

transferring a material onto the wafer
 Available technologies include
 Physical Vapour Deposition (PVD)
 Chemical Vapour Deposition (CVD)
 Electrochemical Deposition (ECD)
 Molecular Beam Epitaxy (MBE)
 Atomic Layer Deposition (ALD)
S. B. Sivasubramaniyan MSEC, Chennai
Physical Vapour Deposition

 Deposition is carried out by condensation of a vapourized

material on to the surface of the wafer
 Various types include
 Cathodic Arc Deposition
 Electronic Beam Physical Vapour Deposition
 Evaporative Deposition
 Pulsed Laser Deposition
 Sputter Deposition

S. B. Sivasubramaniyan MSEC, Chennai

Deposition

 Depositing something by growing, coating or

transferring a material onto the wafer
 Available technologies include
 Physical Vapour Deposition (PVD)
 Chemical Vapour Deposition (CVD)
 Electrochemical Deposition (ECD)
 Molecular Beam Epitaxy (MBE)
 Atomic Layer Deposition (ALD)
S. B. Sivasubramaniyan MSEC, Chennai
 Chemical Vapour Deposition

 It’s a chemical process in which gas or vapour is allowed to react on

the surface of the substrate resulting in the formation of solids
 Deposition include Silicon dioxide, silicon nitride, silicon carbide,
silicon oxynitride, titanium nitride etc.,
 If silane gas alone is allowed to react at high temperature, say 1000
deg. C, crystalline silicon layer is deposited on the surface – denoted
as epitaxial layer and the process is epitaxy
 If the reaction temperature is lower, say 500 deg. C, the crystalline
silicon layer deposited will not be single crystal rather poly-
crystalline, commonly referred to as Poly-Si
 Poly-Si is usually heavily doped and used in place of metal gate
(silicon gate technology, 1971)
S. B. Sivasubramaniyan MSEC, Chennai
Other Deposition techniques

 Students are advised to refer standard text books

for further enhancing their knowledge

S. B. Sivasubramaniyan MSEC, Chennai

Processing after Wafer

 The various processing steps fall under four

major categories
 Deposition
 Removal
 Patterning
 Modification of electrical properties

S. B. Sivasubramaniyan MSEC, Chennai

Removal

 Removing something from the surface of the

substrate (wafer) either fully or selectively i.e.,
etching process
 Etching has two forms – dry etching or wet
etching
 Chemical-mechanical planarization is also a
etching process used effectively

S. B. Sivasubramaniyan MSEC, Chennai

 Etching

 In most of the cases, the wafer is protected from the etchant by a

masking material
 The masking material, in most of the cases, is a photoresist,
patterned using photolithography
 First the wafer is coated (deposition) with a photosensitive layer
(photoresist)
 A photographic plate (glass plate with chromium pattern) is placed
on top of photoresist to selectively expose the photoresist to UV
illumination
 The exposed layer gets softened (for positive photoresist) which can
be etched using a chemical developer, leaving the masking pattern

S. B. Sivasubramaniyan MSEC, Chennai

 Etching

 Silicon dioxide, silicon nitride, polysilicon and metal layers can be

selectively removed using this etching methods
 After etching, the photoresist is stripped away, leaving behind the
image of the photomask on the wafer surface
 As many as 20 layers of masking are needed in most advanced VLSI
fabrication processes

S. B. Sivasubramaniyan MSEC, Chennai

 Etching - types

 Wet etching involves wet (liquid) etchants where in wafers

immersed in a bath of wet etchant and agitated
 Buffered Hydrofluoric acid etches silicon dioxide from silicon surface
 Wet etching is obsolete as it involves large amount of toxic waste
 However, photographic developer used in photoresist resemble wet
etching
 Dry etching (plasma etching) is the other technique in which the
wafer is allowed to react with source gas (plasma) rich in chlorine
and fluorine operating at 133.3 pascals
 Carbon tetrachloride etches silicon and aluminium and
trifluoromethane etches silicon dioxide and silicon nitride
S. B. Sivasubramaniyan MSEC, Chennai
Processing after Wafer

 The various processing steps fall under four

major categories
 Deposition
 Removal
 Patterning
 Modification of electrical properties

S. B. Sivasubramaniyan MSEC, Chennai

Patterning

 Patterning the deposited material on the wafer

 The procedure often referred to as lithography
 Similar to photolithography discussed earlier
 A thing to note is that the remaining excess
patterns are shaped and aligned
 For which a machine called as stepper(!?) is
employed

S. B. Sivasubramaniyan MSEC, Chennai

Processing after Wafer

 The various processing steps fall under four

major categories
 Deposition
 Removal
 Patterning
 Modification of electrical properties

S. B. Sivasubramaniyan MSEC, Chennai

Modification of electrical properties

 Modifying the electrical property literally refers to doping

the selected portion of the wafer
 This is done by either diffusion or by ion implantation
 Diffusion is carried out under high temperature (1000 –
1200 deg. C) for faster doping
 Ion implantation is carried out at room temperature using
an ion beam controlled by a electric field
 Ion implantation is more accurate than diffusion

S. B. Sivasubramaniyan MSEC, Chennai

Oxidation

 It’s a chemical process of silicon reacting with oxygen to

form silicon dioxide
 Ultraclean furnace is required for oxidation and is carried
out at 1000 – 1200 deg. C to speed up the process
 There are two methods – dry and wet oxidation
 In either case, thermally grown oxide layer has better
electrical insulating properties

S. B. Sivasubramaniyan MSEC, Chennai

As a general classification,

 We parted the entire fabrication process into Front-end-

of-line (FEOL) processing and Back-end-of-line (BEOL)
processing
 A good look at this classification will end the entire
fabrication process completely

S. B. Sivasubramaniyan MSEC, Chennai

 Front-End-Of-Line processing

 It is the design of transistors on the wafer surface

 As is the case, we need silicon substrate to start with
 Ultrapure silicon is grown over a raw wafer through epitaxy
 We have two methods to concentrate here
 One, depositing silicon on Silicon-Germanium base
 This facilitates better electron mobility due to the stretch of the
deposition
 Other, depositing silicon on an insulator which will reduce parasitic
effects
 Having done with the substrate, the next step is the design of gate
oxide, source and drain diffused regions, and silicon gate
S. B. Sivasubramaniyan MSEC, Chennai
 Back-End-Of-Line processing

 It consists of the design of metal layers and interconnect

 The process is usually referred to as metallization
 The metal interconnecting wires are usually separated by dielectrics
 Earlier design involved SiO2 and silicate glass, now low K materials such as
SiOC are preferred
 For the case of interconnect, aluminium was once a popular choice
 With the increase in the transistor density, the interconnect conductivity
played an important role which prompted the usage of copper
 The process involved placing the wafer inside a chamber above the target
where is also placed an argon gun
 The Argon gas atoms bombard the target and knock the atoms out of it
which covers the entire chamber including the wafer
 The unwanted metal layers are then etched out
MSEC, Chennai
S. B. Sivasubramaniyan
Packaging

 This is the last step involved

 The fully designed wafer contain hundreds of
transistors
 The circuit is finally tested and the tested circuits
are separated by a process called dicing
 The die is then mounted in packages or headers
 Finally the package is sealed using plastic or
epoxy under vacuum or in an inert atmosphere
MSEC, Chennai
S. B. Sivasubramaniyan
Technology – a glance

 The first 4 bit microprocessor was built with pmos(?)

technology in the year 1971 (intel 4004)
 In 1973, the second generation microprocessor were
designed with nmos(?) technology (intel 8082, 8085…..)
 In 1978, the third generation microprocessors were
designed using high density mos (hmos) (?) technology
 Fourth generation used high density cmos (?) technology
(intel 80386, 80486…). It was in the year 1980

MSEC, Chennai
S. B. Sivasubramaniyan
PMOS, NMOS, CMOS - What’s all this?

 The basic building block of any digital system is the

inverter(?) design
 If the inverter was designed using pmos the technology is
referred to as PMOS technology
 If the inverter was designed with nmos – NMOS
technology
 Employing both pmos and nmos – cmos technology
 Each of these technologies has its own merits and
demerits
MSEC, Chennai
S. B. Sivasubramaniyan
PMOS, NMOS

S. B. Sivasubramaniyan MSEC, Chennai

PMOS, NMOS - drawbacks

 Consider this particular case in each of the inverter

designs

S. B. Sivasubramaniyan MSEC, Chennai

Overcoming the drawback

 To overcome the drawback of static power

dissipation, a newer technology was
introduced in the year 1978
 The complementary MOS technology,
commonly referred to as CMOS technology

S. B. Sivasubramaniyan MSEC, Chennai

CMOS technology

 As the name specifies, the CMOS technology

basically has both PMOS and NMOS type of
transistors in it (hence, the name)
 The logic behind is either of the transistor will be
OFF when an input is applied to the gate which
avoids a short between supply and the ground
 As said, a direct short between the supply and the
ground which was present in the previous
technologies was narrowly avoided by using both
PMOS and NMOS transistors

S. B. Sivasubramaniyan MSEC, Chennai

CMOS technology

S. B. Sivasubramaniyan MSEC, Chennai

CMOS technology

 As said, static power dissipation is zero in the

case of CMOS technology as there is no
direct path existing between the supply and
ground
 However, dynamic power dissipation is
present in the CMOS technology due to the
inherent capacitance associated with the
transistors

S. B. Sivasubramaniyan MSEC, Chennai

Coming back to fabrication

 We will the see the nmos process step by

step

S. B. Sivasubramaniyan MSEC, Chennai

NMOS process – summary
(as given in Basic VLSI Design by D. Pucknell, K. Eshragian, 3rd edition)

 Processing takes place on a p-doped silicon crystal

wafer on which is given a thick layer of SiO2
 Mask 1 – Pattern SiO2 to expose the silicon surface
in areas where paths in the diffusion layer or gate
areas of transistors are required. Deposit thin oxide
over all. For this reason, this mask is often known as
the ‘thinox’ mask but some texts refer to it as
diffusion mask
 Mask 2 – Pattern the ion implantation within the
thinox region where diffusion mode devices are to be
produced – self-aligning
S. B. Sivasubramaniyan MSEC, Chennai
NMOS process – summary
(as given in Basic VLSI Design by D. Pucknell, K. Eshragian, 3rd edition)

 Mask 3 – Deposit polysilicon over all, then pattern using Mask

3. Using the same mask, remove thin oxide layer where it is not
covered by polysilicon
 Diffue n regions into areas where thinoxide has been removed.
Transistor drains and sources are thus self-aligning with
respect to the gate structures
 Mask 4 – Grow thick oxide over all and then etch for contact
cuts
 Mask 5 – Deposit metal and pattern with Mask 5
 Mask 6 – Would be required for the overglassing process step

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well
 Depending on the type of substrates, CMOS
process can be identified as n-well, p-well,
twin well processes
 Advanced CMOS process uses trench
isolation and silicon on insulator technology
to reduce parasitic capacitance and to
improve packing density

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well
 Minimum of 7 mask layers are needed
 However, additional layer for
 N & P guards for better latch up immunity (?!),
 A second polysi layer for capacitors
 Multilayer metals for high density interconnections
 All these amounts to nearly 15 to 20 masking layers

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well
 Starting material is P-type substrate
 Process begins with n-well diffusion
(wherever pmos is required)

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well
 Kindly note that, except for LOCOS, in all the
steps we need a mask in the above
discussion
 On the whole there are 7 masks required
 The 8th mask is sometimes needed for
overall passivate (glass) layer to define the
openings for access to bonding pads

S. B. Sivasubramaniyan MSEC, Chennai

N-well process – steps
(as given in Basic VLSI Design by D. Pucknell, K. Eshragian, 3rd edition)

 The main steps can be given as a flow chart (not drawn, the students
are advised to draw it themselves, using the steps listed)
 Formation of n-well regions
 Define NMOS and PMOS active areas
 Field and gate oxidations (thinox)
 Form and pattern polysilicon
 P+ diffusion
 N+ diffusion
 Contact cuts
 Deposit and pattern metallization
 Over glass with cuts for bonding pads

S. B. Sivasubramaniyan MSEC, Chennai

CMOS process – N-well
 There are a number of p-well and n-well
fabrication processes
 For example, Berkeley n-well proess is
shown

S. B. Sivasubramaniyan MSEC, Chennai

Berkeley N-well process – steps
(as given in Basic VLSI Design by D. Pucknell, K. Eshragian, 3rd edition)

 The main steps can be given as a flow chart (not drawn, the students
are advised to draw it themselves, using the steps listed)
 Define the phosphorous doped n-wells
 Grow gate oxide, then cover wafer with silicon nitride
 Delineate the thin oxide areas above the p-substrate, leaving all n-well
regions covered
 Nitride is selectively etched from the regions where thick oxide is
desired
 Boron implant is introduced to act as a self-aligned p-type channel
stop
 Field oxidation
 Nitride layer is selectively etched above n-well

S. B. Sivasubramaniyan MSEC, Chennai

Berkeley N-well process – steps
(as given in Basic VLSI Design by D. Pucknell, K. Eshragian, 3rd edition)

 Phosphorous implant is introduced to form n-type channel stop in the

n-well
 The remaining nitride layer is etched
 Implant for threshold adjustment
 Heavily n-doped polysilicon is deposited over wafer
 Formation of n+ regions in thinox areas not covered by polysilicon
using arsenic implant
 Formation of P+ regions through boron implant
 Thick oxide over all
 Define contact cuts
 Deposit aluminium and pattern
 Passivate and make cuts for bonding pads

S. B. Sivasubramaniyan MSEC, Chennai

P-well process
 All the processing steps are similar to nmos
process
 Students are advised to refer, “Basic VLSI
Design by Douglas Pucknell and Kamran
Eshragian, 3rd edition, Prentice Hall of
India” &
 “Principles of CMOS VLSI Design” by Neil
H.E. Weste, Kamran Eshragian, 2nd
edition, Pearson Education
S. B. Sivasubramaniyan MSEC, Chennai
Twin-Tub process
 Both P-well and N-well are created in the high
resistive n-substrate in twin tub process
 It is a logical extension of p-well and n-well process
 Students are advised to refer, “Basic VLSI Design”
by Douglas Pucknell and Kamran Eshragian, 3rd
edition, Prentice Hall of India &
 “Principles of CMOS VLSI Design” by Neil H.E.
Weste, Kamran Eshragian, 2nd edition, Pearson
Education

S. B. Sivasubramaniyan MSEC, Chennai

Bi-CMOS fabrication
 Bi-CMOS along with p-well and twin tub process are
to be submitted as an assignment
 Students are advised to refer, “Basic VLSI Design
by Douglas Pucknell and Kamran Eshragian, 3rd
edition, Prentice Hall of India” &
 “Principles of CMOS VLSI Design” by Neil H.E.
Weste, Kamran Eshragian, 2nd edition, Pearson
Education

S. B. Sivasubramaniyan MSEC, Chennai