CSD19536KTT

SLPS540C – MARCH 2015 – REVISED MAY 2025

CSD19536KTT 100V N-Channel NexFET™ Power MOSFET

1 Features Product Summary
TA = 25°C TYPICAL VALUE UNIT
• Ultra-low Qg and Qgd VDS Drain-to-Source Voltage 100 V
• Low thermal resistance
Qg Gate Charge Total (10V) 118 nC
• Avalanche rated
Qgd Gate Charge Gate-to-Drain 17 nC
• Lead-free terminal plating
• RoHS compliant Drain-to-Source On- VGS = 6V 2.2
RDS(on) mΩ
• Halogen free Resistance VGS = 10V 2
• D2PAK plastic package VGS(th) Threshold Voltage 2.5 V

2 Applications Device Information

DEVICE(1) QTY MEDIA PACKAGE SHIP
• Secondary side synchronous rectifier
CSD19536KTT 500 13-Inch D2PAK Plastic
• Hot swap Tape and Reel
CSD19536KTTT 50 Reel Package
• Motor control
(1) For all available packages, see the orderable addendum at
3 Description the end of the data sheet.
This 100V, 2mΩ, D2PAK (TO-263) NexFET™ power Absolute Maximum Ratings
MOSFET is designed to minimize losses in power TA = 25°C VALUE UNIT
conversion applications. VDS Drain-to-Source Voltage 100 V
Drain (Pin 2) VGS Gate-to-Source Voltage ±20 V
Continuous Drain Current
200
(Package Limited)
Continuous Drain Current (Silicon Limited),
ID 272 A
TC = 25°C

Gate Continuous Drain Current (Silicon Limited),

192
(Pin 1) TC = 100°C
IDM Pulsed Drain Current(1) 400 A
PD Power Dissipation 375 W
Source (Pin 3)
TJ, Operating Junction,
–55 to 175 °C
Tstg Storage Temperature
Pin Out
Avalanche Energy, Single Pulse
EAS 806 mJ
ID = 127A, L = 0.1mH, RG = 25Ω

(1) Max RθJC = 0.4°C/W, Pulse duration ≤ 100µs, Duty cycle ≤

1%.

8 10
TC = 25° C, ID = 100 A ID = 100 A
9 VDS = 50 V
RDS(on) - On-State Resistance (m:)

7 TC = 125° C, ID = 100 A
VGS - Gate-to-Source Voltage (V)

8
6
7
5
6
4 5

3 4
3
2
2
1
1
0 0
0 2 4 6 8 10 12 14 16 18 20 0 12 24 36 48 60 72 84 96 108 120
VGS - Gate-to-Source Voltage (V) D007 Qg - Gate Charge (nC) D004

RDS(on) vs VGS Gate Charge

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19536KTT
SLPS540C – MARCH 2015 – REVISED MAY 2025 www.ti.com

Table of Contents
1 Features............................................................................1 5 Device and Documentation Support..............................7
2 Applications..................................................................... 1 5.1 Receiving Notification of Documentation Updates......7
3 Description.......................................................................1 5.2 Community Resources................................................7
4 Specifications.................................................................. 3 5.3 Trademarks................................................................. 7
4.1 Electrical Characteristics.............................................3 6 Revision History.............................................................. 7
4.2 Thermal Information....................................................3 7 Mechanical, Packaging, and Orderable Information.... 8
4.3 Typical MOSFET Characteristics................................ 4

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4 Specifications
4.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0V, ID = 250μA 100 V
IDSS Drain-to-source leakage current VGS = 0V, VDS = 80V 1 μA
IGSS Gate-to-source leakage current VDS = 0V, VGS = 20V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250μA 2.1 2.5 3.2 V
VGS = 6V, ID = 100A 2.2 2.8
RDS(on) Drain-to-source on-resistance mΩ
VGS = 10V, ID = 100A 2 2.4
gfs Transconductance VDS = 10V, ID = 100A 329 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance 9250 12000 pF
Coss Output capacitance VGS = 0V, VDS = 50V, ƒ = 1MHz 1820 2370 pF
Crss Reverse transfer capacitance 47 61 pF
RG Series gate resistance 1.4 2.8 Ω
Qg Gate charge total (10V) 118 153 nC
Qgd Gate charge gate-to-drain 17 nC
VDS = 50V, ID = 100A
Qgs Gate charge gate-to-source 37 nC
Qg(th) Gate charge at Vth 24 nC
Qoss Output charge VDS = 50V, VGS = 0V 335 nC
td(on) Turnon delay time 13 ns
tr Rise time VDS = 50V, VGS = 10V, 8 ns
td(off) Turnoff delay time IDS = 100A, RG = 0Ω 32 ns
tf Fall time 6 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 100A, VGS = 0V 0.9 1.1 V
Qrr Reverse recovery charge VDS= 50V, IF = 100A, 548 nC
trr Reverse recovery time di/dt = 300A/μs 103 ns

4.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance 0.4 °C/W
RθJA Junction-to-ambient thermal resistance 62 °C/W

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4.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)

Figure 4-1. Transient Thermal Impedance

200 200
TC = 125° C
175 175 TC = 25° C
IDS - Drain-to-Source Current (A)

IDS - Drain-to-Source Current (A)

TC = -55° C
150 150

125 125

100 100

75 75

50 50
VGS = 6 V
25 VGS = 8 V 25
VGS = 10 V
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 1 2 3 4 5 6 7
VDS - Drain-to-Source Voltage (V) D002 VGS - Gate-to-Source Voltage (V) D003

Figure 4-2. Saturation Characteristics VDS = 5V

Figure 4-3. Transfer Characteristics

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10 100000

9
VGS - Gate-to-Source Voltage (V)

8 10000

C - Capacitance (pF)
7
1000
6
5
100
4
3
10 Ciss = Cgd + Cgs
2 Coss = Cds + Cgd
Crss = Cgd
1
1
0 0 10 20 30 40 50 60 70 80 90 100
0 12 24 36 48 60 72 84 96 108 120 VDS - Drain-to-Source Voltage (V) D005
Qg - Gate Charge (nC) D004 Figure 4-5. Capacitance
VDS = 50V ID = 100A

Figure 4-4. Gate Charge

3.1 8
TC = 25° C, ID = 100 A
2.9

RDS(on) - On-State Resistance (m:)

7 TC = 125° C, ID = 100 A
VGS(th) - Threshold Voltage (V)

2.7
6
2.5
2.3 5

2.1 4
1.9 3
1.7
2
1.5
1.3 1

1.1 0
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 2 4 6 8 10 12 14 16 18 20
TC - Case Temperature (° C) D006
VGS - Gate-to-Source Voltage (V) D007

ID = 250µA Figure 4-7. On-State Resistance vs Gate-to-Source

Voltage
Figure 4-6. Threshold Voltage vs Temperature
2.4 100
VGS = 6 V TC = 25° C
2.2 VGS = 10 V TC = 125° C
Normalized On-State Resistance

ISD - Source-to-Drain Current (A)

10
2
1.8 1
1.6
1.4 0.1

1.2
0.01
1
0.8 0.001

0.6
0.0001
0.4 0 0.2 0.4 0.6 0.8 1
-75 -50 -25 0 25 50 75 100 125 150 175 200 VSD - Source-to-Drain Voltage (V) D009
TC - Case Temperature (° C) D008
Figure 4-9. Typical Diode Forward Voltage
ID = 100A

Figure 4-8. Normalized On-State Resistance vs

Temperature

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1000 500
TC = 25q C
TC = 125q C
IDS - Drain-to-Source Current (A)

IAV - Peak Avalanche Current (A)

100

100
10

DC 1 ms
10 ms 100 µs
0.1 10
0.1 1 10 100 1000 0.01 0.1 1
VDS - Drain-to-Source Voltage (V) D010 TAV - Time in Avalanche (ms) D011
Single pulse, max RθJC = 0.4°C/W Figure 4-11. Single Pulse Unclamped Inductive
Switching
Figure 4-10. Maximum Safe Operating Area
225

200
IDS - Drain-to-Source Current (A)

175

150

125

100

75

50

25

0
-50 -25 0 25 50 75 100 125 150 175 200
TC - Case Temperature (° C) D012

Figure 4-12. Maximum Drain Current vs Temperature

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5 Device and Documentation Support

5.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
5.2 Community Resources
5.3 Trademarks
NexFET™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

6 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2015) to Revision C (May 2025) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1

Changes from Revision A (May 2015) to Revision B (August 2016) Page

• Added Section 5.1 section..................................................................................................................................7

Changes from Revision * (March 2015) to Revision A (May 2015) Page

• Added Section 5.2 section..................................................................................................................................7
• Added PCB and stencil drawings in Section 7 ...................................................................................................8

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7 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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