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Answers For Selected Problems

The document outlines key parameters for IC design, including unit cost, NRE cost, size, performance, power, flexibility, time-to-prototype, time-to-market, and maintainability. It emphasizes the importance of time-to-market as a critical design parameter and discusses the role of HDL in system design, including its simulation and synthesis capabilities. Additionally, it describes various types of HDL descriptions and the purpose of a testbench in verifying module functionality.

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12 views20 pages

Answers For Selected Problems

The document outlines key parameters for IC design, including unit cost, NRE cost, size, performance, power, flexibility, time-to-prototype, time-to-market, and maintainability. It emphasizes the importance of time-to-market as a critical design parameter and discusses the role of HDL in system design, including its simulation and synthesis capabilities. Additionally, it describes various types of HDL descriptions and the purpose of a testbench in verifying module functionality.

Uploaded by

naveensl0207
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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07.

IC Design Matrices

• Unit cost: monetary cost of manufacturing each copy of the system, excluding NRE
cost

• NRE cost (Non-Recurring Engineering cost): one-time monetary cost of designing


the system (IC)

• Size: physical space required by the system (IC)

• Performance: execution time or throughput of the system (Maximum rate of


production)

• Power: amount of power consumed by the system (IC)

• Flexibility: the ability to change the functionality of the system without incurring
heavy NRE cost

• Time-to-prototype: time needed to build a working version of the system

• Time-to-market: the time required to develop a system to the point that it can be
released and sold to customers

• Maintainability: ability to ‘look after’ the system after its initial release

Time to Market (TTM) is a Most Demanding Design Parameter


Q21.

Q33
Q25.
Q-3
Q-
Q-8
Model Answers for Selected Tutorial Questions

35.

(a).

• A high level of description of the entire system can be precisely specified.

• HDL description can be simulated. The simulation supports design verification.

• HDL supports for logic synthesis.

• HDL eases the design of complex digital systems/logic ICs

(b) HDL descriptions written in RTL can be used as a design entry to many different CAD
tools while the graphical/schematic entries are unique for a particular design tool

(c) .

i. Logic synthesis: Transforms an RTL description of a circuit into an optimized netlist


representing storage elements and combinatorial logic

ii. Data flow description provides the means of describing combinational circuits by their
function rather than by their gate structure. Dataflow modelling uses a number of
operators to produce the desired results

iii. Structural Description: describes the circuit structure in terms of the logic gates used and
the interconnect wiring between the logic gates to form a circuit netlist.

iv. Behavioral Description: Behavioral modeling describes what the circuit does, focusing on
its functionality

(d).

Keywords “module” and “endmodule” are mandatory components

Portlist, port declaration - mandatory

variables, data flow statements, behavioural blocks, lower level module intantiations,
tasks or funtionas are optional. But one of them should be included to perform the desired
function.
36.

(a). Test Bench in HDL: A testbench is an HDL module used to test another module, known
as the device under test (DUT), by applying inputs and verifying correct outputs through test
vectors

In Verilog, a module is defined and, possibly, given the name testBench. Within this module
are two other modules, one representing the system being designed, and the other
representing the test generator and monitor

(b)

(c).
(d).
37.

(a).
(b).

(c).

(d).
(e).
38. (a)

(b).
39. (a)

(b).

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