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The course EE2520, Introduction to CMOS Processing, covers the history of integrated circuits, the planar process, Moore's Law, and Dennard Scaling. Key topics include technology nodes, unit processes, and the advantages of CMOS technology. By the end of the course, students will understand the evolution of microprocessors and the implications of scaling in semiconductor technology.

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66 views10 pages

Into

The course EE2520, Introduction to CMOS Processing, covers the history of integrated circuits, the planar process, Moore's Law, and Dennard Scaling. Key topics include technology nodes, unit processes, and the advantages of CMOS technology. By the end of the course, students will understand the evolution of microprocessors and the implications of scaling in semiconductor technology.

Uploaded by

chirag.garg02062005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COURSE TITLE: INTRODUCTION TO CMOS PROCESSING

COURSE CODE: EE2520


Textbook: Integrated Circuit Fabrication (Science and
Technology)
Authors: James D Plummer and Peter B. Griffith

Introduction
(Lecture1)

1
KEY CONCLUSIONS
By the end of Introduction Lecture(s), you should be familiarized with

❖ History of Integrated Circuits


❖ Planar Process
❖ Moore’s Law
❖ Dennard Scaling
❖ Technology Node
❖ Unit Processes
❖ Course Objectives

2
1948 - Present

First Solid State Device

First Integrated Circuit

A Complex Chip (i7 processor)

Latest Microprocessor

3
Bulk Vs Planar

Alloy junction technology of


the 1950s.
Grown junction transistor
technology of the 1950s

SiO2

Double diffused transistor The planar process (Hoerni -


technology of the 1950s Fairchild, late 1950s).
4
Planar Process

The Sub Micron Transistor


Basic lithography process

SiO2

Multiple Devices
CMOS Transistors with Metal
Interconnects 5
MOS Vs CMOS

CMOS allows:

• High input impedance.


• 0 DC power dissipation.
• 0 and 1 voltage levels at Gnd and VDD.
• High ION, low IOFF.
• Highly flexible circuit/system design
6
Dennard Scaling

k=2

ITRS - 2003 version

Year of Production 2000 2002 2004 2007 2010 2013 2016 2018
Technology Node (nm) 180 130 90 65 45 32 22 14
MPU Gate Length 100 70 53 35 25 18 13 10
DRAM Bits/Chip (GB) .512 1 4 16 32 64 128 128
MPU Transistors (106) 550 1100 2200 4400 8800 14000

Supply Voltage (V) 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1.0 0.6-0.9 0.5-0.8 0.5-0.7

6
Non Ideal Scaling
VG + VD

N+ N+

Inverse slope

6
Beyond Ideal Scaling - Innovations

6
The two limited Regimes

TSMC
Intel

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