CPE 110408343

Fundamentals of Computer Architecture

Chapter 19 (11th Edition)

Control Unit Operation

Dr. Khalil Yousef

[Computer Engineering Department, Hashemite University]

1
 Review
• The execution of an instruction involves the execution of a sequence of substeps, generally called
cycles.
– For example, an execution may consist of fetch, indirect, execute, and interrupt cycles.

• Each cycle is in turn made up of a sequence of more fundamental operations, called micro-
operations.

• A single micro-operation generally involves:

– A transfer between registers
– A transfer between a register and an external bus
– A simple ALU operation.

2
 The Control Unit
• So far, we focused on machine instructions and the operations
performed by the processor to execute each instruction.

• What was left out of this discussion is exactly how each individual
operation is caused to happen.

• This is the job of the control unit.

3
 The Control Unit
• The portion of the processor that actually causes things to happen.

• Output: Issues control signals external to the processor to:

– Cause data exchange with memory and I/O modules.

• Output: Issues control signals internal to the processor to:

– Move data between registers
– Cause the ALU to perform a specified function
– Regulate other internal operations.

• Input to the control unit consists of:

– The instruction register
– Flags
– Control signals from external sources (e.g., interrupt signals).

4
 Control Unit- Inputs
• The inputs are:
• Clock
– This is how the control unit “keeps time.
– The control unit causes one micro-instruction (or set of parallel micro-instructions) for
each clock pulse
– This is sometimes referred to as the processor cycle time or the clock cycle time
– Need a counter or a time generator
• Instruction register
– The opcode and addressing mode of the current instruction are used to determine which
micro-operations to perform during the execute cycle.
– Opcode causes different control signals for each different instruction
– To simplify the control unit logic, there is a unique logic input for each opcode
– Decoder takes an encoded input and produces single output
– In general, a decoder will have n binary inputs and 2n binary outputs
• Flags
– Determine the status of the processor
– Determine the outcome of previous ALU operations
• Control signals from control
– The control bus portion of the system bus provides signals to the control unit
– Interrupts
– Acknowledgements

5
 Control Unit Outputs:
Control Signals
• Control Signals within the processor:
– Two Types
• Those that cause data to be moved from one register to another
• Those that activate specific ALU functions
• Control signals to control bus:
– Two Types
• Control signals to memory
• Control signals to I/O modules

6
The General Model of the Control Unit Showing All of Its Inputs
And Output

7
 Hardwired Implementation of
Control Unit with Decoded Inputs
With the previous two
refinements (Decoder and
Counter) the control unit can
be depicted as shown below:

Counter or

8
 Control Unit Recap
The external specifications
• Inputs
– Allow the control unit to determine the state of the system
• outputs
– Allow the control unit to control the behavior of the system.
– These are the

• The internal specification will not be covered in this course

• Next: The main functions of the control unit …

9
The Functional Description of What the Control
Unit Does
• The control unit performs two basic tasks:
– Sequencing: The control unit causes the processor to step through a series of micro-operations in
the proper sequence, based on the program being executed.
• Micro-operations are the functional or atomic operation of a processor.
• Each micro-operation is very simple and does very little.
• The concept of micro-operations serves as a guide to the design of the control unit, which will be discussed shortly
– Execution: The control unit causes each micro-operation to be performed.

• The key to how the control unit operates is the use of control signals on the micro-
operations.

10
 Micro-Operations
• The operations of a computer in executing a program consists of a
sequence of instruction cycles.

• Each cycle has a number of steps called sub-cycles

– Fetch, indirect, execute, and interrupt cycles (see pipelining)
– Fetch/execute cycles always occurring

• The execution of each sub-cycle involves one or more shorter

operations, called micro-operations.

11
Constituent Elements of
Program Execution

12
 Micro-Operations (Cont...)
• Each micro-operation is very simple and does very little

• Micro-operations are the functional or atomic operation of a processor

• The types of micro-operations processor performs

1. Transfer data between registers
2. Transfer data from register to external
3. Transfer data from external to register
4. Perform arithmetic or logical ops

13
 The Fetch Cycle
• Occurs at the beginning of each instruction cycle
• Causes an instruction to be fetched from memory.
• We assume the organization as depicted below

14
 The Fetch Cycle - 4 Registers
• Memory Address Register (MAR)
– Connected to address lines of the system bus
– Specifies address for read or write op
• Memory Buffer Register (MBR)
– Connected to data lines of the system bus
– Holds data to write to memory or last data to read from memory
• Program Counter (PC)
– Holds address of next instruction to be fetched
• Instruction Register (IR)
– Holds last instruction fetched

15
 The Fetch Cycle – Sequence of events

• Address of next instruction is in PC

• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data
bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with data
fetch from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches

16
 The Fetch Cycle – Sequence of events
• The simple fetch cycle actually consists of three steps and four micro-
operations.

• Each micro-operation involves the movement of data into or out of a

register.

• So long as these movements do not interfere with one another, several

of them can take place during one step, saving time.

17
 Fetch Sequence (Symbolic)
3 Steps 4 Micro- 3 Steps 4 Micro-
Operations Operations

• t1: MAR <- (PC) • t1: MAR <- (PC)

• t2: MBR <- (memory) • t2: MBR <- (memory)
PC <- (PC) +1 OR • t3: PC <- (PC) +1
• t3: IR <- (MBR) IR <- (MBR)
(tx = time unit/clock cycle)
Grouping
Data Bus

Increment

18
 Rules for Clock Cycle Grouping
• The proper sequence of events must be followed
– MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
– Must not read & write same register at same time. Otherwise the results would
be unpredictable.
– Example: MBR <- (memory) & IR <- (MBR) must not be in same cycle

• Also: PC <- (PC) +1 involves addition

– To avoid duplication of circuitry, this addition could be performed by the ALU
– The use of the ALU may involve additional micro-operations May need additional
micro-operations

19
 The Indirect Cycle
• Once an instruction is fetched, the next step is to fetch source
operands.
• Continuing our simple example:
– Let’s assume a one-address instruction format, with direct and
indirect addressing allowed.
– If the instruction specifies an indirect address (refer to Chapter 11 –
page 422), then an indirect cycle must precede the execute cycle.
– This requires the following micro-operations

20
 The Indirect Cycle
• t1: MAR <- (IRaddress) - address field of IR
• t2: MBR <- (memory)
• t3: IRaddress <- (MBRaddress)

• The parentheses are to be interpreted as meaning “contents of”.

• The address field of the instruction is transferred to the MAR.
• This is then used to fetch the address of the operand.
• Finally, the address field of the IR is updated from the MBR, so that it now contains a direct rather
than an indirect address.
• The IR is now in the same state as if indirect addressing had not been used, and it is ready for the
execute cycle.
• We skip the execute cycle for a moment, to consider the interrupt cycle.

21
 The Interrupt Cycle
• At the completion of the execute cycle, a test is made to
determine whether any enabled interrupts have occurred.

• If so, the interrupt cycle occurs.

• We now present a very simple sequence of events occur during

the interrupt cycle

22
 The Interrupt Cycle
• t1: MBR <-(PC) • Then the MAR is loaded with the address at which
the contents of the PC are to be saved, and the PC is
• t2: MAR <- save-address loaded with the address of the start of the
interrupt-processing routine.
• PC <- routine-address – These two actions may each be a single micro-operation
• t3: memory <- (MBR) (refer to the book for further details)

• The final step is to store the MBR, which contains

• In the first step, the contents of the PC are the old value of the PC, into memory.
transferred to the MBR, so that they can be saved
for return from the interrupt. • The processor is now ready to begin the next
instruction cycle.
• Note: saving context is done by interrupt handler
routine, not micro-ops

23
 The Execute Cycle
• The fetch, indirect, and interrupt cycles are simple and
predictable.

• Each involves a small, fixed sequence of micro-operations and,

in each case, the same micro-operations are repeated each
time around.

• This is not true of the execute cycle.

– Because of the variety opcodes, there are a number of different
sequences of micro-operations that can occur.
• Different for each instruction
– Let us consider several hypothetical examples.
• First, consider an add instruction.

24
 Execute Cycle (ADD)
• ADD R1,X
– Add the contents of location X to Register 1 , result in R1

• The following sequence of micro-operations might occur:

– t1: MAR <- (IR(address)) •We begin with the IR containing the ADD
– t2: MBR <- (memory) instruction.
•In the first step, the address portion of the IR
– t3: R1 <- (R1) + (MBR) is loaded into the MAR.
•Then the referenced memory location is read.
•Finally, the contents of R1 and MBR are
• Note no overlap of micro-operations added by the ALU.

25
 Execute Cycle (ISZ)
• ISZ X
– Increment and skip if zero
– The content of location X is incremented by 1. If the result is 0, the next instruction is skipped.

• A possible sequence of micro-operations is

– t1: MAR <- (IR(address))
– t2: MBR <- (memory)
– t3: MBR <- (MBR) + 1
– t4: memory <- (MBR)
if (MBR) == 0 then PC <- (PC) + 1

• Notes:
– This test and action can be implemented as one micro-operation.
– this micro-operation can be performed during the same time unit during which the updated value in MBR is
stored back to memory (t4).

26
 Recap
• We have seen that each phase of the instruction cycle can be decomposed into a
sequence of elementary micro-operations.

• In our example, there is one sequence each for the fetch, indirect, and interrupt
cycles, and, for the execute cycle, there is one sequence of micro-operations for
each opcode.

• To complete the picture, we need to tie sequences of micro-operations together

28
 Instruction Cycle
• We assume a new 2-bit register called the Instruction Cycle
Code (ICC).
• The ICC designates the state of the processor in terms of which
portion of the cycle it is in:
– 00: Fetch
– 01: Indirect
– 10: Execute
– 11: Interrupt

29
 The Instruction Cycle
• At the end of each of the four cycles, the ICC is set appropriately.
– The indirect cycle (01) is always followed by the execute cycle (10).
– The interrupt cycle (11) is always followed by the fetch cycle (00).
– For both the fetch (00) and execute cycles (10), the next cycle depends on the state of the system.
– Thus, the flowchart of the Figure in the next slide defines the complete sequence of micro-operations, depending only on the instruction
sequence and the interrupt pattern.

• Of course, this is a simplified example. The flowchart for an actual processor would be more complex.

• In any case, we have reached the point in our discussion in which the operation of the processor is defined as
the performance of a sequence of micro-operations.

• We can now consider how the control unit causes this sequence to occur.

30
 Flowchart for Instruction Cycle

01

Fetch Execute
cycle cycle

Execute Indirect
cycle cycle

Interrupt Fetch
cycle cycle 31
 The Use of Control Signals
• Let us consider again the fetch cycle to see how the control
unit maintains control.

• The control unit keeps track of where the fetch cycle is in the
instruction cycle

32
 Example Control Signal Sequence - Fetch
• MAR <- (PC)
– The first step is to transfer the contents of the PC to the MAR.
– The control unit does this by activating the control signal that opens
the gates between the bits of the PC and the bits of the MAR.
• MBR <- (memory)
– The next step is to read a word from memory into the MBR and
increment the PC.
– The control unit does this by sending the following control signals
simultaneously:
• Open gates between MAR and address bus
• Memory read control signal on the control bus
• Open gates between data bus and MBR
• Control signals to logic that add 1 to the contents of the PC and store the result
back to the PC

• Following this, the control unit sends a control signal that

opens gates between the MBR and the IR.
33
 Figure 19.5
Data Paths and Control Signals
C5

M C11
B
R
C10
C12 C3 C4
C8 C1 AC

PC IR
C7 C9
C6

C2 C13 Control
C0 ALU signals
M
A
R Control
Flags
unit

Clock
Control
signals
34
 Table 19.1
Micro-operations and Control Signals
Micro-operations Active Control Signals

t1: MAR ← (PC) C2

Fetch: t2: MBR ← Memory

C5, CR
PC ← (PC) + 1
t3: IR ← (MBR) C4

t1: MAR ← (IR(Address)) C8

Indirect: t2: MBR ← Memory C5, CR

t3: IR(Address) ← (MBR(Address)) C4

t1: MBR ← (PC) C1

t2 : MAR ← Save-address
Interrupt:
PC ← Routine-address

t3: Memory ← (MBR) C12, CW

CR = Read control signal to system bus. (Table can be found on page 681in the textbook.)

CW = Write control signal to system bus.

35
 The End
• Please Read Chapter 19, 11th edition.

36