LIMITATIONS OF THE STUCK-AT FAULT MODEL AS AN ACCURATE MEASURE OF CMOS IC
QUALITY AND A PROPOSED SCHEMATIC LEVEL FAULT MODEL
Robert J. Lipp
Crosscheck Technology, Inc.
2001 Gateway Place, #301 East
San Jose, CA 95110
ABSTRACT classical [stuck-at] fault model can Only
account for 64 percent of the faults. It
Limitations in current testability should be noted, however, that this Only
approaches have forced major compromises illustrates the weakness of the classical
in IC fault modeling, test and quality. fault model and not the weakness of the
The stuck-at fault model is inadequate to
achieve world class quality. Meaningful
test sets .. .I1. To my knowledge, no
empirical studies have been published
CMOS fault models based upon relating actual IC quality to stuck-at
schematically
presented .
extracted faults are
Unity observability, the
fault coverage .Without quantitative
evidence of the acceptability of the
ability to probe all nodes, is presented present models, concentrating on ever
as a practical approach to effective use higher fault coverage is not necessarily
of these models. the most productive approach to high
quality. Development and use of accurate
fault models may offer significantly
INTRODUCTION higher returns.
Traditionally, the quality of a
functional test program has been measured LIMITATIONS E CONVENTIONAL MODELING
by its level of fault coverage. A fault
is inserted by forcing a node to a The stuck-at model assumes any defect can
logical Itone'' or @'zero1@ .The test be modeled as a short to power or ground.
pattern is then simulated to see if the It is a *Ihardt1short and it is static,
fault can be detected by creating deviant independent of patterns. It is commonly
behavior at any of the circuit's outputs. used for single faults only; multiple
f-iults are very difficult to handle. It
This technique has been an effective tool does not consider some of the most
for generating and analyzing test
programs. Its simplicity made it amenable
prevalent failure modes, (e .g .
shorted
interconnect). It does not even test for
to automation. Higher fault coverage has basic functionality. It lacks any direct
been shown to have a meaningful impact on relationship with real manufacturing
product quality . For example, an defects and the percentage fault coverage
experiment by Motorola found a direct does not relate in any meaningful fashion
correlation of fault coverage to quality to the density of defects distribution,
in testing the MC6802. [lo] .
In that
example, an increase in stuck-at fault
and therefore, actual chip quality.
coverage from 96.6% to 99.9% resulted in A simple example of the stuck-at
0 .8% additional reject rate . In other limitation regarding functionality is the
words a coverage rate of 96.6%, excellent
by today's standards, resulted in
exclusive-or gate .
Since neither input
needs to be in any particular state to
shipping devices of which at least 0.8% propagate a fault, a pattern set
were defective . This is at least two sufficient to check functionality is not
orders of magnitude below acceptable
standards. Additional studies such as
guaranteed . Complete stuck-at coverage
does not require both the (11) and (00)
this would be very interesting, and easy pattern sets. Figure 1 illustrates a
to do, yet this is the only published
work in this area.
comqon exclusive-or/nor schematic If .
either pattern is missing, two FETs are
not tested. By observation one can see
Theoretical work has been done to that if the (00) pattern is missing, two
correlate the stuck-at model to actual parallel n-channel FETs are not tested
manufacturing defects [4]. This thorough
study indicated that , "at best , the
for shorts . If the (11) pattern is
missing, two parallel p-channel FETs are
26.2.1
IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE CH2671-6/89/0000-0164$1.00 '1989 IEEE
not tested for opens . The gate is may require sequential patterns, faults
therefore not guaranteed to operate may be detected only with certain select
functionally for the untested pattern patterns, device stacking order may be
set. important and even the selection of an
And or OR shorting model may be dependent
An example of improper fault ftweighting8f not only upon the class of gates shorted,
is illustrated by comparing a flip-flop but may change during simulation
with two inputs and two outputs and a 3- depending upon their relative input
input Nand gate. The flip-flop has 2 4 states [l-91 . Patterns sets sufficient
transistors while the Nand gate has 6 for these tasks may be difficult or
transistors. Each has 8 faults, four 1/0 impossible to achieve.
signals which can be stuck at either
IIone" or "zero" . Yet the flip-flop It would appear then that the adoption of
contains four times the circuitry . any significantly improved modeling and
Another example of improper weighting is fault grading is doomed to inevitably
interconnect. An open interconnect is sink into the abyss of impracticality.
reasonably modeled by stuck-at. However, Computing power and practical test
an interconnect which traverses the chip lengths seem woefully inadequate when
has the same weighting as an interconnect sized up against the required task.
to an adjacent element . For fault
grading to be useful as a measure of
quality, these faults should have --
DEFECT MODELS
different weights.
A very useful and practical fault model
In summary, the stuck-at model is clearly can be developed by concentrating on
inadequate when world class quality is possible manufacturing defects extracted
desired. The standard for IC quality is from transistor schematics . This is
rapidly approaching the six sigma limit, significantly different from the more
or 3dpm. It has been demonstrated that traditional llfaultslf, the observable
traditional fault grading can effect of the defect on the electrical
deterministically grade less than 75% of operation of the circuit. This is also
the possible defect types in a CMOS IC. somewhat different than proposed explicit
It is even worse if one considers the manufacturing defect models proposed by
probability distribution of the probable .
others [ 4 ] [ 6 ] Possible opens and
defects detected versus non detected , shorts between nodes are calculated using
Very high fault coverage merely gives a schematic drawings as the primary source
"warm fuzzytqabout the level of quality. document . The electrical effects of
It more closely relates to the nodal these potential defects is calculated.
activity of the circuit and the Sensitization and measurement conditions
probability that a fault will propagate needed to detect them are determined .
from its origin. For example, a shorting defect may be
observable only when the inputs are in
Guaranteed high quality requires high one unique state and result in an
fault coverage using fault models based intermediate voltage level requiring a
upon actual possible defects and their voltage comparator: a weak or open device
distribution. Possible defects must be may require current injection. Net level
determined: the faults they create must shorts are modeled separately from gate
be modeled: and methods for detecting level.
them must be addressed.
If fault modeling is then to be used as
an accurate measure of quality, the
actual manufacturing defects responsible
CURRENT RESEARCH for these schematic level faults may be
calculated [l].
Modeling and fault grading have been
attacked with some limited success Several manufacturing defects can usually
Stuck-at modeling has been expanded by be mapped unto the same schematic level
several sources to include several common fault. One example is an open FET. The
real world defect types. For example, FET may be open due to either diffusion,
metal bridging shorts have been modeled metal or contact opens in series with the
by And or Or gates between the bridging source or drain. Alternately, an open
lines. Such models may be theoretically gate poly will be capacitively coupled to
effective but often impractical, the substrate, turning off the FET.
stressing the largest computing
resources. It turns out that schematic based defect
CMOS has many potential failure modes models are actually more straightforward
that are resistant to practical modeling to develop than explicit manufacturing or
via stuck-ats and simple shorts. Opens electrical operation based fault models.
26.2.2
may be noise or operating condition
Potential defects, even through quite
large in number, are usually fewer in sensitive [SI . Additionally, certain
number. And all the possible of fault open faults may require a two pattern set
modes, with pattern sensitivities and for sensitization and propagation [ 7 ] .
structure variations included, are
exceedingly difficult to evaluate for Deterministic detection of all these
complex cells. Postulating all schematic defects are possible, often with reduced
based manufacturing faults and pattern sets, by directly probing every
determining the way to detect them is node and making conventional analog
straightforward, accurate and effective. measurements.
The model can be illustrated with a CMOS This is very much akin to the "good old
two input Nand, Figure 2. The potential days" of SSI .NQbody ever seriously
defects are illustrated with dashed lines considered not testing the output current
showing the potential open and short drive and voltage levels of a component.
locations. As described above, multiple Somehow we all have convinced ourselves
types of defects responsible for similar that this is not necessary in the era of
failures are not shown. LSI and VLSI . This is mere
rationalization. Yield and quality haqe
indeed improved, but not in proportion to
Of the 26 possible defects shown, only 16
can be deterministically detected with the density of integration . Device
the stuck-at fault model. For example, a quality has to improve considerably
shorted n-channel FET may or may not be before the need to test is obviated. It
detected, as it affects the high output is impossible to test an IC in every
voltage level, VOH , not the possible functional mode, at speed and at
functionality. An open p-channel FET is all operating conditions and at every
likewise not deterministically detected possible pattern combination . It is
because of possible charge storage on the physically impossible to even determine
output node. the minimum test set that will completely
test a complex IC from measurements at
Models for larger logic elements can be its outputs alone.
quite complex. A D-type flip-flop has
over 150 possible potential defect sites. The only option is to return to original
concepts . If we probe and test every
component individually, and then check
DEFECT DETECTION the interconnect for continuity and
shorts, the device must be good. Trying
After a Defect Model is built, each to thoroughly test the IC as a functional
defect must be analyzed to determine its block is a losing battle, one that gets
fault effect upon the cperation of the more difficult every year.
logic element. That effect must then be
propagated to an observation point for
detection. The three possible detection UNITY OBSERVABILITY
points are: internal to the element, at
the output of the element and after Electronically probing every node in
propagation through other element(s). vivo, what is called unity observability,
is possible and practical, but it is a
Conventionally, faults are detected after paradigm shift. A 20,000 gate circuit
propagation through other elements and may have 10,000 nodes, a seemingly
then to the output. This method is used impossible connection problem .
even for formal design-for-test Integrated circuits are efficient
techniques such as scan. The fault is substrates for regular two dimensional
therefore detected/not-detected and structures . The general problem of
rebuffered by the first logic element probing 10,000 nodes on an IC requires
through which it propagates. rethinking the problem. An orthogonal two
dimensional grid of 100 wires in each
This would be sufficient if all faults dimension can be used to address 10,000
were "hardti,if the defect forced the points. If the intersection of each pair
element to go to a solid but incorrect of wires contains an analog switch, each
floneffor "zero" value. However, as in point can be measured accurately, in an
the two input Nand example above, many of analog manner . Techniques have been
the defects cause *tsoft8f shorts, shorts developed to make this practical [ll].
that are not clearly a IIone" or "zero".
Such faults may be detected, or not Further processing may be used to either
detected depending upon the input compress the data to a more compact form
sensitivity of the logic element ( s ) they such as a signature, to serialize the
drive. They may cause transition faults. data to send off chip through a minimum
They may be pattern sensitive. Or, they pin configuration, or to analyze the
26.2.3
failure.
om
References
0
A
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26.2.4
