Reliable communication to multiple

BMICs for high voltage applications

March 2024

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Agenda
TI HEV/EV system overview

Proprietary daisy chain protocol

System level design considerations

Layout design considerations

Q&A
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TI BMIC evolution
2010 2015 2018 2020 2023

1st gen: PL536 2nd gen: PL455A 3rd gen: BQ79606A 4th gen: BQ7961x 5th gen: BQ7971x

Improved accuracy over the last decade 10 mV → 1 mV

Acceleration of 400-V to 800-V transition → more channels
Scalable, stackable communications
Why? Using an optimized, unique daisy chain communication protocol, the battery monitors can
be stacked to support various battery pack sizes.

400 V
800 V
1500 V

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High cell count design challenges
• Very high current (100s of ampere)
• Harsh noise environment (accuracy, communication)
• Wide temp range -40 – 125 ºC Battery
modules
• Physically larger battery pack
– More difficult to connect cells in order
– Cell connections more fragile (likely to break)
– Harness routing
• Thermal management
• Mechanical design
• Functional safety requirements in automotive

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Proprietary daisy chain protocol

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The daisy chain protocol
Why use the daisy chain protocol?
• Designed to minimize electromagnetic susceptibility
• Robust immunity against electromagnetic interference
• Easy to use ring architecture
What is the daisy chain protocol?
• Differential, bi-directional, half-duplex communication
interface
• Each data frame is 13-bits long
• BMIC extracts timing information using the preamble
and SYNC bits to decode the rest of the data frame
• Each bit transmitted at 2 MHz (250 ns per pulse or
500 ns per couplet)
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Receiver topology and common mode voltages
• BQ7971x is designed to
withstand +/- 25-V common
mode voltage swings due to EV
inverter noise or bulk current
injection
• RX topology is similar to RS-485
standard with additional design
mechanisms to attenuate
common mode voltages
• Above this +/- 25-V limit risks
clamping the internal ESD
structure and damaging COM
pins

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Signal integrity requirements
Proper receiver waveform timing and thresholds are critical factors for the internal digital
circuitry to correctly interpret data.

BQ7971x Parameters Condition Min Typ Max

Measure COMP-COMN from +1.2 V of rising
Positive pulse width 230 ns 250 ns 270 ns
edge to -1.2 V of next falling edge
Measure COMP-COMN from -1.2 V of falling
Negative pulse width 230 ns 250 ns 270 ns
edge to +1.2 V of next rising edge
Measure COMP-COMN from -1.2 V to +1.2 V
Rise slew rate 60 ns
of rising edge
Measure COMP-COMN from +1.2 V to -1.2 V
Fall slew rate 60 ns
of falling edge
Starting peak amplitude If ending amplitude is above 1.3 V 1.6 V
Starting peak amplitude If ending amplitude is b/w 1.2 V and 1.3 V 1.7 V

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Signal integrity requirements

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System level design considerations

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System level design
• MCU will interface with BQ79600 via SPI or UART
• BQ79600 converts SPI/UART commands to daisy chain to send data up the stack
– This is a power intensive process, recommended to use BQ79600 as base
– Option to use a BQ7971x as base, will consume much more power than stack devices

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Power consumption
• Stack one will consume the
most current, communicates
the longest
• Use IDDQ COMM function to
balance out communication
current imbalance
• Implement IDDQ STATIC to
passively burn current if the
number of cells is imbalanced

18-Cell 18-Cell 14-Cell

MCU BQ79600 BQ7971x BQ7971x BQ7971x

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Ring architecture
• If a break occurs in one
direction, can switch and
recover in the other direction
• Can switch communication
direction every safety diagnostic
cycle (FDTI) to reduce the
current skew between devices

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Timing example
• Re-clocking enables more devices to be stacked and longer daisy chains
– Each device retransmits data rather than a simple passthrough
– 4-us re-clocking time
• Devices will immediately forward responses down the daisy chain

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Layout design considerations

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Communication isolation
Cap-only isolation:
• Uses high voltage series caps to
isolate communication signals
• Cheapest solution
Cap-choke isolation:
• Same as cap-only but adds a
high inductance common mode
choke in series with the
capacitors
• Second to transformer in
robustness
Transformer isolation:
• Most robust but also most costly
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Layout considerations
• Keep differential traces as short as
possible and as straight as possible
• Keep differential traces on the same layer
with matching trace impedance
• Shield the differential traces from other
signals with ground pours, utilize via
stitching to ground
• Place isolation components close to the
connectors
• Place 220-pF bypass capacitor close to
COM pins
• Create a keep-out area with no other
traces or ground planes around isolation
components on all layers 18
Key takeaways
• Ensure daisy chain waveforms meet signal
integrity requirements
• Utilize IDDQ function and ring architecture to
reduce current skew
• Calculate system timing requirements
• Choose isolation components wisely
• Ensure to signal condition COM signals

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Q&A

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