Whitefield ,Bengaluru
Pritam 9148780240,9923598785
92pritampaul@gmail.com
https://www.linkedin.com/in/pritam-paul-
Paul 237237a0/
To work in an environment where I can apply myself for the betterment of my organization
through assertiveness and hard work, gaining knowledge and wisdom.
Skills
Excellent knowledge on Physical design tools like IC compiler, cadence, Design
compiler, Primetime.
Have completed PD of blocks from RTL to Gate level netlist to layout stage.
Good knowledge on physical verification flow at 10nm which exposed me to issues like
trclvs, drcd, ERC, MRC, density.
Tool Automation scripting language TCL/TK.
HDL languages like VERILOG & VHDL.
SOFTWARE languages like C/C++, python.
Strong vlsi fundamentals.
[8/2/2017] – [PRESENT]
Physical Design Engineer / Intel technologies, Bengaluru
Project 1: FIVR (CNL)
TOOL USED: ICC
TECHNOLOGY: 14nm
Description:
This project covers Physical verification at 10nm technology like
Implementing ECO’s, Design Rule Checks (DRC), Layout versus Schematic (LVS),
Density cleaning and Antenna and DFM Violations using the Synopsys EDA tools.
Responsibilities:
As a Mask designer, I was responsible for Physical verification for multiple partitions.
Design should be cleaned during Pre-base fill, Base fill and Metal Fill in all Layout
verification aspects such as DRC, LVS, Antenna and Density.
Project 2: GPIO
TOOL USED: ICC, DC, PRIMETIME
TECHNOLOGY: 10nm
Description:
This project covers synthesis of RTL to netlist using Design compiler to
layout through APR in ICC at 10nm technology. Thorough understanding of the
ASIC flow and different aspects of Floorplan, Placement and Timing.
Responsibilities:
hecking the timing violations using Primetime.
Different scenarios and commands to generate reports relating to timing closure for
different milestones.
PTSI to observe noise violation due to crosstalk and glitch.
PTPX for signoff power estimation.
Education
[08/08/2015] - [PRESENT]
Master of Science (Electronics science) / University of Pune
GPA – 7.3/10
COURSEWORK: IC Technology & CAD VLSI Tools, Advance VLSI Tools, VHDL/VERILOG
testing and verification. Specialized in VLSI and Embedded systems with experience in tools
like Xilinx, Cadence, Mentor Graphics, Lab view and LT-spice
[06/06/2011 – 15/06/2015]
Bachelor of Science (Electronics) / NEHU, Meghalaya
GPA – 8.3/10
COURSEWORK: Basics of electronics, analog and digital systems, network analysis, signal
processing.
[05/07/2009 – 5/06/2011]
12 / MBOSE, Meghalaya
Percentage – 70%
2
[05/07/2009]
10 / MBOSE, Meghalaya
Percentage – 85%
Personal Projects
Dark activated LDR:
A Light / Dark activated switch is a circuit that will measure the light level and will turn
on or off a relay accordingly. The sensitivity of the device was an important feature to
control. This technique ensures an automated and energy saving approach.
Linear Regulated Power Supply:
Using IC 7805 to produce a stable output devoid of any internal or external variations. A
Zener diode is used externally to provide input to the IC 2 volts more than the required
output for internal drop.
Water level indicator using Arduino:
Programming an Arduino using c language to indicate the level of water in a tank and
ring an alarm when it goes below a threshold level.
General competencies
Working in a team and contributing individually in the interests of the team.
Good communication and presentation skills gives me an edge in the
working environment.
Organized, composed and well-structured working style
Hobbies
Reading books
Playing musical instruments
Cooking
Travelling
Outdoor games
3
Languages
English
Hindi
Bengali
