Profile Information
Name: Uday Kumar V Email: udaykumarv0627@gmail.com
Phone: +91 8050442302 Address: #438, Mahaveer Willow Apartment,
Kengeri Satellite Town, Bengaluru,
Karnataka-560060
Core Competency
Worked on implementing ASIC flow (Synthesis to ECO) on multiple partitions with critical power,
area and timing budgets.
Designed floor-plans with high macro count and power-planned with strict IR drops and power
budgets.
Synthesized clock tree (CTS) while meeting targets like max skew and min/max insertion delay.
Hands-on experience in generating and analyzing timing reports of per-layout and post-layout STA
on PrimeTime with OCV and Xtalk, and resolved timing violations.
Converged the design for multiple modes and multiple corners (MCMM).
Performed timing closure and cleared Caliber violations on various technologies with aggressive
timing and power budgets.
Analyzed DFM issues (Antenna violations) and fixed DFM violations.
Worked on DFT related concepts like scan-chains and performed re-ordering to optimize it.
Executed physical verification checks like DRC and LVS. Fixed violations related to the same.
Working on Linux and automated various analysis and violation fixes by scripting.
Education Details
Degree Discipline University/Board Year of passing Aggregate
PG Diploma ASIC Physical Design RV-VLSI Design Center 2016 -
Degree Electronics and Visvesvaraya 2014 65
Instrumentation Technological University
PUC - Karnataka PU Board 2010 71
SSLC - Central Board of Secondary 2008 71
Education
Experience Details
Company Name Designation From To
Intel Corporation Graphics Design Engineer Oct,2016 Present
RV-VLSI Design Center Physical Design Engineer Trainee Oct,2015 Oct,2016
Tech Mahindra Associate Software Engineer Jan, 2015 Jul, 2015
Project Details
Company: Intel Corporation
Designation: Graphics Hardware Engineer
Duration: October 2016 – Present
Tools used:
DC Topo for synthesis.
IC Compiler for PNR flows and ECOs.
Prime Time for Timing analysis.
Work Experience:
Handled 3 partitions with multi-million gate count. Following were the issues faced.
Partition 1: This was a partition with around 1.4 million gate count, high port density (25ports/u), lot
of feedthroughs and converged with high util of 75%. The initial port placement was bad because
they were diagonally opposite and caused a lot of crisscross routing. This resulted in waste of routing
resources, large feedthrough delays and shorts in top level metal layers. I did a lot of port movements
after carefully analyzing its effects on neighboring partitions. The finalization of macro channels was
also critical because of high util. CTS needed a few iterations to finalize because of port movements.
Scope for buffer addition and upsizing was limited due to high util.
Partition 2: This was a section to section interface partition. This was converged at a very low util of
15% and had very little logic; but had a lot of top-level paths going through it. This was an odd
shaped partition and had a lot of shorts around the notches which was tough to resolve. Spreading the
cells apart but still providing least delay was a challenge.
Partition 3: This was a partition with a 4 large soft-macros. Initial area provided gave a very high
util of 78% at route. Discussed with section owner and got one lego of space; which brought down
util to 70%. Initial runs were crashing because util was shooting up beyond 100% at post-place
because of soft-macro bloat-up. Had to characterize the soft-macros so they don’t spread too much
and cause unnecessary buffer addition.
Project Title: Block level implementation on 40nm node
Institute Name: RV-VLSI Design Center
Project Description:
•Worked from the initial steps of building the library and setting up the tool to Place and Route.
•Experimented and setup different sets of libraries.
•Experimented with different ports and macro positions.
•Reduced area of block to converge it with high util.
•Experimented with different route and post-route flows
Tools Used:
•Library compiler for library development
•Synopsys ICC 2 for PD Implementation
Challenges:
•Training self on new tools using only tool manual in a limited time duration.
•Understanding new concepts and matching them with previous ICC version.
•Coming up with work-arounds for tool related bugs.
Project Title: Block level implementation on 180nm node
Institute Name: RV-VLSI Design Center
Project Description:
•Technology node 180nm
•Macros 32
•Standard cells 43,234
•Clocks 5 (3 Propagated, 2 generated)
•Operating frequency 400MHz
•Operating voltage 1.8V
•Max IR Drop (Vdd + Vss) 5% of Operating Voltage (90mV)
•Power budget 300mW
•Metal layers 6
Tools Used:
•Synopsys IC Compiler for complete PD flow
•Synopsys PrimeTime for STA
•Hercules from Synopsys and Calibre from Mentor Graphics for DRC and LVS
Challenges:
•Creating a floor-plan, keeping in mind its effects on further steps.
•Adjusting power straps to fix various bugs.
•Fixing various violations, using automation and not manually.
•Finding a common source for several violations.
•Analyzing and understanding LVS reports.
•Fixing timing violations such that it doesn’t cause even more timing or DRC violations.
