Sample-and-Hold

ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter with Internal
July 2006

ADC08200
8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D
Converter with Internal Sample-and-Hold
General Description Features
The ADC08200 is a low-power, 8-bit, monolithic analog-to- n Single-ended input
digital converter with an on-chip track-and-hold circuit. Opti- n Internal sample-and-hold function
mized for low cost, low power, small size and ease of use, n Low voltage (single +3V) operation
this product operates at conversion rates up to 230 MSPS n Small package
while consuming just 1.05 mW per MHz of clock frequency, n Power-down feature
or 210 mW at 200 MSPS. Raising the PD pin puts the
ADC08200 into a Power Down mode where it consumes
about 1 mW. Key Specifications
The unique architecture achieves 7.3 Effective Bits with n Resolution 8 Bits
50 MHz input frequency. The ADC08200 is resistant to n Maximum sampling frequency 200 MSPS (min)
latch-up and the outputs are short-circuit proof. The top and n DNL ± 0.4 LSB (typ)
bottom of the ADC08200’s reference ladder are available for n ENOB (fIN= 50 MHz) 7.3 bits (typ)
connections, enabling a wide range of input possibilities. The n THD (fIN= 50 MHz) 61 dB (typ)
digital outputs are TTL/CMOS compatible with a separate n Power Consumption
output power supply pin to support interfacing with 3V or — Operating 1.05 mW/MSPS (typ)
2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS — Power Down 1 mW (typ)
compatible. The output data format is straight binary.
The ADC08200 is offered in a 24-lead plastic package Applications
(TSSOP) and, while specified over the industrial temperature
n Flat panel displays
range of −40˚C to +85˚C, it will function over the to −40˚C to
+105˚C temperature range. An evaluation board is available n Projection systems
to assist in the easy evaluation of the ADC08200. n Set-top boxes
n Battery-powered instruments
n Communications
n Medical imaging
n Astronomy

Pin Configuration

20017901

© 2006 National Semiconductor Corporation DS200179 www.national.com

ADC08200
Ordering Information
Order Number Temperature Range Package
ADC08200CIMT −40˚C ≤ TA ≤ +105˚C TSSOP
ADC08200CIMTX −40˚C ≤ TA ≤ +105˚C TSSOP (tape and reel)
ADC08200EVAL Evaluation Board

Block Diagram

20017902

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

6 VIN Analog signal input. Conversion range is VRB to VRT.

Analog Input that is the high (top) side of the reference

ladder of the ADC. Nominal range is 0.5V to VA. Voltage
3 VRT
on VRT and VRB inputs define the VIN conversion range.
Bypass well. See Section 2.0 for more information.
Mid-point of the reference ladder. This pin should be
9 VRM bypassed to a quiet point in the ground plane with a 0.1
µF capacitor.
Analog Input that is the low side (bottom) of the
reference ladder of the ADC. Nominal range is 0.0V to
10 VRB (VRT – 0.5V). Voltage on VRT and VRB inputs define the
VIN conversion range. Bypass well. See Section 2.0 for
more information.

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 ADC08200
Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

Power Down input. When this pin is high, the converter is

23 PD in the Power Down mode and the data output pins hold
the last conversion result.

CMOS/TTL compatible digital clock Input. VIN is sampled

24 CLK
on the rising edge of CLK input.

13 thru 16 Conversion data digital Output pins. D0 is the LSB, D7 is

and D0–D7 the MSB. Valid data is output just after the rising edge of
19 thru 22 the CLK input.

7 VIN GND Reference ground for the single-ended analog input, VIN.
Positive analog supply pin. Connect to a quiet voltage
source of +3V. VA should be bypassed with a 0.1 µF
1, 4, 12 VA
ceramic chip capacitor for each pin, plus one
10 µF capacitor. See Section 3.0 for more information.
Power supply for the output drivers. If connected to VA,
18 VDR
decouple well from VA.
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.

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ADC08200
Absolute Maximum Ratings Operating Ratings (Notes 1, 2)
(Notes 1, 2) Operating Temperature Range −40˚C ≤ TA ≤ +105˚C
If Military/Aerospace specified devices are required, Supply Voltage (VA) +2.7V to +3.6V
please contact the National Semiconductor Sales Office/
Driver Supply Voltage (VDR) +2.4V to VA
Distributors for availability and specifications.
Ground Difference |GND - DR GND| 0V to 300 mV
Supply Voltage (VA) 3.8V
Upper Reference Voltage (VRT) 0.5V to (VA −0.3V)
Driver Supply Voltage (VDR) VA +0.3V
Lower Reference Voltage (VRB) 0V to (VRT −0.5V)
Voltage on Any Input or Output
VIN Voltage Range VRB to VRT
Pin −0.3V to VA
Reference Voltage (VRT, VRB) VA to AGND
CLK, PD Voltage Range −0.05V to
Package Thermal Resistance
(VA + 0.05V) Package θJA
Input Current at Any Pin (Note 3) ± 25 mA 24-Lead TSSOP 92˚C/W
Package Input Current (Note 3) ± 50 mA
Power Dissipation at TA = 25˚C See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model 2500V
Machine Model 200V
Soldering Temperature, Infrared,
10 seconds (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8)
Typical Limits Units
Symbol Parameter Conditions
(Note 9) (Note 9) (Limits)
DC ACCURACY
+1.0 +1.9 LSB (max)
INL Integral Non-Linearity
−0.3 −1.2 LSB (min)
DNL Differential Non-Linearity ± 0.4 ± 0.95 LSB (max)
Missing Codes 0 (max)
FSE Full Scale Error 36 50 mV (max)
VOFF Zero Scale Offset Error 46 60 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
VRB V (min)
VIN Input Voltage 1.6
VRT V (max)
(CLK
3 pF
LOW)
CIN VIN Input Capacitance VIN = 0.75V +0.5 Vrms
(CLK
4 pF
HIGH)
RIN RIN Input Resistance >1 MΩ
BW Full Power Bandwidth 500 MHz
VA V (max)
VRT Top Reference Voltage 1.9
0.5 V (min)
VRT − 0.5 V (max)
VRB Bottom Reference Voltage 0.3
0 V (min)
VRT - 1.0 V (min)
Reference Voltage Delta 1.6
VRB 2.3 V (max)
120 Ω (min)
RREF Reference Ladder Resistance VRT to VRB 160
200 Ω (max)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH Logical High Input Voltage VDR = VA = 3.6V 2.0 V (min)

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 ADC08200
Converter Electrical Characteristics (Continued)

The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8)
Typical Limits Units
Symbol Parameter Conditions
(Note 9) (Note 9) (Limits)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIL Logical Low Input Voltage VDR = VA = 2.7V 0.8 V (max)
IIH Logical High Input Current VIH = VDR = VA = 3.6V 10 nA
IIL Logical Low Input Current VIL = 0V, VDR = VA = 2.7V −50 nA
CIN Logic Input Capacitance 3 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High Level Output Voltage VA = VDR = 2.7V, IOH = −400 µA 2.6 2.4 V (min)
VOL Low Level Output Voltage VA = VDR = 2.7V, IOL = 1.0 mA 0.4 0.5 V (max)
DYNAMIC PERFORMANCE
fIN = 4 MHz, VIN = FS − 0.25 dB 7.5 Bits
fIN = 20 MHz, VIN = FS − 0.25 dB 7.4 Bits
ENOB Effective Number of Bits fIN = 50 MHz, VIN = FS − 0.25 dB 7.3 6.9 Bits (min)
fIN = 70 MHz, VIN = FS − 0.25 dB 7.2 Bits
fIN = 100 MHz, VIN = FS − 0.25 dB 7.0 Bits
fIN = 4 MHz, VIN = FS − 0.25 dB 47 dB
fIN = 20 MHz, VIN = FS − 0.25 dB 46 dB
SINAD Signal-to-Noise & Distortion fIN = 50 MHz, VIN = FS − 0.25 dB 46 43.3 dB (min)
fIN = 70 MHz, VIN = FS − 0.25 dB 45 dB
fIN = 100 MHz, VIN = FS − 0.25 dB 44 dB
fIN = 4 MHz, VIN = FS − 0.25 dB 47 dB
fIN = 20 MHz, VIN = FS − 0.25 dB 46 dB
SNR Signal-to-Noise Ratio fIN = 50 MHz, VIN = FS − 0.25 dB 46 43.4 dB (min)
fIN = 70 MHz, VIN = FS − 0.25 dB 45 dB
fIN = 100 MHz, VIN = FS − 0.25 dB 44 dB
fIN = 4 MHz, VIN = FS − 0.25 dB 60 dBc
fIN = 20 MHz, VIN = FS − 0.25 dB 58 dBc
SFDR Spurious Free Dynamic Range fIN = 50 MHz, VIN = FS − 0.25 dB 60 dBc
fIN = 70 MHz, VIN = FS − 0.25 dB 57 dBc
fIN = 100 MHz, VIN = FS − 0.25 dB 54 dBc
fIN = 4 MHz, VIN = FS − 0.25 dB −60 dBc
fIN = 20 MHz, VIN = FS − 0.25 dB −58 dBc
THD Total Harmonic Distortion fIN = 50 MHz, VIN = FS − 0.25 dB −60 dBc
fIN = 70 MHz, VIN = FS − 0.25 dB -56 dBc
fIN = 100 MHz, VIN = FS − 0.25 dB −53 dBc
fIN = 4 MHz, VIN = FS − 0.25 dB −66 dBc
fIN = 20 MHz, VIN = FS − 0.25 dB -68 dBc
HD2 2nd Harmonic Distortion fIN = 50 MHz, VIN = FS − 0.25 dB −66 dBc
fIN = 70 MHz, VIN = FS − 0.25 dB -60 dBc
fIN = 100 MHz, VIN = FS − 0.25 dB −55 dBc
fIN = 4 MHz, VIN = FS − 0.25 dB −72 dBc
fIN = 20 MHz, VIN = FS − 0.25 dB −58 dBc
HD3 3rd Harmonic Distortion fIN = 50 MHz, VIN = FS − 0.25 dB −72 dBc
fIN = 70 MHz, VIN = FS − 0.25 dB -58 dBc
fIN = 100 MHz, VIN = FS − 0.25 dB −60 dBc
f1 = 11 MHz, VIN = FS − 6.25 dB
IMD Intermodulation Distortion -55 dBc
f2 = 12 MHz, VIN = FS − 6.25 dB

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ADC08200
Converter Electrical Characteristics (Continued)

The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8)
Typical Limits Units
Symbol Parameter Conditions
(Note 9) (Note 9) (Limits)
POWER SUPPLY CHARACTERISTICS
DC Input 69.75 86 mA (max)
IA Analog Supply Current
fIN = 10 MHz, VIN = FS − 3 dB 69.75 mA
IDR Output Driver Supply Current DC Input, PD = Low 0.25 0.6 mA (max)
DC Input, PD = Low 70 86.6 mA (max)
IA + IDR Total Operating Current
CLK Low, PD = Hi 0.3 mA
DC Input, Excluding Reference 210 260 mW (max)
PC Power Consumption
CLK Low, PD = Hi 1 mW
FSE change with 2.7V to 3.3V change
PSRR1 Power Supply Rejection Ratio 54 dB
in VA
SNR reduction with 200 mV at 1MHz
PSRR2 Power Supply Rejection Ratio 45 dB
on supply
AC ELECTRICAL CHARACTERISTICS
fC1 Maximum Conversion Rate 230 200 MHz (min)
fC2 Minimum Conversion Rate 10 MHz
tCL Minimum Clock Low Time 0.87 1.0 ns (min)
tCH Minimum Clock High Time 0.65 0.75 ns (min)
CLK to Data Invalid, VA = 3.3V to
Output Hold Time, Output Falling
3.6V, tA = −40˚C to +105˚C, CL = 8 2.4 3.3 ns (max)
(Note 10)
pF
tOH
CLK to Data Invalid, VA = 3.3V to
Output Hold Time, Output Rising
3.6V, tA = −40˚C to +105˚C, CL = 8 1.9 2.5 ns (max)
(Note 10)
pF
CLK to Data Transition, VA = 3.3V to 2.4 ns (min)
Output Delay, Output Falling
3.6V, VA = −40˚C to +105˚C, CL = 8 3.9
(Note 10) 5.1 ns (max)
pF
tOD
CLK to Data Transition, VA = 3.3V to 2.4 ns (min)
Output Delay, Output Rising
3.6V, tA = −40˚C to +105˚C, CL = 8 3.3
(Note 10) 4.0 ns (max)
pF
Output Falling, VA = 3.3V, CL = 8 pF,
0.73 V/ns
tA = −40˚C to +105˚C
tSLEW Output Slew Rate
Output Rising, VA = 3.3V, CL = 8 pF,
0.88 V/ns
tA = −40˚C to +105˚C
Pipeline Delay (Latency) 6 Clock Cycles
tAD Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns
tAJ Aperture Jitter 2 ps rms

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or VDR), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation listed above will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.

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 ADC08200
Converter Electrical Characteristics (Continued)
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input
voltage must be ≤2.8VDC to ensure accurate conversions.

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Note 8: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 10: These specifications are guaranteed by design and not tested.
Note 11: Typical output slew rate is based upon the maximum tOD and tOH figures.

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ADC08200
Specification Definitions sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
APERTURE (SAMPLING) DELAY is that time required after Pipeline Delay plus the Output Delay.
the rise of the clock input for the sampling switch to open.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
The Sample/Hold circuit effectively stops capturing the input
sure of how well the ADC rejects a change in the power
signal and goes into the “hold” mode tAD after the clock goes
supply voltage. For the ADC08200, PSRR1 is the ratio of the
high.
change in Full-Scale Error that results from a change in the
APERTURE JITTER is the variation in aperture delay from DC power supply voltage, expressed in dB. PSRR2 is a
sample to sample. Aperture jitter shows up as input noise. measure of how well an AC signal riding upon the power
CLOCK DUTY CYCLE is the ratio of the time that the clock supply is rejected from the output and is here defined as
wave form is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 200 MSPS with a ramp input.
where SNR0 is the SNR measured with no noise or signal on
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE the supply line and SNR1 is the SNR measured with a
BITS) is another method of specifying Signal-to-Noise and 1 MHz, 200 mVP-P signal riding upon the supply lines.
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
1.76) / 6.02 and says that the converter is equivalent to a
dB, of the rms value of the input signal at the output to the
perfect ADC of this (ENOB) number of bits.
rms value of the sum of all other spectral components below
FULL POWER BANDWIDTH is a measure of the frequency one-half the sampling frequency, not including harmonics or
at which the reconstructed output fundamental drops 3 dB d.c.
below its low frequency value for a full scale input.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
FULL-SCALE ERROR is a measure of how far the last code SINAD) is the ratio, expressed in dB, of the rms value of the
transition is from the ideal 11⁄2 LSB below VRT and is defined input signal at the output to the rms value of all of the other
as: spectral components below half the clock frequency, includ-
Vmax + 1.5 LSB – VRT ing harmonics but excluding d.c.
where Vmax is the voltage at which the transition to the SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
maximum (full scale) code occurs. ence, expressed in dB, between the rms values of the input
INTEGRAL NON-LINEARITY (INL) is a measure of the signal at the output and the peak spurious signal, where a
deviation of each individual code from a line drawn from zero spurious signal is any signal present in the output spectrum
scale (1⁄2 LSB below the first code transition) through positive that is not present at the input.
full scale (1⁄2 LSB above the last code transition). The devia- TOTAL HARMONIC DISTORTION (THD) is the ratio ex-
tion of any given code from this straight line is measured pressed in dB, of the rms total of the first nine harmonic
from the center of that code value. The end point test method levels at the output to the level of the fundamental at the
is used. Measured at 200 MSPS with a ramp input. output. THD is calculated as
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS. where Af1 is the RMS power of the fundamental (output)
MISSING CODES are those output codes that are skipped frequency and Af2 through Af10 are the RMS power of the
and will never appear at the ADC outputs. These codes first 9 harmonic frequencies in the output spectrum
cannot be reached with any input value. ZERO SCALE OFFSET ERROR is the error in the input
OUTPUT DELAY is the time delay after the rising edge of voltage required to cause the first code transition. It is de-
the input clock before the data update is present at the fined as
output pins. VOFF = VZT − VRB
OUTPUT HOLD TIME is the length of time that the output where VZT is the first code transition input voltage.
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-

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 ADC08200
Timing Diagram

20017931

FIGURE 1. ADC08200 Timing Diagram

Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless other-
wise stated
INL INL vs. Temperature

20017908 20017914

INL vs. Supply Voltage INL vs. Sample Rate

20017915 20017910

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ADC08200
Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless
otherwise stated (Continued)

DNL DNL vs. Temperature

20017909 20017917

DNL vs. Supply Voltage DNL vs. Sample Rate

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SNR vs. Temperature SNR vs. Supply Voltage

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 ADC08200
Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless
otherwise stated (Continued)

SNR vs. Sample Rate SNR vs. Input Frequency

20017912 20017923

SNR vs. Clock Duty Cycle Distortion vs. Temperature

20017924 20017925

Distortion vs. Supply Voltage Distortion vs. Sample Rate

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ADC08200
Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless
otherwise stated (Continued)

Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle

20017928 20017929

SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage

20017930 20017938

SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Input Frequency

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 ADC08200
Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless
otherwise stated (Continued)

SINAD/ENOB vs. Clock Duty Cycle Power Consumption vs. Sample Rate

20017940 20017919

Spectral Response @ fIN = 50 MHz Spectral Response @ fIN = 76 MHz

20017946 20017947

Spectral Response @ fIN = 99 MHz Intermodulation Distortion

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ADC08200
Functional Description The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the
The ADC08200 uses a new, unique architecture that power down mode, where the output pins hold the last
achieves over 7 effective bits at input frequencies up to and conversion before the PD pin went high and the device
beyond 100 MHz. consumes just 1.4 mW . Holding the clock input low will
The analog input signal that is within the voltage range set by further reduce the power consumption in the power down
VRT and VRB is digitized to eight bits. Input voltages below mode to about 1 mW.
VRB will cause the output word to consist of all zeroes. Input
voltages above VRT will cause the output word to consist of Applications Information
all ones.
Incorporating a switched capacitor bandgap, the ADC08200 1.0 REFERENCE INPUTS
exhibits a power consumption that is proportional to fre- The reference inputs VRT and VRB are the top and bottom of
quency, limiting power consumption to what is needed at the the reference ladder, respectively. Input signals between
clock rate that is used. This and its excellent performance these two voltages will be digitized to 8 bits. External volt-
over a wide range of clock frequencies makes it an ideal ages applied to the reference input pins should be within the
choice as a single ADC for many 8-bit needs. range specified in the Operating Ratings table. Any device
Data is acquired at the rising edge of the clock and the digital used to drive the reference pins should be able to source
equivalent of that data is available at the digital outputs 6 sufficient current into the VRT pin and sink sufficient current
clock cycles plus tOD later. The ADC08200 will convert as from the VRB pin to maintain the desired voltages.
long as the clock signal is present. The output coding is
straight binary.

20017932

FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances,
the reference voltage of this circuit can vary too much for some applications.

The reference bias circuit of Figure 2 is very simple and the LM8272 was chosen because of its rail-to-rail input and
performance is adequate for many applications. However, output capability, its high current output and its ability to drive
circuit tolerances will lead to a wide reference voltage range. large capacitive loads.
Better reference stability can be achieved by driving the The divider resistors at the inputs to the amplifiers could be
reference pins with low impedance sources. changed to suit the application reference voltage needs, or
The circuit of Figure 3 will allow a more accurate setting of the divider can be replaced with potentiometers or DACs for
the reference voltages. The upper amplifier must be able to precise settings. The bottom of the ladder (VRB) may be
source the reference current as determined by the value of returned to ground if the minimum input signal excursion is
the reference resistor and the value of (VRT − VRB). The 0V.
lower amplifier must be able to sink this reference current. VRT should always be at least 1.0V more positive than VRB
Both amplifiers should be stable with a capacitive load. The to minimize noise. While VRT may be as high as the VA

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 ADC08200
Applications Information (Continued) The VRM pin is the center of the reference ladder and should
be bypassed to a quiet point in the ground plane with a 0.1
supply voltage and VRB may be as low as ground, the µF capacitor. DO NOT leave this pin open and DO NOT load
difference between these two voltages (VRT − VRB should this pin with more than 10µA.
not exceed 2.3V to prevent waveform distortion.

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FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.

2.0 THE ANALOG INPUT

The analog input of the ADC08200 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 3 pF when the clock is low, and 4 pF
when the clock is high. The sampling nature of the analog The value of "C" in the formula above should include the
input causes current spikes at the input that result in voltage ADC input capacitance when the clock is high
spikes there. Any amplifier used to drive the analog input This will provide optimum SNR performance for Nyquist
must be able to settle within the clock high time. The applications. Best THD performance is realized when the
LMH6702 and the LMH6628 have been found to be good capacitor and resistor values are both zero, but this would
amplifiers to drive the ADC08200. compromise SNR and SINAD performance. Generally, the
Figure 4 shows an example of an input circuit using the capacitor should not be added for undersampling applica-
LMH6702. Any input amplifier should incorporate some gain tions.
as operational amplifiers exhibit better phase margin and The circuit of Figure 4 has both gain and offset adjustments.
transient response with gains above 2 or 3 than with unity If you eliminate these adjustments normal circuit tolerances
gain. If an overall gain of less than 3 is required, attenuate may result in signal clipping unless care is exercised in the
the input and operate the amplifier at a higher gain, as worst case analysis of component tolerances and the input
shown in Figure 4. signal excursion is appropriately limited to account for the
The RC at the amplifier output filters the clock rate energy worst case conditions.
that comes out of the analog input due to the input sampling Full scale and offset adjustments may also be made by
circuit. The optimum time constant for this circuit depends adjusting VRT and VRB, perhaps with the aid of a pair of
not only upon the amplifier and ADC, but also on the circuit DACs.
layout and board material. A resistor value should be chosen
between 18Ω and 47Ω and the capacitor value chose ac-
cording to the formula

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ADC08200
Applications Information (Continued)

20017934

FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).

3.0 POWER SUPPLY CONSIDERATIONS 4.0 THE DIGITAL INPUT PINS

A/D converters draw sufficient transient current to corrupt The ADC08200 has two digital input pins: The PD pin and
their own power supplies if not adequately bypassed. A the Clock pin.
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a 4.1 The PD Pin
0.1 µF ceramic chip capacitor placed within one centimeter The Power Down (PD) pin, when high, puts the ADC08200
of the converter’s power supply pins. Leadless chip capaci- into a low power mode where power consumption is reduced
tors are preferred because they have low lead inductance. to about 1.4 mW with the clock running, or to about 1 mW
While a single voltage source is recommended for the VA with the clock held low. Output data is valid and accurate
and VDR supplies of the ADC08200, these supply pins about 1 microsecond after the PD pin is brought low.
should be well isolated from each other to prevent any digital The digital output pins retain the last conversion output code
noise from being coupled into the analog portions of the when either the clock is stopped or the PD pin is high.
ADC. A choke or 27Ω resistor is recommended between
these supply lines with adequate bypass capacitors close to 4.2 The ADC08200 Clock
the supply pins. Although the ADC08200 is tested and its performance is
As is the case with all high speed converters, the ADC08200 guaranteed with a 200 MHz clock, it typically will function
should be assumed to have little power supply rejection. well with clock frequencies from 10 MHz to 230 MHz.
None of the supplies for the converter should be the supply The low and high times of the clock signal can affect the
that is used for other digital circuitry in any system with a lot performance of any A/D Converter. Because achieving a
of digital power being consumed. The ADC supplies should precise duty cycle is difficult, the ADC08200 is designed to
be the same supply used for other analog circuitry. maintain performance over a range of duty cycles. While it is
No pin should ever have a voltage on it that is in excess of specified and performance is guaranteed with a 50% clock
the supply voltage or below ground by more than 300 mV, duty cycle and 200 Msps, ADC08200 performance is typi-
not even on a transient basis. This can be a problem upon cally maintained with clock high and low times of 0.65 ns and
application of power and power shut-down. Be sure that the 0.87 ns, respectively, corresponding to a clock duty cycle
supplies to circuits driving any of the input pins, analog or range of 13% to 82.5% with a 200 MHz clock. Note that
digital, do not come up any faster than does the voltage at minimum low and high times may not be simultaneously
the ADC08200 power pins. asserted.

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 ADC08200
Applications Information (Continued) The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
The CLOCK line should be series terminated at the clock external component (e.g., a filter capacitor) connected be-
source in the characteristic impedance of that line if the clock tween the converter’s input and ground should be connected
line is longer than to a very clean point in the ground plane.

where tr is the clock rise time and tprop is the propagation rate
of the signal along the trace. Typical tprop is about 150
ps/inch (59 ps/cm) on FR-4 board material.
If the clock source is used to drive more than just the
ADC08200, the CLOCK pin should be a.c. terminated with a
series RC to ground such that the resistor value is equal to
the characteristic impedance of the clock line and the ca-
pacitor value is

where tPD is the signal propagation rate down the clock line,
"L" is the line length and ZO is the characteristic impedance
of the clock line. This termination should be located as close
20017936
as possible to, but within one centimeter of, the ADC08200
clock pin. Further, this termination should be close to but
beyond the ADC08200 clock pin as seen from the clock FIGURE 5. Layout Example
source. Typical tprop is about 150 ps/inch on FR-4 board
material. For FR-4 board material, the value of C becomes Figure 5 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital compo-
nents.

6.0 DYNAMIC PERFORMANCE

Where L is the length of the clock line in inches. The ADC08200 is a.c. tested and its dynamic performance is
This termination should be located as close as possible to, guaranteed. To meet the published specifications, the clock
but within one centimeter of, the ADC08200 clock pin. source driving the CLK input must exhibit less than 2 ps
(rms) of jitter. For best a.c. performance, isolating the ADC
5.0 LAYOUT AND GROUNDING clock from any digital circuitry should be done with adequate
Proper grounding and proper routing of all signals are es- buffers, as with a clock tree. See Figure 6.
sential to ensure accurate conversion. A combined analog It is good practice to keep the ADC clock line as short as
and digital ground plane should be used. possible and to keep it well away from any other signals.
Coupling between the typically noisy digital circuitry and the Other signals can introduce jitter into the clock signal. The
sensitive analog circuitry can lead to poor performance that clock signal can also introduce noise into the analog path.
may seem impossible to isolate and remedy. The solution is
to keep all lines separated from each other by at least six
times the height above the reference plane, and to keep the
analog circuitry well separated from the digital circuitry.
The DR GND connection to the ground plane should not use
the same feedthrough used by other ground connections.
High power digital components should not be located on or
near a straight line between the ADC or any linear compo-
nent and the power supply area as the resulting common
return current path could cause fluctuation in the analog
input “ground” return of the ADC.
Generally, analog and digital lines should cross each other at 20017937

90˚ to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and FIGURE 6. Isolating the ADC Clock from Digital
digital lines altogether. Clock lines should be isolated from Circuitry
ALL other lines, analog AND digital. Even the generally
accepted 90˚ crossing should be avoided as even a little
7.0 COMMON APPLICATION PITFALLS
coupling can cause problems at high frequencies. Best per-
formance at high frequencies is obtained with a straight Driving the inputs (analog or digital) beyond the power
signal path. supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above

17 www.national.com
ADC08200
Applications Information (Continued) Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the
the supply pins. Exceeding these limits on even a transient input alternates between 3 pF and 4 pF with the clock. This
basis may cause faulty or erratic operation. It is not uncom- dynamic capacitance is more difficult to drive than is a fixed
mon for high speed digital circuits (e.g., 74F and 74AC capacitance, and should be considered when choosing a
devices) to exhibit undershoot that goes more than a volt driving device.
below ground. A 51Ω resistor in series with the offending Driving the VRT pin or the VRB pin with devices that can
digital input will usually eliminate the problem. not source or sink the current required by the ladder. As
Care should be taken not to overdrive the inputs of the mentioned in Section 1.0, care should be taken to see that
ADC08200. Such practice may lead to conversion inaccura- any driving devices can source sufficient current into the VRT
cies and even to device damage. pin and sink sufficient current from the VRB pin. If these pins
Attempting to drive a high capacitance digital data bus. are not driven with devices than can handle the required
The more capacitance the output drivers must charge for current, these reference pins will not be stable, resulting in a
each conversion, the more instantaneous digital current is reduction of dynamic performance.
required from VDR and DR GND. These large charging cur- Using a clock source with excessive jitter, using an
rent spikes can couple into the analog section, degrading excessively long clock signal trace, or having other
dynamic performance. Buffering the digital data outputs (with signals coupled to the clock signal trace. This will cause
a 74AF541, for example) may be necessary if the data bus the sampling interval to vary, causing excessive output noise
capacitance exceeds 5 pF. Dynamic performance can also and a reduction in SNR performance. The use of simple
be improved by adding 47Ω to 56Ω series resistors at each gates with RC timing is generally inadequate as a clock
digital output, reducing the energy coupled back into the source.
converter input pins.

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 Sample-and-Hold
ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter with Internal
Physical Dimensions inches (millimeters) unless otherwise noted

NOTES: UNLESS OTHERWISE SPECIFIED

REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.
24-Lead Package TC
Order Number ADC08200CIMT
NS Package Number MTC24

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.

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